CN114927509A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN114927509A
CN114927509A CN202210064434.2A CN202210064434A CN114927509A CN 114927509 A CN114927509 A CN 114927509A CN 202210064434 A CN202210064434 A CN 202210064434A CN 114927509 A CN114927509 A CN 114927509A
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China
Prior art keywords
device die
tier
tier device
die
redistribution structure
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CN202210064434.2A
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English (en)
Inventor
陈明发
郑筌安
叶松峯
胡致嘉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/229,283 external-priority patent/US12125820B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN114927509A publication Critical patent/CN114927509A/zh
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Abstract

一种方法包括将第一层器件管芯接合至载体，形成第一间隙填充区域以密封第一层器件管芯，在第一层器件管芯上方形成第一再分布结构，并且第一再分布结构电连接至第一层器件管芯，以及将第二层器件管芯接合至第一层器件管芯。第二层器件管芯位于第一层器件管芯上方，并且第二层器件管芯横向延伸超出第一层器件管芯的相应边缘。该方法还包括形成第二间隙填充区域以密封第二层器件管芯，去除载体，以及形成穿透第一间隙填充区域的介电通孔。介电通孔与第二层器件管芯重叠并且电连接至第二层器件管芯。形成第二再分布结构，其中第一再分布结构和第二再分布结构位于第一层器件管芯的相对侧上。本发明的实施例还涉及封装件及其形成方法。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
集成电路的封装件变得越来越复杂，在同一封装件中封装更多的器件管芯以实现更多的功能。例如，已经开发封装结构以在同一封装件中包括多个器件管芯，诸如处理器和存储器立方体。封装结构可以包括使用不同技术形成的器件管芯，并且具有接合至同一器件管芯的不同功能，从而形成系统。这可以节省制造成本并且优化器件性能。管芯堆叠件中的一些器件管芯可以包括用于电连接目的的硅通孔。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：将第一层器件管芯接合至第一载体；形成第一间隙填充区域以密封所述第一层器件管芯；在所述第一层器件管芯上方形成第一再分布结构，并且所述第一再分布结构电连接至所述第一层器件管芯；将第一第二层器件管芯接合至所述第一层器件管芯，其中，所述第一第二层器件管芯位于所述第一层器件管芯上方，并且所述第一第二层器件管芯横向延伸超出所述第一层器件管芯的相应边缘；形成第二间隙填充区域以密封所述第一第二层器件管芯；去除所述第一载体；形成穿透所述第一间隙填充区域的第一介电通孔，其中，所述第一介电通孔与所述第一第二层器件管芯重叠并且电连接至所述第一第二层器件管芯；以及形成第二再分布结构，其中，所述第一再分布结构和所述第二再分布结构位于所述第一层器件管芯的相对侧上。
本发明的另一实施例提供了一种封装件，包括：第一再分布结构；第一层器件管芯，位于所述第一再分布结构上方，其中，所述第一层器件管芯包括：第一半导体衬底；和第一半导体通孔，穿透所述第一半导体衬底；第一间隙填充区域，密封所述第一层器件管芯；第二再分布结构，位于所述第一层器件管芯和所述第一半导体通孔上方并且电连接至所述第一层器件管芯和所述第一半导体通孔；第一第二层器件管芯，位于所述第一层器件管芯上方并且接合至所述第一层器件管芯，其中，所述第一第二层器件管芯横向延伸超出所述第一层器件管芯的相应边缘；第二间隙填充区域，密封所述第一第二层器件管芯；以及第一介电通孔，穿透所述第一间隙填充区域，其中，所述第一介电通孔将所述第一第二层器件管芯电连接至所述第一再分布结构。
本发明的又一实施例提供了一种封装件，包括：第一再分布结构；第一器件管芯，位于所述第一再分布结构上方；第一间隙填充区域，密封所述第一器件管芯；第二器件管芯，位于所述第一器件管芯上方，其中，所述第二器件管芯横向延伸超出所述第一器件管芯的第一边缘；第二间隙填充区域，密封所述第二器件管芯；第三器件管芯，位于所述第二器件管芯上方，其中，所述第三器件管芯横向延伸超出所述第二器件管芯的第二边缘；第三间隙填充区域，密封所述第三器件管芯；第一介电通孔，位于所述第一间隙填充区域中，其中，所述第一介电通孔与所述第二器件管芯重叠并且电连接至所述第二器件管芯；以及第二介电通孔，与所述第三器件管芯重叠，其中，所述第二介电通孔穿透所述第一间隙填充区域与所述第二间隙填充区域。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图7示出了根据一些实施例的封装件的形成中的中间阶段的截面图。
图8至图14示出了根据一些实施例的封装件的形成中的中间阶段的截面图。
图15至图19示出了根据一些实施例的封装件的形成中的中间阶段的截面图。
图20示出了根据一些实施例的封装件的截面图。
图21至图24示出了根据一些实施例的封装件的形成中的中间阶段的截面图。
图25示出了根据一些实施例的封装件的截面图。
图26至图31示出了根据一些实施例的封装件的形成中的中间阶段的截面图。
图32示出了根据一些实施例的封装件的截面图。
图33和图34分别示出了根据一些实施例的包括形成阵列的器件管芯的封装件的顶视图和截面图。
图35示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开提供了许多用于实现本发明的不同特征的不同的实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示讨论的个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间相对描述符可以同样地作相应地解释。
根据一些实施例提供了封装件及其形成方法。封装件包括堆叠的器件管芯，一些器件管芯包括衬底通孔。器件管芯可以由间隙填充区域环绕，一些介电通孔穿过间隙填充区域以直接互连两个器件管芯，使得这两个器件管芯的连接不通过衬底通孔和器件管芯中的金属线与通孔。因此减小了RC延迟。本文讨论的实施例将提供示例以使得能够制造或使用本发明的主题，并且本领域普通技术人员将容易理解在保持在不同实施例的预期范围内的同时可以进行的修改。在各种视图和说明性实施例中，相同的附图标记用于表示相同的元件。虽然方法实施例可以讨论为以特定顺序执行，但是其他方法实施例可以以任何逻辑顺序执行。
图1至图7示出了根据本发明的一些实施例的封装件的形成中的中间阶段的截面图。相应的工艺也在图35所示的工艺流程中示意性地反映。
参考图1，提供了载体110。根据一些实施例，载体110是由均质材料形成的毯式载体，整个载体110由相同材料形成。载体110可以是硅载体、玻璃载体等。根据其中载体110是硅载体的一些实施例，可以由氧化硅形成或包括氧化硅的介电层112形成在载体110的顶面上以用于接合。介电层112可以通过载体110的表面层的热氧化、沉积工艺等形成。根据可选实施例，不形成介电层112。
器件管芯210放置在载体110上方并且通过管芯至晶圆接合而接合至载体110。相应的工艺示出为如图35所示的工艺流程600中的工艺602。接合可以在晶圆级。因此，多个器件管芯210(它们可以彼此相同或彼此不同)接合至载体110，但是示出了一个器件管芯210。在整个描述中，图中所示的器件管芯210和其他器件管芯可以是逻辑管芯、存储器管芯、IO管芯等。例如，逻辑管芯可以包括应用处理器(AP)管芯、图形处理单元(GPU)管芯、现场可编程门阵列(FPGA)管芯、专用集成电路(ASIC)管芯、输入-输出(IO)管芯、网络处理单元(NPU)管芯、张量处理单元(TPU)管芯、人工智能(AI)引擎管芯等。存储器管芯可以是或可以包括静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯、宽I/O存储器管芯、NAND存储器管芯、电阻随机存取存储器(RRAM)管芯、磁阻随机存取存储器(MRAM)管芯、相变随机存取存储器(PCRAM)管芯等或其他类型的易失性或非易失性存储器管芯。
器件管芯210包括衬底212。根据一些实施例，衬底212是半导体衬底，该半导体衬底可以是晶体硅衬底，同时它也可以包括其他半导体材料或可以由其他半导体材料形成，诸如硅锗、硅碳等。根据一些实施例，器件管芯210包括有源电路，有源电路包括形成在半导体衬底212的所示底面(正面)处的诸如晶体管(未示出)的有源器件。根据一些实施例，可以形成贯通孔(有时称为衬底通孔(TSV))214以延伸至衬底212中。当衬底212是硅衬底时，TSV214有时也称为硅通孔。每个TSV 214可以由隔离衬垫(未示出)环绕，该隔离衬垫由诸如氧化硅、氮化硅等的介电材料形成。隔离衬垫将相应的TSV 214与半导体衬底212隔离。TSV214延伸至半导体衬底212的顶面和底面之间的中间层级。根据一些实施例，TSV214的底面与示出的半导体衬底212的底面齐平。根据可选实施例，TSV 214进一步向下延伸至介电层216中的一个。示意性地示出导电部件218以表示前端导电部件，包括接触插塞、金属线、通孔、金属焊盘、金属柱等。
根据一些实施例，第一层器件管芯210通过熔融接合接合至载体110。例如，器件管芯210中的底部介电层可以是由氧化硅、氮氧化硅、碳氧化硅等形成的含硅介电层。当没有形成介电层112时，器件管芯210可以通过熔融接合直接接合至载体110。熔融接合可以导致生成Si-O-Si键以将器件管芯210接合至载体10。根据可选实施例，载体110可以由除硅之外的其他材料形成，诸如玻璃、有机材料等。因此，介电层112也可以是粘合层，粘合层可以是光热转换(LTHC)膜。
图2示出了密封器件管芯210的间隙填充工艺。相应的工艺示出为如图35所示的工艺流程600中的工艺604。根据一些实施例，间隙填充区域220由无机材料形成或包括无机材料。例如，间隙填充区域220的形成可以包括沉积介电衬垫(也是蚀刻停止层)和在介电衬垫上方沉积介电材料。介电衬垫可以是延伸至介电层112的顶面以及器件管芯210的侧壁和顶面的共形层。蚀刻停止层由对器件管芯210的侧壁和介电层112的顶面具有良好粘附性的介电材料形成。根据本发明的一些实施例，蚀刻停止层由诸如氮化硅的含氮化物材料形成。沉积可以包括共形沉积工艺，诸如原子层沉积(ALD)或化学气相沉积(CVD)。沉积在蚀刻停止层上的介电材料可以由氧化硅形成或包括氧化硅。根据可选实施例，间隙填充区域220由模塑料、环氧树脂、树脂等形成。执行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以使器件管芯210的背面(示出的顶面)与间隙填充区域220的顶面齐平。平坦化工艺是在暴露贯通孔214之后停止。当在所示结构的顶视图中观察时，间隙填充区域220(以及随后在上层中形成的间隙填充区域)环绕相应的器件管芯。
在随后的工艺中，执行蚀刻工艺，以使衬底212的背面凹进，使得形成凹槽，间隙填充区域220的侧壁暴露于该凹槽。贯通孔214不凹进，使得贯通孔214的端部突出于凹进的衬底212的背面。接下来，将介电材料(诸如氧化硅、氮化硅等)填充到凹槽中，接着是抛光工艺以去除介电层的过量部分，在凹槽中留下介电层226。在整个描述中，介电层216被认为是器件管芯210的部分。
贯通孔225(为介电通孔)也形成为穿透间隙填充区域220。相应的工艺示出为如图35所示的工艺流程600中的工艺606。根据一些实施例，形成工艺可以包括蚀刻间隙填充区域220以形成穿透间隙填充区域220的开口。然后将导电材料(诸如氮化钛、铜、钨等或它们的多层)填充到开口中。然后执行诸如CMP工艺或机械抛光工艺的平坦化工艺以去除导电材料的过量部分，在开口中留下贯通孔225。
图2还示出了在器件管芯210的背侧上形成背侧互连结构230。相应的工艺示出为如图35所示的工艺流程600中的工艺608。一个或多个介电层224沉积在器件管芯210和间隙填充区域220上方。介电层224也可以由无机材料形成(诸如氧化硅、氮化硅、氮氧化硅、碳氧化硅、低k材料等)或有机材料(诸如聚酰亚胺、聚苯并恶唑(PBO)等)。背侧互连结构230可以包括介电层中的RDL和接合焊盘228。虽然将单层互连结构230示出为示例，但是其中可以存在一个或多个介电层和相应的RDL/金属焊盘228。器件管芯210、间隙填充区域220和互连结构230共同形成重构晶圆232。
参考图3，第二层器件管芯310放置在重构晶圆232上方并且通过晶圆上芯片接合接合至重构晶圆232。相应的工艺示出为如图35所示的工艺流程600中的工艺610。所示的接合方案也是面对至背接合，但是可以采用其他接合方案，诸如面至面接合或背至背接合。接合可以为晶圆级。因此，虽然示出了一个器件管芯310，但适将彼此相同的多个器件管芯310接合至重构晶圆232。器件管芯310包括衬底312。根据一些实施例，器件管芯310包括位于半导体衬底312的所示底面处的有源电路。贯通孔314可以形成为延伸至衬底312的顶面和底面之间的中间层级。导电部件318形成在介电层316中以连接至有源电路。
器件管芯310通过混合接合接合至重构晶圆232，混合接合包括直接金属至金属接合和熔融接合。例如，器件管芯310中的底部介电层通过熔融接合接合至顶部介电层224，并且器件管芯310中的接合焊盘322通过直接金属至金属接合接合至接合焊盘228。
图4示出了器件管芯310的间隙填充。相应的工艺示出为如图35所示的工艺流程600中的工艺612。材料和形成工艺可以选自间隙填充区域220的相应的候选材料和候选形成工艺，并且在此不再重复细节。执行诸如CMP工艺或机械研磨工艺的平坦化工艺以使器件管芯310的背面(所示的顶面)与间隙填充区域320的顶面齐平。在暴露贯通孔314之后停止平坦化工艺。
在随后的工艺中，执行蚀刻工艺以使衬底312的背面凹进。在凹槽中形成介电层226以环绕贯通孔314的顶端部分。然后在器件管芯210的背侧上形成背侧互连结构330。相应的工艺示出为如图35所示的工艺流程600中的工艺614。背侧互连结构330可以包括一个或多个介电层324，介电层324可以由氧化硅、氮化硅、氮氧化硅、碳氧化硅、聚酰亚胺、PBO等形成。RDL/接合焊盘328形成在介电层324中。在整个描述中，器件管芯310、间隙填充区域320和互连结构330共同形成重构晶圆332。
参考图5，将第三层器件管芯410放置在重构晶圆332上方并且通过晶圆上芯片接合接合至重构晶圆332。相应的工艺示出为如图35所示的工艺流程600中的工艺616。所示的接合方案也是面至背接合，但是可以采用其他接合方案，诸如面至面接合或背至背接合。接合可以为晶圆级。因此，虽然示出了一组器件管芯410，但适将多组器件管芯410接合至重构晶圆332。一些器件管芯410可以彼此相同，并且可以与其他器件管芯410相同或不同。器件管芯410包括半导体衬底412。根据一些实施例，器件管芯410包括位于半导体衬底412的表面处的有源电路。导电部件418形成为连接至有源电路，并且形成在介电层416中。
器件管芯410通过混合接合接合至重构晶圆332，混合接合包括直接金属至金属接合和熔融接合。例如，器件管芯410中的底部介电层通过熔融接合接合至顶部介电层324，并且器件管芯410中的接合焊盘422通过直接金属至金属接合接合至接合焊盘328。
图6示出了器件管芯410的间隙填充。相应的工艺示出为如图35所示的工艺流程600中的工艺618。材料和形成工艺可以选自间隙填充区域220的相应的候选材料和候选形成工艺，并且在此不再重复细节。执行诸如CMP工艺或机械研磨工艺的平坦化工艺以使器件管芯410的背面(所示的顶面)与间隙填充区域420的顶面齐平。
在随后的工艺中，接合层424沉积在间隙填充区域420和器件管芯410的顶部上。接合层424可以是含硅介电层，含硅介电层可以由氧化硅、氮氧化硅、碳氮氧化硅等形成或包括氧化硅、氮氧化硅、氧碳氮化硅等。
接下来，执行载体更换工艺，如图7所示。相应的工艺示出为如图35所示的工艺流程600中的工艺620。载体更换工艺包括将载体510附接在重构晶圆432上。根据一些实施例，载体510由硅载体形成或包括硅载体，并且介电/接合层512形成在载体510上。介电层512可以由氧化硅或另一种含硅介电材料形成或包括氧化硅或另一种含硅介电材料。接合因此可以是熔融接合。在随后的工艺中，从重构晶圆232去除载体110。例如，当载体110由硅形成时，载体110可以通过激光提升从重构晶圆232分离，或者可以通过研磨去除。当载体110是玻璃载体并且介电层112包括LTHC时，可以通过将激光束投射到介电层112上使得层分解来执行该脱粘。
进一步参考图7，贯通孔125(为介电通孔)形成为穿透间隙填充区域220、互连结构230和间隙填充区域320。相应的工艺示出为如图35所示的工艺流程600中的工艺622。根据一些实施例，形成工艺可以包括蚀刻间隙填充区域220、介电层224和间隙填充区域320以形成开口，通过该开口暴露接合焊盘328。然后将诸如氮化钛、铜、钨等或它们的多层的导电材料填充到开口中。然后执行诸如CMP工艺或机械抛光工艺的平坦化工艺以去除导电材料的过量部分，在开口中留下贯通孔125。应该理解，通过形成直接穿透两层间隙填充区域的贯通孔125，从器件管芯410到随后形成的互连结构244的连接不需要穿过多层RDL和金属焊盘。电路径的电阻因此更小，并且RC延迟和电压降减小。
根据可选实施例，代替形成贯穿间隙填充区域220、互连结构230和间隙填充区域320的贯通孔125，每个贯通孔125分为第一间隙填充区域220中的第一贯通孔和穿透间隙填充区域320的第二贯通孔。第一贯通孔和相应的第二贯通孔通过再分布结构230中的接合焊盘/RDL 228电互连。
在形成贯通孔125之后，形成互连结构244，互连结构244包括介电层240和介电层240中的RDL 242。然后在互连结构244的底面处形成电连接件246，并且电连接件246电连接至器件管芯210和贯通孔125和225。相应的工艺示出为如图35所示的工艺流程600中的工艺624。
图7中的结构统称为重构晶圆20。可以执行分割工艺以将重构晶圆20分为多个相同的封装件20’。相应的工艺示出为图35所示的工艺流程600中的工艺626。根据一些实施例，在不去除载体510的情况下将重构晶圆20锯开，并且载体510的锯切件留在封装件20’中。根据可选实施例，在分割工艺之前去除载体510。因此，所得封装件20’的顶面可以位于介电层512的顶面层级处，或者如果去除介电层512，则位于器件管芯410的顶面的层级处。
如图7所示，器件管芯310横向延伸超出下面的器件管芯210的相应边缘。因此，贯通孔225可以与器件管芯310重叠。贯通孔225将接合焊盘228(和器件管芯310)直接连接至互连结构244，而不通过器件管芯210中的贯通孔214与金属线和通孔。贯通孔125也可以形成为将接合焊盘328(和器件管芯410)直接连接至互连结构244，而不通过器件管芯210和310中的贯通孔214和314以及金属线和通孔。因此，连接路径的电阻减小，并且RC延迟和电压降减小。根据一些实施例，贯通孔125和225可以具有比器件管芯内部的贯通孔更大的横向尺寸，并且因此可以用于提供诸如VDD和VSS的电源，而不同层的器件管芯之间的信号连接可以由器件管芯内部的贯通孔提供。例如，根据一些实施例，从互连结构244到第二层器件管芯310和第三层器件管芯410的所有电源连接可以通过诸如125和225的介电通孔，并且所有信号连接可以通过诸如214和314的半导体通孔。
器件管芯310连接至两个器件管芯410。因此，器件管芯310可以用作桥接管芯，并且在器件管芯410之间提供信号和/或电源的横向传输。信号路径可以包括金属线以及器件管芯310和410中的通孔和接合焊盘。而且，信号路径可以包括诸如开关、路由器等的数字器件，或者包括金属线/焊盘和通孔的全金属连接。
图8至图14示出了根据本发明的可选实施例的封装件的形成。这些实施例类似于图1至图7中所示的实施例，除了两个或多个第二层器件管芯310接合至一个第一层器件管芯210，并且一个第三层器件管芯410可以接合至两个第二层器件管芯310。除非另有说明，这些实施例(以及图15至图32所示的实施例)中的部件的材料和形成工艺与在图1至图7中所示的前述实施例中由相同的参考数字指代的相同的部件基本相同。因此，可以在前述实施例的讨论中找到关于图8至图32中所示的部件的形成工艺和材料的细节。
参考图8，例如，通过熔融接合或通过粘合剂，将第一层器件管芯210附接至载体110。接下来，如图9所示，形成间隙填充区域220以密封器件管芯210。然后执行平坦化工艺以使器件管芯210的顶面、贯通孔214的顶面和间隙填充区域220的顶面齐平。根据一些实施例，不同于图2所示的实施例，在此阶段没有在间隙填充区域220中形成贯通孔。根据可选实施例，与图2相同，在此阶段也可以形成贯通孔225以穿透间隙填充区域220。然后通过使半导体衬底212凹进并且将介电材料填充到产生的凹槽中来形成介电层226。接下来，在间隙填充区域220和器件管芯210上方形成包括介电层224和接合焊盘/RDL 228的互连结构230。因此形成重构晶圆232。
参考图10，例如通过混合接合将第二层器件管芯310接合至重构晶圆232。接合也可以是面之背接合，也可以采用其他接合方案。根据一些实施例，两个或多个器件管芯310接合至相同的器件管芯210。因此，器件管芯210还可以用作桥接管芯(除了它的其他功能之外)以提供器件管芯310之间的横向连接。一个或多个器件管芯310可以横向延伸超出器件管芯210的相应边缘，其中器件管芯310的一些接合焊盘322也从器件管芯210垂直偏移。
接下来，如图11所示，形成间隙填充区域320，然后平坦化间隙填充区域320，使得它们的背面与衬底312的背面共面。然后形成贯通孔325(为介电通孔)以穿透间隙填充区域320，并且连接至接合焊盘228。还形成介电层326以环绕贯通孔314的顶端部分。然后形成互连结构330，互连结构330包括介电层324和RDL/接合焊盘328。因此形成重构晶圆332。
图12示出了第三层器件管芯410的接合，第三层器件管芯410接合至两个器件管芯310。因此，根据一些实施例，器件管芯410也可以用作桥接管芯以互连两个器件管芯310。器件管芯410通过贯通孔325电连接至器件管芯210，而不通过器件管芯310中的任何半导体通孔。
图13示出了在间隙填充区域420中的器件管芯410的密封以及接合层424的形成。因此形成重构晶圆432。接下来，例如通过熔融接合将载体510附接至或接合至重构晶圆432，载体510的表面上的介电层512接合至接合层424。载体510可以是硅载体、玻璃晶圆等。载体510也可以通过粘合剂附接至重构晶圆432，而不是通过熔融接合接合至重构晶圆432。
在随后的工艺中，载体110从重构晶圆232脱粘，随后形成贯通孔225。在图14中示出了所得结构。接下来，形成互连结构244，互连结构244包括介电层240和形成RDL/接合焊盘242。还形成电连接件246以通过互连结构244电连接至贯通孔225和器件管芯210。因此形成重构晶圆20。
在随后的工艺中，分割重构晶圆20以形成多个相同的封装件20’。再次，封装件20’可以包括或不包括载体510的剩余件，并且可以包括或不包括接合层424和512的剩余件。
图15至图19示出了根据本发明的可选实施例的封装件的形成。这些实施例类似于图1至图14中所示的实施例，除了有两层(而不是三层)器件管芯。参考图15，第一层器件管芯210附接至载体110。接下来，如图16所示，形成间隙填充区域220以密封器件管芯210，随后形成介电层226。然后形成互连结构230，互连结构230包括介电层224和介电层224中的接合焊盘/RDL 228。因此形成重构晶圆232。
参考图17，例如通过混合接合将第二层器件管芯310接合至重构晶圆232。接合可以是面至背接合，但是也可以采用其他接合方案。根据一些实施例，两个或多个器件管芯310接合至相同的器件管芯210。因此，器件管芯210还可以用作桥接管芯(除了它的其他功能之外)以提供器件管芯310之间的横向连接。一个或多个器件管芯310可以横向延伸超出器件管芯210的相应边缘，其中器件管芯310的一些接合焊盘322也从器件管芯210垂直偏移。
接下来，如图18所示，形成间隙填充区域320，然后进行平坦化，使得它们的背面与衬底312的背面共面。当在顶视图中观察时，间隙填充区域320环绕器件管芯310。然后形成接合层324，接合层324为介电层。因此形成重构晶圆332。接下来，例如通过熔融接合将载体510附接至重构晶圆332，载体510的表面上的介电层512接合至接合层324。载体510可以是硅载体或玻璃晶圆。载体510也可以通过粘合剂附接至重构晶圆332，而不是通过熔融接合接合至重构晶圆332。
在随后的工艺中，载体110从重构的晶圆232脱粘，随后形成贯通孔225。在图19中示出了所得结构。接下来，形成互连结构244，互连结构244包括介电层240和形成RDL/接合焊盘242。还形成电连接件246以通过互连结构244电连接至贯通孔225和器件管芯210。因此形成重构晶圆20。
在随后的工艺中，分割重构晶圆20以形成多个相同的封装件20’。再次，封装件20’可以包括或不包括载体510的剩余件，并且可以包括或不包括介电层324和512的剩余件。
图20示出了根据可选实施例的重构晶圆20和相应的封装件20’。这些实施例类似于图19中所示的实施例，除了单个第二层器件管芯310接合至器件管芯210。再次，器件管芯310横向延伸超出器件管芯210的边缘，使得贯通孔225可以形成在器件管芯310正下方，并且互连器件管芯310和互连结构244。
图21至图24示出了根据本发明的可选实施例的封装件的形成。这些实施例类似于前述实施例，除了载体110由器件晶圆110’替换。参考图21，第二层器件管芯210通过混合接合接合至器件晶圆110’中的器件管芯110”。接合也可以是面至面接合，但是也可以采用其他接合方案。器件管芯110”还包括半导体衬底112和位于半导体衬底112的顶面处的有源电路(未示出)。此外，器件管芯110”包括介电层116、导电部件118、表面介电层124和接合焊盘128。
接下来，如图22所示，形成间隙填充区域220以密封器件管芯210，随后形成介电层226。贯通孔325也形成在间隙填充区域220中，并且电连接至接合焊盘128。然后形成互连结构230，互连结构230包括介电层224和介电层224中的接合焊盘/RDL 228。因此形成重构晶圆232。
参考图23，例如通过混合接合将第二层器件管芯310接合至重构晶圆232。接合可以是面至背接合，但是也可以采用其他接合方案。根据一些实施例，两个或多个器件管芯310接合至相同的器件管芯210。因此，器件管芯210还可以用作桥接管芯(除了它的其他功能之外)以提供器件管芯310的横向连接。一个或多个器件管芯310可以横向延伸超出器件管芯210的相应边缘，其中器件管芯310的一些接合焊盘322也从器件管芯210垂直偏移。
接下来，如图24所示，形成间隙填充区域320以密封器件管芯310，然后进行平坦化，使得它们的背面与衬底312的背面共面。可以使半导体衬底312和间隙填充区域320凹进，然后形成介电层326以环绕器件管芯310中的贯通孔314的顶端部分。
接下来，包括介电层240和RDL/接合焊盘242的互连结构244形成在器件管芯410上方并且电连接至器件管芯410。还形成电连接件246以通过互连结构244电连接至器件管芯310。因此形成重构晶圆20。在随后的工艺中，分割重构晶圆20以形成多个相同的封装件20’。
图25示出了根据可选实施例的重构晶圆20和相应的封装件20’。这些实施例类似于图24中所示的实施例，除了单个器件管芯310接合至器件管芯210。再次，器件管芯310横向延伸超出器件管芯210的边缘，使得贯通孔225可以形成在器件管芯310正下方，并且互连器件管芯310和互连结构244。
图26至图31示出了根据本发明的可选实施例的封装件的形成。这些实施例类似于如图21至图25所示的实施例(器件晶圆用于替换载体)，除了三层器件管芯堆叠在底部晶圆110’上方。参考图26，第二层器件管芯210通过混合接合堆叠在器件晶圆110’中的器件管芯110”上。接合也可以是面至面接合，但是也可以采用其他接合方案。
接下来，如图27所示，形成间隙填充区域220以密封器件管芯210，随后形成介电层226。贯通孔225也形成在间隙填充区域220中，并且电连接至接合焊盘128。然后形成互连结构230，互连结构230包括介电层224和介电层224中的接合焊盘/RDL 228。因此形成重构晶圆232。
参考图28，例如通过混合接合将第二层器件管芯310接合至重构晶圆232。接合也可以是面至背接合，但是也可以采用其他接合方案。根据一些实施例，两个或多个器件管芯310接合至相同的器件管芯210。因此，器件管芯210还可以用作桥接管芯(除了它的其他功能之外)以提供器件管芯310的横向互连。一个或多个器件管芯310可以横向延伸超出器件管芯210的相应边缘，其中器件管芯310的一些接合焊盘322也从器件管芯210垂直偏移。
接下来，如图29所示，形成间隙填充区域320，然后进行平坦化，使得它们的背面与衬底312的背面共面。在间隙填充区域320中形成贯通孔325。可以使半导体衬底312和间隙填充区域320凹进，然后形成介电层226以环绕器件管芯310中的贯通孔314的顶端部分。
图30示出了器件管芯410的接合，器件管芯410接合至两个器件管芯310。因此，根据一些实施例，器件管芯410也可以用作桥接管芯以互连两个器件管芯310。器件管芯410通过贯通孔325电连接至器件管芯210，而不通过器件管芯310中的任何半导体通孔。
图31示出了间隙填充区域420中的器件管芯410的密封。因此形成重构晶圆432。可以使半导体衬底412和间隙填充区域420凹进，然后形成介电层426以环绕器件管芯410中的贯通孔414的顶端部分。
接下来，包括介电层240和RDL/接合焊盘242的互连结构244形成在器件管芯410上方并且电连接至器件管芯410。还形成电连接件246。因此形成重构晶圆20。在随后的工艺中，分割重构晶圆20以形成多个相同的封装件20’。
图32示出了根据可选实施例的重构晶圆20和相应的封装件20’。这些实施例类似于图31中所示的实施例，除了单个器件管芯310接合至器件管芯210，并且两个器件管芯410接合至一个器件管芯310。此外，贯通孔425形成在间隙填充区域420中。在图31和图32的实施例中，器件管芯310横向延伸超出器件管芯210的边缘，使得贯通孔225可以形成在器件管芯310正下方，并且互连器件管芯310和110”。
图33和图34分别示出了示例封装件20’的部分的顶视图和截面图。根据一些实施例，多个第二层器件管芯210布置为阵列。多个第三层器件管芯310A和310B位于第二层器件管芯上方并且接合至第二层器件管芯。第三层器件管芯310B是桥接管芯，每个桥接管芯接合至两个相邻的器件管芯210。
在以上所示的实施例中，根据本发明的一些实施例讨论了一些工艺和部件以形成三维(3D)封装件。还可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或在衬底上的测试焊盘，测试焊盘允许使用探针和/或探针卡等测试3D封装或3DIC。验证测试可以对中间结构以及最终结构执行。此外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用以增加良率并且降低成本。
在以上讨论的实施例中，示出了两到四层器件管芯。根据可选实施例，可以采用更多层的器件管芯。根据一些示例实施例，底层可以包括逻辑器件管芯，诸如CPU管芯、GPU管芯等，而上层可以包括存储器器件管芯。
本发明的实施例具有一些有利特征。通过在间隙填充区域中形成介电通孔，介电通孔替代了一些半导体通孔，并且因此具有更低的电阻率。由半导体通孔和相应的金属线和通孔引起的RC延迟和电压降相应减小。
根据本发明的一些实施例，一种方法包括将第一层器件管芯接合至第一载体；形成第一间隙填充区域以密封第一层器件管芯；在第一层器件管芯上方形成第一再分布结构，并且第一再分布结构电连接至第一层器件管芯；将第一第二层器件管芯接合至第一层器件管芯，其中第一第二层器件管芯位于第一层器件管芯上方，并且第一第二层器件管芯横向延伸超出第一层器件管芯的相应边缘；形成第二间隙填充区域以密封第一第二层器件管芯；去除第一载体；形成穿透第一间隙填充区域的第一介电通孔，其中第一介电通孔与第一第二层器件管芯重叠并且电连接至第一第二层器件管芯；以及形成第二再分布结构，其中第一再分布结构和第二再分布结构位于第一层器件管芯的相对侧上。在实施例中，第一再分布结构包括介电层以及第一接合焊盘和第二接合焊盘，并且其中第一第二层器件管芯的第三接合焊盘接合至第一接合焊盘，并且第一介电通孔物理连接至第二接合焊盘。在实施例中，在形成第一再分布结构之前形成第一介电通孔。在实施例中，在形成第一再分布结构之后，并且在去除第一载体之后，形成第一介电通孔。在实施例中，该方法还包括在去除第一载体之前，在第一第二层器件管芯上方接合第二载体。在实施例中，该方法还包括将第二第二层器件管芯接合至第一层器件管芯，其中第二第二层器件管芯位于第一层器件管芯上方，并且第一层器件管芯将第一第二层器件管芯电桥接至第二第二层器件管芯。在实施例中，第一再分布结构是单层再分布结构，包括单层电介质；以及接合焊盘，接合焊盘的第一顶面和第一底面与单层电介质的相应的第二顶面和第二底面共面。在实施例中，该方法还包括将第三层器件管芯接合至第一第二层器件管芯，其中第三层器件管芯位于第一第二层器件管芯上方，并且第三层器件管芯横向延伸超出第一第二层器件管芯的相应边缘；以及形成第三间隙填充区域以密封第三层器件管芯。在实施例中，该方法还包括形成第二介电通孔以穿透第一间隙填充区域、第一再分布结构和第二间隙填充区域。在实施例中，第二介电通孔着陆在第二再分布结构中的金属焊盘上。
根据本发明的一些实施例，封装件包括第一再分布结构；第一层器件管芯，位于第一再分布结构上方，其中第一层器件管芯包括：第一半导体衬底；以及第一半导体通孔，穿透第一半导体衬底；第一间隙填充区域，密封第一层器件管芯；第二再分布结构，位于第一层器件管芯和第一半导体通孔上方并且电连接至第一层器件管芯和第一半导体通孔；第一第二层器件管芯，位于第一层器件管芯上方并且接合至第一层器件管芯，其中第一第二层器件管芯横向延伸超出第一层器件管芯的相应边缘；第二间隙填充区域，密封第一第二层器件管芯；以及第一介电通孔，穿透第一间隙填充区域，其中第一介电通孔将第一第二层器件管芯电连接至第一再分布结构。在实施例中，第一介电通孔与第一第二层器件管芯重叠。在实施例中，该封装件还包括位于第一第二层器件管芯上方并且接合至该第一第二层器件管芯的第三层器件管芯，其中该第三层器件管芯进一步横向延伸超出第一第二层器件管芯的相应边缘；以及第三间隙填充区域，密封第三层器件管芯。在实施例中，封装件还包括穿透第一间隙填充区域、第二再分布结构和第二间隙填充区域的第二介电通孔。在实施例中，第二介电通孔包括连续延伸至第一间隙填充区域、第二再分布结构和第二间隙填充区域中的部分，并且在该部分中没有界面。在实施例中，封装件还包括穿透第二间隙填充区域的第二介电通孔，其中第二介电通孔与第一层器件管芯重叠并且电连接至第一层器件管芯。
根据本发明的一些实施例，封装件包括第一再分布结构；第一器件管芯，位于第一再分布结构上方；第一间隙填充区域，密封第一器件管芯；第二器件管芯，位于第一器件管芯上方，其中第二器件管芯横向延伸超出第一器件管芯的第一边缘；第二间隙填充区域，密封第二器件管芯；第三器件管芯，位于第二器件管芯上方，其中第三器件管芯横向延伸超出第二器件管芯的第二边缘；第三间隙填充区域，密封第三器件管芯；第一介电通孔，位于第一间隙填充区域中，其中第一介电通孔与第二器件管芯重叠并且电连接至第二器件管芯；以及第二介电通孔，与第三器件管芯重叠，其中第二介电通孔穿透第一间隙填充区域与第二间隙填充区域。在实施例中，第二介电通孔包括连续延伸穿过第一间隙填充区域和第二间隙填充区域的部分，在该部分中没有界面。在实施例中，第二介电通孔具有第一顶端和比第一顶端宽的第一底端。在实施例中，第一介电通孔具有第二顶端和比第二顶端窄的第二底端。
前面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基底来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同配置不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成封装件的方法，包括：
将第一层器件管芯接合至第一载体；
形成第一间隙填充区域以密封所述第一层器件管芯；
在所述第一层器件管芯上方形成第一再分布结构，并且所述第一再分布结构电连接至所述第一层器件管芯；
将第一第二层器件管芯接合至所述第一层器件管芯，其中，所述第一第二层器件管芯位于所述第一层器件管芯上方，并且所述第一第二层器件管芯横向延伸超出所述第一层器件管芯的相应边缘；
形成第二间隙填充区域以密封所述第一第二层器件管芯；
去除所述第一载体；
形成穿透所述第一间隙填充区域的第一介电通孔，其中，所述第一介电通孔与所述第一第二层器件管芯重叠并且电连接至所述第一第二层器件管芯；以及
形成第二再分布结构，其中，所述第一再分布结构和所述第二再分布结构位于所述第一层器件管芯的相对侧上。
2.根据权利要求1所述的方法，其中，所述第一再分布结构包括介电层以及第一接合焊盘和第二接合焊盘，并且其中，所述第一第二层器件管芯的第三接合焊盘接合至所述第一接合焊盘，并且所述第一介电通孔物理连接至所述第二接合焊盘。
3.根据权利要求1所述的方法，其中，在形成所述第一再分布结构之前形成所述第一介电通孔。
4.根据权利要求1所述的方法，其中，在形成所述第一再分布结构之后，并且在去除所述第一载体之后，形成所述第一介电通孔。
5.根据权利要求1所述的方法，还包括在去除所述第一载体之前，在所述第一第二层器件管芯上方接合第二载体。
6.根据权利要求1所述的方法，还包括将第二第二层器件管芯接合至所述第一层器件管芯，其中，所述第二第二层器件管芯位于所述第一层器件管芯上方，并且所述第一层器件管芯将所述第一第二层器件管芯电桥接至所述第二第二层器件管芯。
7.根据权利要求1所述的方法，其中，所述第一再分布结构是单层再分布结构，包括：
单层电介质；以及
接合焊盘，所述接合焊盘的第一顶面和第一底面与所述单层电介质的相应的第二顶面和第二底面共面。
8.根据权利要求1所述的方法，还包括：
将第三层器件管芯接合至所述第一第二层器件管芯，其中，所述第三层器件管芯位于所述第一第二层器件管芯上方，并且所述第三层器件管芯横向延伸超出所述第一第二层器件管芯的相应边缘；以及
形成第三间隙填充区域以密封所述第三层器件管芯。
9.一种封装件，包括：
第一再分布结构；
第一层器件管芯，位于所述第一再分布结构上方，其中，所述第一层器件管芯包括：
第一半导体衬底；和
第一半导体通孔，穿透所述第一半导体衬底；
第一间隙填充区域，密封所述第一层器件管芯；
第二再分布结构，位于所述第一层器件管芯和所述第一半导体通孔上方并且电连接至所述第一层器件管芯和所述第一半导体通孔；
第一第二层器件管芯，位于所述第一层器件管芯上方并且接合至所述第一层器件管芯，其中，所述第一第二层器件管芯横向延伸超出所述第一层器件管芯的相应边缘；
第二间隙填充区域，密封所述第一第二层器件管芯；以及
第一介电通孔，穿透所述第一间隙填充区域，其中，所述第一介电通孔将所述第一第二层器件管芯电连接至所述第一再分布结构。
10.一种封装件，包括：
第一再分布结构；
第一器件管芯，位于所述第一再分布结构上方；
第一间隙填充区域，密封所述第一器件管芯；
第二器件管芯，位于所述第一器件管芯上方，其中，所述第二器件管芯横向延伸超出所述第一器件管芯的第一边缘；
第二间隙填充区域，密封所述第二器件管芯；
第三器件管芯，位于所述第二器件管芯上方，其中，所述第三器件管芯横向延伸超出所述第二器件管芯的第二边缘；
第三间隙填充区域，密封所述第三器件管芯；
第一介电通孔，位于所述第一间隙填充区域中，其中，所述第一介电通孔与所述第二器件管芯重叠并且电连接至所述第二器件管芯；以及
第二介电通孔，与所述第三器件管芯重叠，其中，所述第二介电通孔穿透所述第一间隙填充区域与所述第二间隙填充区域。
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