TWI816138B - 計算系統封裝及其形成方法 - Google Patents

計算系統封裝及其形成方法 Download PDF

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TWI816138B
TWI816138B TW110121573A TW110121573A TWI816138B TW I816138 B TWI816138 B TW I816138B TW 110121573 A TW110121573 A TW 110121573A TW 110121573 A TW110121573 A TW 110121573A TW I816138 B TWI816138 B TW I816138B
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Taiwan
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dies
logic
memory
bridge
die
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TW110121573A
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TW202243035A (zh
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余振華
陳頡彥
王垂堂
蔡仲豪
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台灣積體電路製造股份有限公司
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Abstract

本發明提供一種方法，包含形成重建構晶圓，形成重建構 晶圓包含：在載體之上形成重佈線結構；在重佈線結構之上接合第一多個記憶體晶粒；在重佈線結構之上接合多個橋接晶粒；以及在第一多個記憶體晶粒及多個橋接晶粒之上接合多個邏輯晶粒。多個橋接晶粒中的每一者使多個邏輯晶粒中的四者內連且與所述四者的拐角區交疊。在多個邏輯晶粒之上接合第二多個記憶體晶粒。多個邏輯晶粒形成第一陣列，且第二多個記憶體晶粒形成第二陣列。

Description

計算系統封裝及其形成方法
本發明的實施例是有關於計算系統封裝及計算系統封裝的形成方法。
積體電路的封裝正變得愈發複雜，其中將更多裝置晶粒整合於同一封裝中以達成更多功能。舉例而言，系統封裝已經開發成包含同一封裝中的諸如處理器及記憶體塊的多個裝置晶粒。在系統封裝中，使用不同技術形成且具有不同的功能的裝置晶粒可以2D並列及3D堆疊方式接合，以形成具有高計算效率、高頻寬、高功能封裝密度、低通信延遲以及每位元資料低能量消耗的系統。
本發明實施例的一種計算系統封裝的形成方法包括：形成重建構晶圓。形成重建構晶圓包括：在載體之上形成重佈線結構；在所述重佈線結構之上接合第一多個記憶體晶粒；在所述重佈線結構之上接合多個橋接晶粒；在所述第一多個記憶體晶粒及所述多個橋接晶粒之上接合多個邏輯晶粒，其中所述多個橋接晶粒中的每一者使所述多個邏輯晶粒中的四者內連且與所述四者的拐 角區交疊；以及在所述多個邏輯晶粒之上接合第二多個記憶體晶粒，其中所述多個邏輯晶粒形成第一陣列，且所述第二多個記憶體晶粒形成第二陣列。
本發明實施例的一種計算系統封裝。所述計算系統封裝包括重佈線結構、第一多個記憶體晶粒、多個橋接晶粒、多個邏輯晶粒及第二多個記憶體晶粒。所述第一多個記憶體晶粒位於所述重佈線結構之上。所述多個橋接晶粒位於所述重佈線結構之上。所述多個邏輯晶粒位於所述第一多個記憶體晶粒及所述多個橋接晶粒之上，其中所述多個橋接晶粒中的每一者使所述多個邏輯晶粒中的至少兩者內連且與所述至少兩者的拐角區交疊。所述第二多個記憶體晶粒位於所述多個邏輯晶粒之上且接合至所述多個邏輯晶粒，其中所述多個邏輯晶粒形成第一陣列，且所述第二多個記憶體晶粒形成第二陣列。
本發明實施例的一種計算系統封裝。所述計算系統封裝包括重建構晶圓。所述重建構晶圓包括重佈線結構、多個橋接晶粒、多個邏輯晶粒及多個記憶體晶粒。所述重佈線結構包括多條重佈線。所述多個橋接晶粒位於所述重佈線結構之上且接合至所述重佈線結構。所述多個邏輯晶粒位於所述多個橋接晶粒之上且接合至所述多個橋接晶粒，其中所述多個橋接晶粒中的至少一者接合至所述多個邏輯晶粒中的四者的拐角區。所述多個記憶體晶粒位於所述多個邏輯晶粒之上且接合至所述多個邏輯晶粒，其中所述多個記憶體晶粒接合至所述多個邏輯晶粒。
20、20A、20B、20C:半導體基底
22:內連線結構
26A、26B:基底穿孔
28、28A、28B、122、124A、124B、142:電連接件
30:表面介電層
34:橋接結構
36:電學路徑
42:被動裝置/深溝渠電容器
42A、43A:絕緣體
42B、43B:電容器電極
43:被動裝置/金屬絕緣體金屬電容器
50:內連線結構/重佈線結構
54、108、116、126A、126B:介電層
100:計算系統封裝/重建構晶圓
102:載體
104:釋放膜
106、112:重佈線(RDL)
110:開口/通孔開口
112L:RDL線/跡線/跡線部分
112V:通孔部分/通孔
114:導電凸塊/凸塊下金屬
114A:導電凸塊
120:穿孔/模塑穿孔/金屬支柱
130、132、134:密封體
130A、132A、134A:基礎材料
130B、132B、134B:填充劑顆粒/球形顆粒
131、133、135:重建構晶圓
141:切割道
144:封裝組件
146:底膠
148:封裝
150:區
152:連接件
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224、226、228、230:製程
A-A、B-B、1A-1A、1F-1F、1G-1G:參考橫截面
BD:橋接晶粒/裝置晶粒/晶粒
BD1、BD2:橋接晶粒
LD:邏輯晶粒/晶粒
MD1:記憶體晶粒/裝置晶粒/晶粒
MD3:記憶體晶粒/晶粒
MD1':記憶體堆疊/記憶體晶粒堆疊
MD3':記憶體堆疊/晶粒堆疊/記憶體晶粒堆疊
當結合隨附圖式閱讀時，自以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，出於論述清楚的目的，可任意地增大或減小各種特徵的尺寸。
圖1A、圖1B、圖1C、圖1D、圖1E、圖1F以及圖1G示出根據一些實施例的計算系統封裝的橫截面圖、透視圖以及俯視圖及仰視圖。
圖2至圖14示出根據一些實施例的形成計算系統封裝的中間階段的橫截面圖。
圖15A、圖15B、圖15C、圖16A、圖16B、圖16C、圖17A、圖17B以及圖17C示出根據一些實施例的計算系統封裝的橫截面圖。
圖18A及圖18B示出根據一些實施例的計算系統封裝的俯視圖及仰視圖。
圖19A、圖19B、圖20A、圖20B、圖21A、圖21B、圖22A以及圖22B示出根據一些實施例的計算系統封裝的橫截面圖。
圖23示出根據一些實施例的晶粒對晶圓接合製程的透視圖。
圖24示出根據一些實施例的晶圓對晶圓接合製程的透視圖。
圖25示出根據一些實施例的橋接晶粒中的內連線結構的一部分。
圖26示出根據一些實施例的橋接晶粒中的電容器。
圖27示出根據一些實施例的計算系統封裝中的密封體的放大視圖。
圖28示出根據一些實施例的用於形成計算系統封裝的製程 流程。
以下揭露內容提供用於實施本發明的不同特徵的許多不同的實施例或實例。下文描述組件及配置的特定實例以簡化本揭露。當然，這些僅為實例且不意欲為限制性的。舉例而言，在以下描述中，在第二特徵之上或上形成第一特徵可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含可在第一特徵與第二特徵之間形成額外特徵使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號裝置及/或字母。此重複是出於簡單及清晰的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
此外，為易於描述，本文中可使用諸如「在......之下」、「在......下方」、「下部」、「上覆」、「上部」以及類似者的空間相對術語來描述如圖式中所示出的一個元件或特徵與另一元件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋裝置在使用或操作中的不同定向。裝置可另外定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據各種實施例，提供一種計算系統封裝及其形成方法。計算系統封裝可包含三個層級(tier)，其中中間層級包含多個邏輯晶粒，且底部層級及頂部層級包含多個記憶體晶粒。因此，邏輯晶粒具有至其存取的記憶體晶粒的最短路徑。多個橋接晶粒處於底部層級中，且用於使多個邏輯晶粒內連。因此多個邏輯晶粒中的每 一者具有對其他多個邏輯晶粒及多個記憶體晶粒的最大化存取，而不會增加系統的複雜度。此外，歸因於採用邏輯晶粒、記憶體晶粒以及橋接晶粒的陣列，系統的可縮放性(scalability)得以改良。藉由此設定，可改善計算效率，可增加系統的頻寬，且可由於記憶體晶粒及邏輯晶粒的緊密近接以及有效佈局而減小延遲。根據一些實施例，示出形成封裝的多個中間階段。論述一些實施例的一些變化。貫穿各種視圖及說明性實施例，相同的附圖標號用以指定相同元件。
圖1A、圖1B、圖1C、圖1D、圖1E、圖1F以及圖1G示出根據一些實施例的計算系統封裝100的橫截面圖、透視圖以及俯視圖及仰視圖。計算系統封裝100包含分佈於包含層級1、層級2以及層級3的多個層級中的多個邏輯晶粒、多個記憶體晶粒以及多個橋接晶粒，所述晶粒分別密封於密封體130、密封體132以及密封體134中。層級1可包含多個記憶體晶粒(亦稱為裝置晶粒、晶粒)MD1及多個橋接晶粒(亦稱為裝置晶粒、晶粒)BD。層級2可包含多個邏輯晶粒(亦稱為晶粒)LD。層級3可包含多個記憶體晶粒(亦稱為晶粒)MD3。邏輯晶粒LD執行計算功能，且邏輯晶粒LD存取記憶體晶粒MD1及記憶體晶粒MD3。在本揭露的圖式中，裝置晶粒的附圖標號可以符號「LD」、符號「MD」或符號「BD」開始。符號「LD」用於表示對應晶粒為邏輯晶粒。符號「MD1」用於表示對應晶粒為層級1中的記憶體晶粒，且符號「MD3」用於表示對應晶粒為層級3中的記憶體晶粒。記憶體晶粒MD1及記憶體晶粒MD3統稱為記憶體晶粒MD。字母「BD」用於表示對應晶粒為橋接晶粒。在層級1、層級2以及層級3中的 每一者中，邏輯晶粒的數目及記憶體晶粒的數目可超過所示出的數目。應理解，儘管繪示三個層級的封裝作為實例，但計算系統封裝可包含超過三個層級，諸如四個層級、五個層級或更多個層級，且新增層級可位於所示出層級1下方及/或所示出層級3之上。
根據本揭露的一些實施例，邏輯晶粒LD可為應用處理器(Application Processor；AP)晶粒、圖形處理單元(Graphics Processing Unit；GPU)晶粒、現場可程式化閘陣列(Field Programmable Gate Array；FPGA)晶粒、特殊應用積體電路(Application Specific Integrated Circuit；ASIC)晶粒、輸入輸出(Input-Output；IO)晶粒、網路處理單元(Network Processing Unit；NPU)晶粒、張量處理單元(Tensor Processing Unit；TPU)晶粒、人工智慧(Artificial Intelligence；AI)引擎晶粒或類似者。
根據本揭露的一些實施例，記憶體晶粒MD1及記憶體晶粒MD3可包含靜態隨機存取記憶體(Static Random Access Memory；SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)晶粒、寬I/O記憶體晶粒、反及記憶體晶粒(NAND Memory die)、電阻式隨機存取記憶體(Resistive Random Access Memory；RRAM)晶粒、磁阻式隨機存取記憶體(Magneto-resistive Random Access Memory；MRAM)晶粒、相變隨機存取記憶體(Phase Change Random Access Memory；PCRAM)晶粒、或類似者，或其他類型的揮發性記憶體晶粒或非揮發性記憶體晶粒。記憶體晶粒中可包含或可不含控制器。在記憶體晶粒並不包含控制器的實施例中，控制器可建構於邏輯晶粒中。記憶體晶粒亦可呈單個記憶體晶粒或預先堆疊的記憶體塊形式。
在計算系統封裝100中，及可能在多個層級中的每一者中，可混合不同類型的記憶體晶粒。舉例而言，層級1可採用如前述的一種類型的記憶體晶粒，且層級3可採用另一類型的記憶體晶粒。然而，層級1中的所有記憶體晶粒可屬於相同類型且彼此相同，且層級3中的所有記憶體晶粒可屬於相同類型且彼此相同，以便改良系統的可縮放性且減小封裝的厚度(由於若混合了不同類型，則對應層級的厚度由最厚類型來判定)。層級2中的多個邏輯晶粒LD可包含不同類型的邏輯晶粒，所述不同類型的邏輯晶粒可包含前述邏輯晶粒。替代地，層級2中的所有邏輯晶粒可屬於同一類型且彼此相同。
層級1可包含多個記憶體晶粒MD1及多個橋接晶粒BD，且可含或可不含其他類型的晶粒，諸如邏輯晶粒、非相依被動裝置晶粒以及類似者。層級2可包含多個邏輯晶粒LD，且可含或可不含其他類型的晶粒，諸如記憶體晶粒、橋接晶粒、被動裝置晶粒以及類似者。層級3可包含多個記憶體晶粒MD3，且可含或可不含其他類型的晶粒，諸如邏輯晶粒、橋接晶粒、被動裝置晶粒以及類似者。
邏輯晶粒LD、記憶體晶粒MD1/記憶體晶粒MD3以及橋接晶粒BD中的每一者可包含可為矽基底的半導體基底20A、半導體基底20B或半導體基底20C。內連線結構22形成於對應的半導體基底20A/半導體基底20B/半導體基底20C上，且用於使對應的晶粒中的多個裝置內連線。基底穿孔26A及基底穿孔26B可形成為穿透層級1的多個晶粒及層級2的多個晶粒的對應的半導體基底20，且用於上覆組件至下伏組件的內連。此外，多個電連接件 28可形成為用於接合至其他裝置晶粒。電連接件28用於不同層級中的晶粒之間的接合，且可為金屬接墊、金屬柱、焊料區或類似者。根據一些實施例，電連接件28為金屬柱(諸如銅柱)，且位於對應的表面介電層30中。根據一些實施例，表面介電層30由氧化矽形成或包括氧化矽。根據其他實施例，表面介電層30包含聚合物，諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯環丁烷(benzocyclobutene；BCB)或類似者。貫穿描述，具有內連線結構22(及諸如電晶體的主動裝置，未繪示)的半導體基底20的一側被稱為前側(或「正面」)，且相對側稱為背側(或「背面」)。因此，取決於晶粒以哪些側彼此接合，接合可為面對背接合、面對面接合、背對背接合。舉例而言，在圖1A中，採用面對背接合。
另外再次參考圖1A、圖1F或圖1G，相鄰層級經由直接金屬-金屬接合、焊料接合或混合接合而彼此接合。混合接合包含介電質-介電質接合(亦稱為熔融接合(fusion bonding)，其中Si-O-Si接合可形成於兩個接合的介電層之間)及金屬-金屬接合。
下伏於層級1的晶粒可具有內連線結構(重佈線結構)50。重佈線結構50可包含介電層54、介電層108以及介電層116、RDL 106及RDL 112以及多個凸塊下金屬(Under-Bump Metallurgies；UBM)(亦稱為導電凸塊)114。可包含焊料區、金屬柱、微凸塊或類似者的多個電連接件142形成於重佈線結構50的底部表面處。
圖1B及圖1C分別示出如圖1A中所繪示的計算系統封裝100的俯視圖及仰視圖。計算系統封裝100的橫截面可參考圖 1A、圖1F以及圖1G所見，其中圖1A示出圖1B及圖1C中的參考橫截面1A-1A，圖1F示出圖1B及圖1C中的參考橫截面1F-1F，且圖1G示出圖1B及圖1C中的參考橫截面1G-1G。如圖1B中所繪示，記憶體晶粒MD1及橋接晶粒BD示出為虛線，此是由於其位於邏輯晶粒LD下方。根據一些實施例，多個記憶體晶粒MD3可配置為陣列。多個邏輯晶粒LD可配置為陣列。多個橋接晶粒BD可配置為陣列，且多個記憶體晶粒MD1亦可為佈置為陣列。儘管3×3陣列示出為實例，但可形成更大陣列。使裝置晶粒形成為陣列具有高可縮放性的有利特徵。此對經由添加更多的邏輯晶粒、記憶體晶粒以及橋接晶粒來增加計算能力尤其有用。如後續段落中將論述，邏輯晶粒的協同操作可經由共用記憶體晶粒以及經由橋接晶粒進行相互作用來達成，使得按比例擴大系統及提高計算能力可易於藉由放大裝置陣列來達成。
根據一些實施例，所有邏輯晶粒LD彼此相同。根據替代實施例，一些邏輯晶粒LD彼此相同，且與彼此亦相同的其他邏輯晶粒LD不同。舉例而言，第一多個邏輯晶粒LD可彼此相同，且第二多個邏輯晶粒LD可彼此相同且與第一多個邏輯晶粒LD不同。第一多個邏輯晶粒LD及第二多個邏輯晶粒LD可按交替佈局佈置，例如在陣列的多個列及多個行中的每一者中交替。
根據一些實施例，多個記憶體晶粒MD3中的每一者接合至多個邏輯晶粒LD中的一者且由多個邏輯晶粒LD中的一者訊號地存取。多個記憶體晶粒MD1中的每一者接合至亦繪示於圖1G中的兩個相鄰的邏輯晶粒LD且由所述邏輯晶粒LD訊號地存取。藉由此佈局，每一邏輯晶粒可在其間沒有佈線的情況下直接存取 三個記憶體晶粒。此顯著地增加由邏輯晶粒存取的記憶體的數量而不增加功率消耗及延遲。
進一步參考圖1B及圖1C，多個橋接晶粒BD中的每一者接合至四個邏輯晶粒LD且使所述四個邏輯晶粒LD內連。橋接晶粒BD用於使四個連接的邏輯晶粒彼此內部通信。舉例而言，橋接晶粒BD中可包含多條導線，所述導線使四個邏輯晶粒LD中的每一對直接內連。橋接晶粒BD亦可包含網路連接電路(networking circuit)(且因此可為晶片上網路連接晶粒(networking-on-chip die))以用於切換四個邏輯晶粒中的每一對之間的訊號，所述網路連接電路包含開關、路由器電路或類似者。因此，經由橋接晶粒BD，所有四個邏輯晶粒LD可充當整合系統。此外，多個邏輯晶粒LD中的每一者連接至四個橋接晶粒，且因此可將訊號自四個橋接晶粒中的任一者路由至另一者。因此，所有邏輯晶粒LD可(經由多個橋接晶粒BD)彼此起作用以形成整合計算系統並達成並行計算。如可自圖1B及圖1C構想，計算系統封裝100可藉由複製及放大邏輯晶粒LD、記憶體晶粒MD1及記憶體晶粒MD3以及橋接晶粒BD的陣列而按比例擴大以改良計算能力。
圖1D及圖1E示出根據一些實施例的計算系統封裝100的透視圖，且圖1D示出頂側透視圖，且圖1E示出底側透視圖。
圖1F示出如圖1B及圖1C中所繪示的參考橫截面1F-1F。記憶體晶粒MD1未繪示於圖1F中，此是由於記憶體晶粒MD1不在所示出橫截面中。示出連接至同一橋接晶粒BD的兩個邏輯晶粒LD，但並未示出連接至同一橋接晶粒BD的另外兩個邏輯晶粒LD，此是由於其不在所示出橫截面中。
圖25示意性地示出包含用於使多個邏輯晶粒LD內連的橋接結構34的橋接晶粒BD。根據一些實施例，橋接結構34形成於橋接晶粒BD的內連線結構22中。舉例而言，內連線結構22可包含多個介電層(有時稱為金屬間介電質(Inter-Metal Dielectric；IMD))，所述介電層可包含低k介電材料。橋接結構34可包含可延伸至內連線結構22中的多個金屬化層中的多條金屬線及多個通孔。金屬線及通孔經內連以形成多個電學路徑36，其中多個電學路徑36中的每一者的相對末端連接至可包含金屬接墊、金屬柱、焊料區或類似者的電連接件28A。邏輯晶粒LD具有接合至多個電連接件28A的多個電連接件28B。橋接結構34亦可包含數位開關、路由器或類似者，所述數位開關、路由器或類似者可包含電學路徑及開關(其包含主動裝置，諸如電晶體及控制電路)。
返回參考圖1F，橋接晶粒BD亦可包含被動裝置(亦稱為深溝渠電容器)42/被動裝置(亦稱為金屬絕緣體金屬(Metal-Insulator-Metal；MIM)電容器)43，諸如電容器、電阻器、電感器或類似者。圖26示出橋接晶粒BD的實例。根據一些實施例，橋接晶粒BD包含深溝渠電容器42及/或MIM電容器43。深溝渠電容器42可包含多個電容器電極42B及在多個電容器電極42B之間的絕緣體42A，其中深溝渠電容器42延伸至半導體基底20中所形成的溝渠中，使得電容可增加。MIM電容器43可包含多個電容器電極43B及在多個電容器電極43B之間的絕緣體43A，且可形成於橋接晶粒BD中的內連線結構22中。根據一些實施例，MIM電容器43及電學路徑36(圖25)延伸至橋接晶粒BD中的同一內連線結構22中。
圖1G示出如圖1B及圖1C中所繪示的參考橫截面1G-1G。橋接晶粒BD未繪示於圖1G中，此是由於橋接晶粒BD不在所示出橫截面中。
如圖1A、圖1F以及圖1G中所繪示，多個基底穿孔26A形成於多個記憶體晶粒MD1及多個橋接晶粒BD中，且穿透所述記憶體晶粒MD1及所述橋接晶粒BD的半導體基底20A。基底穿孔26A用於將重佈線結構50電性且訊號耦接至邏輯晶粒LD。如圖1F及圖1G中所繪示，多個穿孔120(模塑穿孔(through-molding via))形成為穿透密封體130，且用於將重佈線結構50電性且訊號耦接至邏輯晶粒LD。
圖2至圖14示出根據本揭露的一些實施例的形成如圖1A、圖1B、圖1C、圖1D、圖1E、圖1F以及圖1G中所繪示的計算系統封裝100的中間階段的橫截面圖。根據一些實施例，如圖2至圖14中所繪示，採用RDL在先(其中「RDL」表示「重佈線」)的方法，其中重佈線結構50(圖1A)在置放及接合晶粒之前形成。對應製程亦示意性地反映於圖28中所繪示的製程流程中。根據替代實施例，可採用RDL在後方法，其中首先置放及接合晶粒，且接著形成重佈線結構50。
圖2示出載體102及形成於載體102上的釋放膜104。載體102可為玻璃載體、矽晶圓、有機載體或類似者。載體102可具有根據一些實施例的圓形俯視形狀。釋放膜104可由聚合物類材料(諸如光-熱轉換(Light-To-Heat-Conversion；LTHC)材料)形成，所述聚合物類材料能夠在諸如雷射光束的載熱輻射下分解，使得載體102可自將在後續製程中形成的上覆結構剝離。根據本 揭露的一些實施例，釋放膜104由塗佈至載體102上的環氧樹脂類熱釋放材料形成。
多個介電層及多個RDL形成於釋放膜104之上，如圖2至圖5中所繪示。參考圖2，介電層54形成於釋放膜104上。根據本揭露的一些實施例，介電層54由聚合物形成，所述聚合物亦可為可使用包含曝光製程及顯影製程的光微影製程進行圖案化的感光性材料，諸如聚苯并噁唑(PBO)、聚醯亞胺、苯環丁烷(BCB)或類似者。
根據一些實施例，多條重佈線(Redistribution Line；RDL)106形成於介電層54之上。各別製程示出為如圖28中所繪示的製程流程200中的製程202。形成多條RDL 106可包含在介電層54之上形成金屬晶種層(未繪示)、在金屬晶種層之上形成諸如光阻的圖案化罩幕(未繪示)且接著對經暴露的晶種層執行金屬電鍍製程。接著移除圖案化罩幕及晶種層的由圖案化罩幕覆蓋的部分，從而留下如圖2中所繪示的多條RDL 106。根據本揭露的一些實施例，晶種層包含鈦層及鈦層之上的銅層。可使用例如物理氣相沈積(physical vapor deposition；PVD)或類似製程來形成晶種層。可使用例如電化學鍍敷製程或無電極電鍍製程來執行電鍍。
參考圖3，於多條RDL 106上形成介電層108。各別製程示出為如圖28中所繪示的製程流程200中的製程204。介電層108的底部表面與多條RDL 106及介電層54的頂部表面接觸。根據本揭露的一些實施例，介電層108由聚合物形成，所述聚合物可為諸如PBO、聚醯亞胺、BCB或類似者的感光性材料。替代地，介電層108可包含非有機介電材料，諸如氧化矽、氮化矽、碳化矽、 氮氧化矽或類似者。接著圖案化介電層108以在其中形成多個開口(亦稱為通孔開口)110。多條RDL 106的一些部分經由介電層108中的多個開口110暴露。
接著，參考圖4，多條RDL 112形成為連接至多條RDL 106。各別製程示出為如圖28中所繪示的製程流程200中的製程206。多條RDL 112包含介電層108之上的多條金屬跡線(金屬線)。多條RDL 112亦包含延伸至介電層108中的多個開口110中的多個通孔。多條RDL 112亦可藉由電鍍製程形成，其中多條RDL 112中的每一者包含晶種層(未繪示)及晶種層之上的經電鍍金屬材料。根據一些實施例，形成多條RDL 112可包含沈積延伸至多個通孔開口中的毯覆式金屬晶種層，以及形成第一電鍍罩幕(諸如光阻)且將其圖案化，其中多個開口形成於多個通孔開口之上且結合所述通孔開口。接著執行電鍍製程以電鍍金屬材料，所述金屬材料完全填充多個通孔開口110(圖3)且具有高於介電層108的頂部表面的一些部分。接著移除第一電鍍罩幕。
金屬晶種層及經電鍍材料可由相同材料或不同材料形成。RDL 112中的金屬材料可包含金屬或金屬合金，所述金屬合金包含銅、鋁、鎢或其合金。多條RDL 112包含多條RDL線(亦稱為多條跡線或多個跡線部分)112L及多個通孔部分(亦稱為多個通孔)112V，其中多個跡線部分112L位於介電層108之上，且多個通孔部分112V位於介電層108中。由於跡線部分112L及通孔部分(亦稱為通孔)112V在相同電鍍製程中形成，因此在通孔112V與對應的上覆跡線部分112L之間不存在可區分界面。此外，多個通孔112V中的每一者可具有錐形輪廓(tapered profile)，其中上 部部分比對應的下部部分寬。
進一步參考圖4，多個導電凸塊114形成於多條RDL 112上。各別製程示出為如圖28中所繪示的製程流程200中的製程208。應理解，儘管在如所繪示的實例實施例中示出一個層的RDL 112，但更多層的RDL可形成於RDL 112之上且電連接至RDL 112。後續形成製程與用於接合裝置晶粒MD1(圖7)及裝置晶粒BD(圖1A)的接合方案相關，且與將裝置晶粒面朝下抑或面朝上置放以及使用焊料接合、直接金屬-金屬接合抑或混合接合相關。因此，儘管將一個形成製程論述為實例，但其他形成製程及結構在本揭露的範疇內。
根據一些實施例，多個導電凸塊114可使用第二電鍍罩幕來電鍍，且可使用與用於電鍍RDL 112的相同的金屬晶種層來電鍍。導電凸塊114可包括銅、鎳、金或類似者。在電鍍導電凸塊114之後，移除第二電鍍罩幕，隨後執行蝕刻製程以移除金屬晶種層的先前由第二電鍍罩幕及第一電鍍罩幕覆蓋的暴露部分。將金屬晶種層的剩餘部分視為多條RDL 112的部分。因此形成重佈線結構50。
接著，如圖5中所繪示，形成介電層116。各別製程示出為如圖28中所繪示的製程流程200中的製程210。可執行平坦化製程以使多個導電凸塊114及介電層116的頂部表面齊平。當要執行混合接合時，介電層116可包括含矽介電材料，諸如氧化矽。根據替代實施例，多個導電凸塊114可在形成介電層116之後形成，且形成製程可包含在介電層116中形成多個開口以顯露下伏的多條RDL 112，且接著形成多個導電凸塊114。對應的介電層116 可包括諸如PBO、聚醯亞胺、BCB或類似者的有機材料，或諸如氧化矽、氮化矽、氮氧化矽或類似者的無機介電材料。形成製程亦包含形成金屬晶種層、形成電鍍罩幕、電鍍金屬材料、移除電鍍罩幕以及接著蝕刻金屬晶種層的非所要部分。
接著，如圖6中所繪示，形成多個金屬支柱120。各別製程示出為如圖28中所繪示的製程流程200中的製程212。形成製程可包含形成金屬晶種層、在金屬晶種層之上形成電鍍罩幕(未繪示，可為光阻)、圖案化電鍍罩幕以顯露下伏的金屬晶種層，以及接著在電鍍罩幕中的多個開口中電鍍金屬材料。金屬支柱120替代地稱為穿孔或模塑穿孔，此是因為其將穿透隨後形成的密封材料(其可為模塑化合物)。經電鍍的金屬材料可為銅或銅合金。金屬支柱120可具有實質上豎直且筆直的邊緣。根據替代實施例，多個導電凸塊114A未在前述製程中形成。實情為，其在用於形成多個金屬支柱120的相同製程中形成。
圖7示出包含多個記憶體晶粒MD1及多個橋接晶粒BD(亦參考圖1A)的層級1的多個晶粒的置放/貼合。各別製程示出為如圖28中所繪示的製程流程200中的製程214。橋接晶粒BD在未示出的橫截面中，且因此未在圖7中繪示。根據一些實施例，層級11的多個晶粒MD1及BD面朝下，且層級1的多個晶粒MD1及BD中的多個電連接件122接合至多個導電凸塊114。根據替代實施例，例如如圖16A、圖16B以及圖16C中所繪示，多個晶粒MD1及BD可面朝上，且多個裝置晶粒MD1及BD的背側上的多個電連接件接合至多個導電凸塊114。
記憶體晶粒MD1及橋接晶粒BD可具有預先形成為各別 裝置晶粒的部分的多個電連接件124A(諸如金屬接墊、金屬凸塊或類似者)。多個電連接件124A位於各別晶粒的背側上。介電層126A亦可形成於記憶體晶粒MD1及橋接晶粒BD的背表面上。根據替代實施例，多個電連接件124A未預先形成於多個記憶體晶粒MD1及多個橋接晶粒BD中。實情為，多個基底穿孔26A延伸至半導體基底20的頂部表面與背表面之間的中間階層，且多個電連接件在密封多個記憶體晶粒MD1及多個橋接晶粒BD之後形成且在圖8中所繪示的製程與圖9中所繪示的製程之間形成。
接著，將層級1的多個晶粒MD1及BD以及多個金屬支柱120密封於密封體130中，如圖8中所繪示。各別製程示出為如圖28中所繪示的製程流程200中的製程216。密封體130填充相鄰的穿孔120與層級1的多個晶粒MD1及BD之間的間隙。密封體130可包含模塑化合物、模塑底膠、環氧樹脂及/或樹脂。當由模塑化合物形成時，密封體130可包含可為聚合物、樹脂、環氧樹脂或類似者的基礎材料以及基礎材料中的多個填充劑顆粒。填充劑顆粒可為SiO2、Al2O3、二氧化矽或類似者的介電顆粒，且可具有球形形狀。此外，球形填充劑顆粒可具有多個不同直徑。
接著執行諸如化學機械研磨(Chemical Mechanical Polish；CMP)步驟或機械研磨步驟的平坦化製程以薄化密封體130，直至暴露多個穿孔120以及層級1的多個晶粒MD1及BD為止。歸因於平坦化製程，穿孔120的頂端與電連接件124A(若預先形成)的頂部表面實質上齊平(共面)，且與密封體130的頂部表面實質上共面。貫穿描述，層級1的多個晶粒及密封體130統稱為重建構晶圓131。
參考圖9，層級2的多個晶粒LD接合至層級1的多個晶粒MD1及BD以及多個穿孔120(及接合至重建構晶圓131)。各別製程示出為如圖28中所繪示的製程流程200中的製程218。在所示出的實例實施例中，層級2的多個晶粒LD直接接合至層級1的多個晶粒MD1及BD以及多個穿孔120，其間無RDL。根據替代實施例，包含多個介電層及多條RDL的額外扇出型重佈線結構(未繪示)可形成於層級1的多個晶粒MD1及BD以及多個穿孔120上且連接至層級1的多個晶粒MD1及BD以及多個穿孔120，且層級2的多個晶粒LD接合至額外扇出型重佈線結構。與層級1的多個晶粒類似，多個電連接件124B及多個介電層126B可預先形成於層級2的多個晶粒LD中，或可形成於層級2的多個晶粒LD之上的另一額外扇出型重佈線結構中。
圖10示出將層級2的多個晶粒LD密封於可與密封體130類似或相同的密封體132中。接著執行平坦化製程以使層級2的多個晶粒LD及密封體132的頂部表面齊平。各別製程示出為如圖28中所繪示的製程流程200中的製程220。貫穿描述，層級2的多個晶粒LD及密封體132統稱為重建構晶圓133。
在如圖9及圖10中所繪示的實例實施例中，首先置放且密封層級1的多個晶粒以形成重建構晶圓131，且經由晶粒-晶圓接合將離散的層級2的多個晶粒置放於重建構晶圓131上。圖23中繪示晶粒-晶圓接合製程的透視圖，其中重建構晶圓131包含層級1的多個晶粒MD1及BD以及密封體130。層級2的多個晶粒LD置放至重建構晶圓131上。圖24示出替代實施例，其中預先形成重建構晶圓131及重建構晶圓133兩者，且經由晶圓-晶圓接 合將重建構晶圓133接合至重建構晶圓131。與圖23及圖24中所繪示的類似，層級3的多個晶粒MD3亦可經由晶粒-晶圓接合或晶圓-晶圓接合而接合至層級2的多個晶粒。
參考圖11，層級3的多個晶粒MD3接合至層級2的多個晶粒LD(且接合至重建構晶圓133)。各別製程示出為如圖28中所繪示的製程流程200中的製程222。在所示出的實例實施例中，層級3的多個晶粒MD3直接接合至層級2的多個晶粒LD，其間無RDL。根據替代實施例，包含多個介電層及多條RDL的額外扇出型重佈線結構(未繪示)可形成於層級2的多個晶粒LD上且連接至層級2的多個晶粒LD，且層級3的多個晶粒MD3接合至額外扇出型重佈線結構。
圖12示出將層級3的多個晶粒MD3密封於可與密封體130及/或密封體132類似或相同的密封體134中。各別製程示出為如圖28中所繪示的製程流程200中的製程224。接著執行平坦化製程以使層級3的多個晶粒MD3及密封體134的頂部表面齊平。層級3的多個晶粒MD3及密封體134統稱為重建構晶圓135。貫穿描述，包含介電層54及上覆結構的結構稱為重建構晶圓100(其亦稱為計算系統封裝100)。接著，重建構晶圓100自載體102(圖11)剝離，例如藉由將雷射光束投影於釋放膜104上，使得釋放膜104被分解。各別製程示出為如圖28中所繪示的製程流程200中的製程226。
圖13示出多個電連接件142的形成，所述電連接件142可包含焊料區、金屬接墊、金屬柱或其組合。各別製程示出為如圖28中所繪示的製程流程200中的製程228。形成製程可包含在介 電層54中形成多個開口，以及形成延伸至多個開口中以接觸多條RDL 106的多個電連接件142。
圖14示出將重建構晶圓100接合至封裝組件144，所述封裝組件144可為或可包含印刷電路板、封裝基底、矽中介層(interposer)、有機中介層、電源模組、插座或類似者。各別製程示出為如圖28中所繪示的製程流程200中的製程230。將底膠146分配至重建構晶圓100與封裝組件144之間的間隙中。因此形成封裝148。根據一些實施例，可為轉接器、插座(包含用以插入接腳的銷孔)或類似者的連接件152可形成於封裝148中，例如，貼合至封裝組件144，使得封裝148中的電路可電連接至外部組件。
根據一些實施例，未經鋸割的整個重建構晶圓100接合至封裝組件144且包含於所得封裝148中。因此，封裝148中的重建構晶圓100可具有與圖23及圖24中所繪示類似的圓形俯視圖。根據替代實施例，修整重建構晶圓100以移除不具有裝置晶粒及導線的部分，但不修整包含裝置及導線的部分。根據又替代實施例，沿著多條切割道141(圖13)將重建構晶圓100鋸割成多個相同封裝，所述多個相同封裝各自包含如圖13中所繪示的所有所示出的多個裝置晶粒，且相同封裝中的一者用於形成如圖14中的封裝。
圖27示出圖14中的區150的放大視圖。如圖27中所繪示，密封體130包含基礎材料130A及基礎材料130A中的多個填充劑顆粒(亦稱為球形顆粒)130B。密封體132包含基礎材料132A及基礎材料130A中的多個填充劑顆粒(亦稱為球形顆粒)132B。 密封體134包含基礎材料134A及基礎材料134A中的多個填充劑顆粒(亦稱為球形顆粒)134B。由於未對密封體130的底部表面執行平坦化，因此與重佈線結構50接觸的球形顆粒130B是圓形的，其中圓形表面與重佈線結構50接觸。密封體130的與密封體132(或額外重佈線結構(若存在)接觸的部分已在圖8中所繪示的步驟中平坦化。因此，密封體130的頂部表面處的球形顆粒130B在平坦化期間部分地經研磨，且因此將具有實質上共面的頂部表面。類似的，在密封體132及密封體134中的每一者中，底部表面處的球形顆粒132B/球形顆粒134B未經研磨且為球形的，而頂部表面處的球形顆粒132B/球形顆粒134B經研磨，且為具有圓形底部表面及平坦頂部表面的部分球形顆粒。
圖15A、圖15B、圖15C、圖16A、圖16B、圖16C、圖17A、圖17B、圖17C、圖19A、圖19B、圖20A、圖20B、圖21A、圖21B、圖22A及圖22B示出根據替代實施例的計算系統封裝100的橫截面圖。這些實施例與圖1A、圖1B、圖1C、圖1D、圖1E、圖1F以及圖1G(及圖2至圖13)中所繪示的實施例類似，其中修改了一些部分。因此，在適用時，亦可將前述實施例中所提供的論述應用於這些實施例。
圖15A、圖15B、圖15C、圖16A、圖16B、圖16C、圖17A、圖17B以及圖17C中所繪示的實施例亦可自圖1B及圖1C中的參考橫截面1A-1A、參考橫截面1F-1F以及參考橫截面1G-1G獲得。
圖15A、圖15B以及圖15C示出根據一些實施例的計算系統封裝100。這些實施例與圖1A、圖1B、圖1C、圖1D、圖1E、 圖1F以及圖1G中的實施例(其亦為圖13中的結構)類似，不同之處在於在圖13中，多個記憶體晶粒MD1及多個記憶體晶粒MD3中的每一者為單個記憶體晶粒，而在圖15A、圖15B以及圖15C中的實施例中，可使用分別包含多個堆疊的記憶體晶粒MD1及MD3的多個記憶體堆疊(亦稱為記憶體晶粒堆疊)MD1'及多個記憶體堆疊(亦稱為晶粒堆疊、記憶體晶粒堆疊)MD3'。多個記憶體晶粒MD1可經由形成於其中的基底穿孔內連。根據這些實施例，層級1的多個晶粒、層級2的多個晶粒以及層級3的多個晶粒面朝下。層級3的多個晶粒MD3亦可為多個晶粒堆疊MD3'的部分。
圖16A、圖16B以及圖16C示出根據一些實施例的計算系統封裝100。這些實施例與圖1A、圖1B、圖1C、圖1D、圖1E、圖1F以及圖1G中的實施例(其亦為圖13中的結構)類似，不同之處在於在圖13中，層級1的多個晶粒MD1及BD面朝下，而在圖16A、圖16B以及圖16C中的實施例中，層級1的多個晶粒MD1及BD面朝上。層級2的多個晶粒LD及層級3的多個晶粒MD3仍面朝下。
圖17A、圖17B以及圖17C示出根據一些實施例的計算系統封裝100。這些實施例與圖15A、圖15B以及圖15C中的實施例類似，不同之處在於在圖15A、圖15B以及圖15C中，多個記憶體晶粒MD1及多個橋接晶粒BD面朝下，而在圖17A、圖17B以及圖17C中的實施例中，多個記憶體晶粒MD1及多個橋接晶粒BD面朝上。層級2的多個晶粒LD及層級3的多個晶粒MD3仍面朝下。
圖18A及圖18B分別示出根據一些實施例的計算系統封裝100俯視圖及仰視圖，這些實施例與圖1B及圖1C中所繪示的實施例類似，不同之處在於除了使四個邏輯晶粒內連的多個橋接晶粒BD(亦標記為BD1)之外，亦可添加多個橋接晶粒BD(亦標記為BD2)以使兩個相鄰的邏輯晶粒LD內連。根據替代實施例，不形成橋接晶粒BD1，而是形成橋接晶粒BD2。在後續圖19A、圖19B、圖20A、圖20B、圖21A、圖21B、圖22A以及圖22B中，自圖18A及圖18B中的參考橫截面A-A獲得圖號包含字母「A」的圖式，且自圖18A及圖18B中的參考橫截面B-B獲得圖號包含字母「B」的圖式。
圖19A及圖19B示出根據一些實施例的計算系統封裝100。這些實施例與圖1A、圖1B、圖1C、圖1D、圖1E、圖1F以及圖1G中的實施例(其亦為圖13中的結構)類似，不同之處在於添加了多個橋接晶粒BD2，且所示出的多個橋接晶粒BD2中的每一者使兩個層級2的多個晶粒LD內連，而非如橋接晶粒BD1一樣使四個層級2的多個晶粒LD內連。層級1及層級3中的多個記憶體晶粒分別為單個記憶體晶粒。
圖20A及圖20B示出根據一些實施例的計算系統封裝100。這些實施例與圖19A及圖19B中的實施例類似，不同之處在於在圖20A及圖20B中，使用多個記憶體晶粒堆疊MD1'及多個記憶體晶粒堆疊MD3'。
圖21A及圖21B示出根據一些實施例的計算系統封裝100。這些實施例與圖19A及圖19B中的實施例類似，不同之處在於在圖19A及圖19B中，層級1的多個晶粒MD1及BD1面朝下， 而在圖21A及圖21B中，層級1的多個晶粒MD1及BD1面朝上。
圖22A及圖22B示出根據一些實施例的計算系統封裝100。這些實施例與圖20A及圖20B中的實施例類似，不同之處在於在圖20A及圖20B中，多個橋接晶粒BD及多個記憶體晶粒堆疊MD1'中的層級1的多個晶粒MD1面朝下，而在圖22A及圖22B中，多個橋接晶粒BD及多個記憶體晶粒堆疊MD1'中的層級1的多個晶粒MD1面朝上。
本揭露的實施例具有一些有利特徵。藉由形成包含三個層級的計算系統封裝，其中中間層級具有邏輯晶粒，且記憶體晶粒位於上部層級及下部層級中，邏輯晶粒具有至記憶體晶粒的最短路徑。形成橋接晶粒以使相鄰邏輯晶粒內連。歸因於採用邏輯晶粒、記憶體晶粒以及橋接晶粒的陣列，系統的可縮放性得以改善。可改善計算效率，可增加系統的頻寬，且可減小延遲。
根據本揭露的一些實施例，方法包括形成重建構晶圓，形成重建構晶圓包括：在載體之上形成重佈線結構；在重佈線結構之上接合第一多個記憶體晶粒；在重佈線結構之上接合多個橋接晶粒；在第一多個記憶體晶粒及多個橋接晶粒之上接合多個邏輯晶粒，其中多個橋接晶粒中的每一者使多個邏輯晶粒中的四者內連且與所述四者的拐角區交疊；以及在多個邏輯晶粒之上接合第二多個記憶體晶粒，其中多個邏輯晶粒形成第一陣列，且第二多個記憶體晶粒形成第二陣列。根據一實施例，所述方法更包括將封裝組件接合至重建構晶圓以形成額外封裝。根據一實施例，每當封裝組件接合至重建構晶圓時，重建構晶圓包括第一陣列及第二陣列。根據一實施例，所述方法更包括將插座貼合至額外封裝，其中每當貼 合插座之後，重建構晶圓包括第一陣列及第二陣列兩者。根據一實施例，所述方法更包括：將第一多個記憶體晶粒及多個橋接晶粒密封於第一密封體中；將多個邏輯晶粒密封於第二密封體中；以及將第二多個記憶體晶粒密封於第三密封體中。根據一實施例，重建構晶圓在第一密封體及第三密封體中不含邏輯晶粒，且在第二密封體中不含記憶體晶粒。根據一實施例，多個邏輯晶粒具有與第一密封體的頂部表面實體接觸的底部表面。根據一實施例，第二密封體密封於第一密封體之上且與第一密封體實體接觸。根據一實施例，第一多個記憶體晶粒彼此相同，多個邏輯晶粒彼此相同，且第二多個記憶體晶粒彼此相同。根據一實施例，多個邏輯晶粒經由混合接合而接合至第一多個記憶體晶粒。根據一實施例，經由晶粒-晶圓接合來執行在第一多個記憶體晶粒及多個橋接晶粒之上接合多個邏輯晶粒。根據一實施例，經由晶圓-晶圓接合製程來執行在第一多個記憶體晶粒及多個橋接晶粒之上接合多個邏輯晶粒包括：密封第一多個記憶體晶粒及多個橋接晶粒以形成第一重建構晶圓；密封多個邏輯晶粒以形成第二重建構晶圓；以及經由晶圓-晶圓接合而將第二重建構晶圓接合至第一重建構晶圓。
根據本揭露的一些實施例，封裝包括：重佈線結構；第一多個記憶體晶粒，位於重佈線結構之上；多個橋接晶粒，位於重佈線結構之上；多個邏輯晶粒，位於第一多個記憶體晶粒及多個橋接晶粒之上，其中多個橋接晶粒中的每一者使多個邏輯晶粒中的至少兩者內連且與所述至少兩者的拐角區交疊；以及第二多個記憶體晶粒，位於多個邏輯晶粒之上且接合至所述多個邏輯晶粒，其中多個邏輯晶粒形成第一陣列，且第二多個記憶體晶粒形成第二陣 列。根據一實施例，第一多個記憶體晶粒彼此相同，第二多個記憶體晶粒彼此相同，多個邏輯晶粒彼此相同，且多個橋接晶粒彼此相同。根據一實施例，多個橋接晶粒中更包括電容器。根據一實施例，封裝更包括：第一密封體，將第一多個記憶體晶粒密封於其中；第二密封體，將多個邏輯晶粒密封於其中，其中多個邏輯晶粒具有與第一密封體的頂部表面接觸的底部表面；以及第三密封體，將第二多個記憶體晶粒密封於其中。根據一實施例，第三密封體與第二密封體實體接觸。
根據本揭露的一些實施例，封裝包括重建構晶圓，所述重建構晶圓包括：重佈線結構，包括多條重佈線；多個橋接晶粒，位於重佈線結構之上且接合至所述重佈線結構；多個邏輯晶粒，位於多個橋接晶粒之上且接合至所述多個橋接晶粒，其中多個橋接晶粒中的至少一者接合至多個邏輯晶粒中的四者的拐角區；以及多個記憶體晶粒，位於多個邏輯晶粒之上且接合至所述多個邏輯晶粒，其中多個記憶體晶粒接合至多個邏輯晶粒。根據一實施例，封裝更包括接合至重建構晶圓的封裝組件。根據一實施例，封裝更包括接合至封裝組件的插座。
前文概述若干實施例的特徵，使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解，其可易於使用本揭露作為設計或修改用於進行本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更 改。
20A、20B、20C:半導體基底
22:內連線結構
26A、26B:基底穿孔
28、124A、124B、142:電連接件
30:表面介電層
50:內連線結構/重佈線結構
54、108、116、126A、126B:介電層
100:計算系統封裝/重建構晶圓
106、112:重佈線
114:導電凸塊/凸塊下金屬
130、132、134:密封體
BD:橋接晶粒/裝置晶粒/晶粒
LD:邏輯晶粒/晶粒
MD1:記憶體晶粒/裝置晶粒/晶粒
MD3:記憶體晶粒/晶粒

Claims (10)

  1. 一種計算系統封裝的形成方法，包括：形成重建構晶圓，包括：在載體之上形成重佈線結構；在所述重佈線結構之上接合第一多個記憶體晶粒；在所述重佈線結構之上接合多個橋接晶粒；在所述第一多個記憶體晶粒及所述多個橋接晶粒之上接合多個邏輯晶粒，其中所述多個橋接晶粒中的每一者使所述多個邏輯晶粒中的四者內連且與所述四者的拐角區交疊；以及在所述多個邏輯晶粒之上接合第二多個記憶體晶粒，其中所述多個邏輯晶粒形成第一陣列，且所述第二多個記憶體晶粒形成第二陣列。
  2. 如請求項1所述的計算系統封裝的形成方法，更包括：將封裝組件接合至所述重建構晶圓以形成額外封裝。
  3. 如請求項1所述的計算系統封裝的形成方法，更包括：將所述第一多個記憶體晶粒及所述多個橋接晶粒密封於第一密封體中；將所述多個邏輯晶粒密封於第二密封體中；以及將所述第二多個記憶體晶粒密封於第三密封體中。
  4. 如請求項1所述的計算系統封裝的形成方法，其中所述多個邏輯晶粒經由混合接合而接合至所述第一多個記憶體晶粒。
  5. 如請求項1所述的封裝的形成方法，其中經由晶粒-晶圓接合來執行在所述第一多個記憶體晶粒及所述多個橋接晶粒之上接合所述多個邏輯晶粒。
  6. 如請求項1所述的計算系統封裝的形成方法，其中經由晶圓-晶圓接合製程來執行在所述第一多個記憶體晶粒及所述多個橋接晶粒之上接合所述多個邏輯晶粒包括：密封所述第一多個記憶體晶粒及所述多個橋接晶粒以形成第一重建構晶圓；密封所述多個邏輯晶粒以形成第二重建構晶圓；以及經由晶圓-晶圓接合而將所述第二重建構晶圓接合至所述第一重建構晶圓。
  7. 一種計算系統封裝，包括：重佈線結構；第一多個記憶體晶粒，位於所述重佈線結構之上；多個橋接晶粒，位於所述重佈線結構之上；多個邏輯晶粒，位於所述第一多個記憶體晶粒及所述多個橋接晶粒之上，其中所述多個橋接晶粒中的每一者使所述多個邏輯晶粒中的至少兩者內連且與所述至少兩者的拐角區交疊；以及第二多個記憶體晶粒，位於所述多個邏輯晶粒之上且接合至所述多個邏輯晶粒，其中所述多個邏輯晶粒形成第一陣列，且所述第二多個記憶體晶粒形成第二陣列。
  8. 如請求項7所述的計算系統封裝，其中所述第一多個記憶體晶粒彼此相同，所述第二多個記憶體晶粒彼此相同，所述多個邏輯晶粒彼此相同，且所述多個橋接晶粒彼此相同。
  9. 一種計算系統封裝，包括：重建構晶圓，包括：重佈線結構，包括多條重佈線；多個橋接晶粒，位於所述重佈線結構之上且接合至所述重佈線結構；多個邏輯晶粒，位於所述多個橋接晶粒之上且接合至所述多個橋接晶粒，其中所述多個橋接晶粒中的至少一者接合至所述多個邏輯晶粒中的四者的拐角區；以及多個記憶體晶粒，位於所述多個邏輯晶粒之上且接合至所述多個邏輯晶粒，其中所述多個記憶體晶粒接合至所述多個邏輯晶粒。
  10. 如請求項9所述的計算系統封裝，更包括接合至所述重建構晶圓的封裝組件。
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