CN114765165A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN114765165A
CN114765165A CN202210038417.1A CN202210038417A CN114765165A CN 114765165 A CN114765165 A CN 114765165A CN 202210038417 A CN202210038417 A CN 202210038417A CN 114765165 A CN114765165 A CN 114765165A
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China
Prior art keywords
dies
die
logic
memory
bridge
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CN202210038417.1A
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Inventor
余振华
陈颉彦
王垂堂
蔡仲豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN114765165A publication Critical patent/CN114765165A/zh
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Abstract

方法包括形成重构晶圆，包括：在载体上方形成再分布结构，在再分布结构上方接合第一多个存储器管芯，在再分布结构上方接合多个桥接管芯，以及在第一多个存储器管芯和多个桥接管芯上方接合多个逻辑管芯。多个桥接管芯中的每个互连多个逻辑管芯中的四个并且与多个逻辑管芯中的四个的角部区域重叠。第二多个存储器管芯接合在多个逻辑管芯上方。多个逻辑管芯形成第一阵列，并且第二多个存储器管芯形成第二阵列。本申请的实施例涉及封装件及其形成方法。

Description

封装件及其形成方法
技术领域
本申请的实施例涉及封装件及其形成方法。
背景技术
集成电路的封装变得越来越复杂，在同一封装件中集成更多的器件管芯以实现更多的功能。例如，已经开发出系统封装件，以在同一封装件中包括多个器件管芯，例如处理器和存储器块。在系统封装件中，可以采用2D并排和3D堆叠两种方式接合使用不同技术形成的具有不同功能的器件管芯，从而形成系统，其具有很高的计算效率、高带宽、高功能性封装密度、低通讯延迟和每位数据的低能耗。
发明内容
本申请的一些实施例提供了一种形成封装件的方法，包括：形成重构晶圆，包括：在载体上方形成再分布结构；在所述再分布结构上方接合第一多个存储器管芯；在所述再分布结构上方接合多个桥接管芯；在所述第一多个存储器管芯和所述多个桥接管芯上方接合多个逻辑管芯，其中，所述多个桥接管芯中的每个互连所述多个逻辑管芯中的四个并且与所述多个逻辑管芯中的四个的角部区域重叠；以及在所述多个逻辑管芯上方接合第二多个存储器管芯，其中，所述多个逻辑管芯形成第一阵列，并且所述第二多个存储器管芯形成第二阵列。
本申请的另一些实施例提供了一种封装件，包括：再分布结构；第一多个存储器管芯，位于所述再分布结构上方；多个桥接管芯，位于所述再分布结构上方；多个逻辑管芯，位于所述第一多个存储器管芯和所述多个桥接管芯上方，其中，所述多个桥接管芯中的每个互连所述多个逻辑管芯中的至少两个并且与所述多个逻辑管芯中的至少两个的角部区域重叠；以及第二多个存储器管芯，位于所述多个逻辑管芯上方并与所述多个逻辑管芯接合，其中，所述多个逻辑管芯形成第一阵列，并且所述第二多个存储器管芯形成第二阵列。
本申请的又一些实施例提供了一种封装件，包括：重构晶圆，包括：再分布结构，包括多条再分布线；多个桥接管芯，位于所述再分布结构上方并接合至所述再分布结构；多个逻辑管芯，位于所述多个桥接管芯上方并接合至所述多个桥接管芯，其中，所述多个桥接管芯中的至少一个接合至所述多个逻辑管芯中的四个的角部区域；以及第二多个存储器管芯，位于所述多个逻辑管芯上方并接合至所述多个逻辑管芯，其中，所述第二多个存储器管芯接合至所述多个逻辑管芯。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1A、图1B、图1C、图1D、图1E、图1F和图1G示出根据一些实施例的计算系统封装件的截面图、立体图以及俯视图和仰视图。
图2至图14示出根据一些实施例的计算系统封装件的形成中的中间阶段的截面图。
图15A、图15B、图15C、图16A、图16B、图16C、图17A、图17B和图17C示出根据一些实施例的计算系统封装件的截面图。
图18A和图18B示出根据一些实施例的计算系统封装件的俯视图和仰视图。
图19A、图19B、图20A、图20B、图21A、图21B、图22A和图22B示出根据一些实施例的计算系统封装件的截面图。
图23示出根据一些实施例的管芯-晶圆接合工艺的立体图。
图24示出根据一些实施例的晶圆-晶圆接合工艺的立体图。
图25示出根据一些实施例的桥接管芯中的互连结构的一部分。
图26示出根据一些实施例的桥接管芯中的电容器。
图27示出根据一些实施例的计算系统封装件中的密封剂的放大视图。
图28示出根据一些实施例的用于形成计算系统封装件的工艺流程图。
具体实施方式
以下公开内容提供了多种不同实施例或实例，以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在...下面”、“在...下方”、“下部”、“在...上面”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各个实施例，提供了一种计算系统封装件及其形成方法。计算系统封装件可以包括三个层级，其中中间层级包括逻辑管芯，而底部层级和顶部层级包括存储器管芯。因此，逻辑管芯具有到它们访问的存储器管芯的最短路径。桥接管芯位于底部层级，用于互连逻辑管芯。因此，每个逻辑管芯具有对其他逻辑管芯和存储器管芯的最大访问，而不会增加系统的复杂性。同样，由于采用了逻辑管芯、存储器管芯和桥接管芯的阵列，所以系统的可扩展性得到改进。通过该设置，由于存储器管芯和逻辑管芯的紧密接近以及有效的布局，可以提高计算效率，可以增加系统的带宽，并且可以减少延迟。根据一些实施例示出了封装件的形成中的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1A、图1B、图1C、图1D、图1E、图1F和图1G示出根据一些实施例的计算系统封装件100的截面图、立体图以及俯视图和仰视图。计算系统封装件100包括分布在包括层级1、层级2和层级3的多个层级中的逻辑管芯、存储器管芯和桥接管芯，其分别密封在密封剂130、132和134中。层级1可以包括存储器管芯MD1和桥接管芯BD。层级2可以包括逻辑管芯LD。层级3可以包括存储器管芯MD3。逻辑管芯LD执行计算功能，并且逻辑管芯LD访问存储器管芯MD1和MD3。在本公开的附图中，器件管芯的附图标记可以以符号“LD”、符号“MD”或符号“BD”开头。符号“LD”用于表示对应的管芯是逻辑管芯。符号“MD1”用于表示对应的管芯是在层级1中的存储器管芯，符号“MD3”用于表示对应的管芯是在层级3中的存储器管芯。存储器管芯MD1和MD3统称为存储器管芯MD。字母“BD”用于表示对应的管芯是桥接管芯。在层级1、层级2和层级3的每一个中，逻辑管芯的数量和存储器管芯的数量可以比图示的更多。应当理解，尽管示出了三层级封装件作为示例，但是计算系统封装件可以包括多于三个层级，诸如四个层级、五个层级或更多，并且附加层级可以在所示的层级1之下，和/或在所示的层级3之上。
根据本公开的一些实施例，逻辑管芯LD可以是应用处理器(AP)管芯、图形处理单元(GPU)管芯、现场可编程门阵列(FPGA)管芯、专用集成电路(ASIC)管芯、输入输出(IO)管芯、网络处理单元(NPU)管芯、张量处理单元(TPU)管芯、人工智能(AI)引擎管芯等。
根据本公开的一些实施例，存储器管芯MD1和MD3可以包括静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯、宽I/O存储器管芯、NAND存储器管芯、电阻式随机存取存储器(RRAM)管芯、磁阻式随机存取存储器(MRAM)管芯、相变随机存取存储器(PCRAM)管芯等或其他类型的易失性或非易失性存储器管芯。存储器管芯可以在其中包括控制器，或者可以没有控制器。在存储器管芯不包括控制器的实施例中，控制器可以内置在逻辑管芯中。存储器管芯也可以是单个存储器管芯或预堆叠的存储器块的形式。
在计算系统封装件100中，并且可能在每个层级中，可以混合不同类型的存储器管芯。例如，层级1可以采用如上所述的一种类型的存储器管芯，而层级3可以采用另一种类型的存储器管芯。但是，层级1中的所有存储器管芯可以是同一类型，并且彼此相同，而层级3中的所有存储器管芯可以是同一类型，并且彼此相同，以提高系统的可扩展性，并减小封装件的厚度(由于混合了不同类型，所以对应层级的厚度由最厚的类型决定)。层级2中的逻辑管芯LD可以包括不同类型的逻辑管芯，其可以包括上述逻辑管芯。替代地，层级2中的所有逻辑管芯可以是同一类型并且彼此相同。
层级1可以包括多个存储器管芯MD1和多个桥接管芯BD，并且可以不是或没有其他类型的管芯，诸如逻辑管芯、独立的无源器件管芯等。层级2可以包括多个逻辑管芯LD，并且可以是或可以不是、没有其他类型的管芯，诸如存储器管芯、桥接管芯、无源器件管芯等。层级3可以包括多个存储器管芯MD3，并且可以是或可以不是、没有其他类型的管芯，诸如逻辑管芯、桥接管芯、无源器件管芯等。
逻辑管芯LD、存储器管芯MD1/MD3和桥接管芯BD中的每一个可以包括半导体衬底20A、20B或20C，其可以是硅衬底。互连结构22形成在对应的半导体衬底20A/20B/20C上，并用于互连对应管芯中的器件。衬底贯通孔26A和26B可以形成为穿透层级1管芯和层级2管芯的对应半导体衬底20，并且用于将上面的组件互连到下面的组件。此外，可以形成电连接件28以接合至其他器件管芯。电连接件28用于在不同层级中的管芯之间的接合，并且可以是金属焊盘、金属柱、焊料区域等。根据一些实施例，电连接件28是金属柱(诸如铜柱)，并且在对应的表面介电层30中。根据一些实施例，表面介电层30由氧化硅形成或包括氧化硅。根据其他实施例，表面介电层30包括诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物。在整个说明书中，将半导体衬底20的具有互连结构22(以及有源器件，诸如晶体管，未示出)的一侧称为前侧(或“面”)，而将其相反侧称为后侧(或“背”)。因此，取决于管芯的哪一侧彼此接合，接合可以是面-背接合、面-面接合、背-背接合。例如，在图1A中，采用面-背接合。
再次参考图1A、图1F或图1G，相邻层级通过直接金属-金属接合、焊料接合或混合接合彼此接合。混合接合包括电介质-电介质接合(也称为熔融接合，其中可以在两个接合的介电层之间形成Si-O-Si键)。
下面的层级1管芯可以具有互连结构(再分布结构)50。再分布结构50可以包括介电层54、108和116、RDL 106和112以及凸块下金属(UBM)114。可以包括焊料区域、金属柱、微凸块等的电连接件142形成在再分布结构50的底面处。
图1B和图1C分别示出如图1A所示的计算系统封装件100的俯视图和仰视图。可以参考图1A、图1F和图1G找到计算系统封装件100的截面，其中图1A示出图1B和图1C中的参考截面1A-1A，图1F示出图1B和图1C中的参考截面1F-1F，图1G示出图1B和图1C中的参考截面1G-1G。如图1B中所示，存储器管芯MD1和桥接管芯BD以虚线示出，因为它们在逻辑管芯DL之下。根据一些实施例，存储器管芯MD3可以布置为阵列。逻辑管芯LD可以布置为阵列。桥接管芯BD可以布置为阵列，并且存储器管芯MD1也可以布置为阵列。尽管示出3×3阵列作为示例，但是可以形成更大的阵列。以阵列形式形成器件管芯具有高可扩展性的有利特征。这对于通过添加更多逻辑管芯、存储器管芯和桥接管芯来提高计算能力特别有用。如将在随后的段落中讨论的，逻辑管芯的合作可以通过共享存储器管芯以及通过桥接管芯进行交互来实现，从而可以通过扩大器件阵列来轻松地实现系统的规模扩大和计算能力的提高。
根据一些实施例，所有逻辑管芯LD彼此相同。根据替代实施例，一些逻辑管芯LD彼此相同，并且与也彼此相同的其他逻辑管芯LD不同。例如，第一多个逻辑管芯LD可以彼此相同，并且第二多个逻辑管芯LD可以彼此相同，并且不同于第一多个逻辑管芯LD。第一和第二多个逻辑管芯LD可以以交替的布局布置，例如，在阵列的行和列的每一个中交替布置。
根据一些实施例，每个存储器管芯MD3接合至逻辑管芯LD之一，并由其进行信号访问。每个存储器管芯MD1接合至两个相邻的逻辑管芯LD，并由其进行信号访问，这也在图1G中示出。利用这种布局，每个逻辑管芯可以直接访问三个存储器管芯，而无需它们之间的布线。这显著增加了逻辑管芯访问的存储器的量，而没有增加功耗和延迟。
还参考图1B和图1C，每个桥接管芯BD接合至并且互连四个逻辑管芯LD。桥接管芯BD用于四个连接逻辑管芯彼此的相互通信。例如，桥接管芯BD可以在其中包括导线，其直接互连四个逻辑管芯LD中的每对。桥接管芯BD也可以包括联网电路(因此可以是芯片上联网管芯)，其包括用于在四个逻辑管芯的每对之间切换信号的开关、路由器电路等。因此，通过桥接管芯BD，所有四个逻辑管芯LD可以用作集成系统。此外，每个逻辑管芯LD连接至四个桥接管芯，因此可以将信号从四个桥接管芯中的任何一个路由到另一个。因此，所有逻辑管芯LD可以彼此一起工作(通过桥接管芯BD)以形成集成计算系统，并实现并行计算。如从图1B和图1C可以想到的，可以通过复制和扩大逻辑管芯LD、存储器管芯MD1和MD3以及桥接管芯BD的阵列来放大计算系统封装件100以增加计算能力。
图1D和图1E示出根据一些实施例的计算系统封装件100的立体图，图1D示出从顶侧观察的立体图，图1E示出从底侧观察的立体图。
图1F示出如图1B和图1C所示的参考截面1F-1F。由于在示出的截面图中没有存储器管芯MD1，所以在图1F中未示出存储器管芯MD1。示出连接至同一桥接管芯的两个逻辑管芯LD，而未示出连接至同一桥接管芯BD的另外两个逻辑管芯，因为它们不在示出的截面图中。
图25示意性地示出桥接管芯BD，其包括用于互连逻辑管芯LD的桥接结构34。根据一些实施例，桥接结构34形成在桥接管芯BD的互连结构22中。例如，互连结构22可以包括介电层(有时称为金属间电介质(IMD))，其可以包括低k介电材料。桥接结构34可以包括金属线和通孔，其可以延伸到互连结构22中的多个金属化层中。金属线和通孔互连以形成多个电气路径36，每个电气路径36的相反端连接至电连接件28A，其可以包括金属焊盘、金属柱、焊料区域等。逻辑管芯LD具有电连接件28B，其接合至电连接件28A。桥接结构34还可以包括数字开关、路由器等，其可以包括电气路径以及开关(包括有源器件，诸如晶体管和控制电路)。
返回参考图1F，桥接管芯BD也可以包括无源器件42/43，诸如电容器、电阻器、电感器等。图26示出示例桥接管芯BD。根据一些实施例，桥接管芯BD包括深沟槽电容器42和/或金属-绝缘体-金属(MIM)电容器43。深沟槽电容器42可以包括电容器电极42B和电容器电极42B之间的绝缘体42A，其中深沟槽电容器42延伸到形成在半导体衬底20中的沟槽中，从而可以增加电容。MIM电容器43可以包括电容器电极43B和电容器电极43B之间的绝缘体43A，并且可以形成在桥接管芯BD中的互连结构22中。根据一些实施例，MIM电容器43和电气路径36(图25)延伸到桥接管芯BD中的同一互连结构22中。
图1G示出如图1B和图1C所示的参考截面1G-1G。由于示出的截面图中没有桥接管芯BD，所以在图1G中未示出桥接管芯BD。
如图1A、图1F和图1G所示，贯通孔26A形成在存储器管芯MD1和桥接管芯BD中，并穿过存储器管芯MD1和桥接管芯BD的半导体衬底20A。贯通孔26A用于将再分布结构50电和信号耦合至逻辑管芯LD。如图1F和图1G所示，形成贯通孔120(模制贯通孔)以穿过密封剂130，并且用于将再分布结构50电和信号耦合至逻辑管芯LD。
图2至图14示出根据本公开的一些实施例的如图1A、图1B、图1C、图1D、图1E、图1F和图1G所示的计算系统封装件100的形成中的中间阶段的截面图。根据一些实施例，如图2至图14所示，采用先RDL(“RDL”表示“再分布线”)的方法，其中在放置和接合管芯之前形成再分布结构50(图1A)。对应的工艺也示意性地反映在图28所示的工艺流程中。根据替代实施例，可以采用后RDL的方法，首先放置并接合管芯，然后形成再分布结构50。
图2示出载体102和形成在载体102上的释放膜104。载体102可以是玻璃载体、硅晶圆、有机载体等。根据一些实施例，载体102可以具有圆形的俯视图形状。释放膜104可以由聚合物基材料(诸如光热转换(LTHC)材料)形成，其能够在诸如激光束的载热辐射下分解，从而载体102可以从将在随后的工艺中形成的上面的结构脱离。根据本公开的一些实施例，释放膜104由环氧树脂基热释放材料形成，其涂覆在载体102上。
如图2至图5所示，在释放膜104上方形成多个介电层和多个RDL。参考图2，介电层54形成在释放膜104上。根据本发明的一些实施例，介电层54由聚合物形成，其也可以是使用光刻工艺(包括曝光工艺和显影工艺)可以图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。
根据一些实施例，在介电层54上方形成再分布线(RDL)106。相应的工艺被示出为图28中示出的工艺流程200中的工艺202。RDL 106的形成可以包括在介电层54上方形成金属晶种层(未示出)，在金属晶种层上方形成诸如光刻胶的图案化的掩模(未示出)，以及然后在暴露的晶种层上实施金属镀敷工艺。然后去除图案化的掩模和晶种层的由图案化的掩模覆盖的部分，从而留下如图2所示的RDL 106。根据本发明的一些实施例，晶种层包括钛层和位于钛层上方的铜层。例如，可使用物理气相沉积(PVD)等工艺形成晶种层。可以使用例如电化学镀敷工艺或无电镀工艺来执行镀敷。
参考图3，在RDL 106上形成介电层108。相应的工艺被示出为图28中示出的工艺流程200中的工艺204。介电层108的底面与RDL 106和介电层54的顶面接触。根据本发明的一些实施例，介电层108由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等的光敏材料。可选地，介电层108可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等的非有机介电材料。然后图案化介电层108以在介电层28中形成开口110。通过介电层108中的开口110暴露出RDL 106的一些部分。
接下来，参考图4，形成RDL 112以连接至RDL 106。相应的工艺被示出为图28中示出的工艺流程200中的工艺206。RDL 112包括位于介电层108上方的金属迹线(金属线)。RDL112还包括延伸到介电层108中的开口110中的通孔。也可以通过镀覆工艺形成RDL 112，其中，每个RDL 112包括晶种层(未示出)和位于晶种层上方的镀覆的金属材料。根据一些实施例，RDL 112的形成可以包括：沉积延伸到通孔开口中的毯式金属晶种层；以及形成和图案化第一镀敷掩模(诸如光刻胶)，其中在通孔开口上方形成开口并与之结合。然后执行镀覆工艺以镀覆金属材料，该金属材料完全填充通孔开口110(图3)，并且具有比介电层108的顶面高的一些部分。然后，去除第一镀敷掩模。
金属晶种层和镀敷材料可以由相同材料或不同材料形成。RDL 112中的金属材料可以包括金属或金属合金，包括铜、铝、钨或其合金。RDL 112包括RDL线(也称为迹线或迹线部分)112L和通孔部分(也称为通孔)112V，其中迹线部分112L位于介电层108上方，并且通孔部分112V位于介电层108中。由于在相同的镀敷工艺中形成迹线部分112L和通孔部分(也称为通孔)112V，所以在通孔112V和对应的上面的迹线部分112L之间没有可区分的界面。而且，每个通孔112V可以具有锥形轮廓，其上部比对应的下部宽。
还参考图4，在RDL 112上形成导电凸块114。相应的工艺被示出为图28中示出的工艺流程200中的工艺208。应当理解，尽管在如图所示的示例实施例中示出一个RDL层112，但是可以有更多的RDL层形成在RDL层112上方并与之电连接。后续的形成工艺涉及用于接合器件管芯MD1(图7)和BD(图1A)的接合方案，并且涉及器件管芯是朝下放置还是朝上放置，以及是否使用焊料接合、直接金属-金属接合或混合接合。因此，尽管以一个形成工艺为例进行了讨论，但是其他形成工艺和结构也在本公开的范围内。
根据一些实施例，使用第二镀敷掩模来镀敷导电凸块114，并且可以使用与用于镀敷RDL 112相同的金属晶种层来进行镀敷。导电凸块114可以包括铜、镍、金等。在镀敷导电凸块114之后，去除第二镀敷掩模，然后进行蚀刻工艺以去除金属晶种层的暴露部分，其先前被第二镀敷掩模和镀敷的RDL 112覆盖。金属晶种层也被认为是RDL 112的一部分。由此形成再分布结构50。
接下来，如图5所示，形成介电层116。相应的工艺被示出为图28中示出的工艺流程200中的工艺210。可以执行平坦化工艺以使导电凸块114和介电层116的顶面齐平。当要进行混合接合时，介电层116可以包括诸如氧化硅的含硅介电材料。根据替代实施例，可以在形成介电层116之后形成导电凸块114，并且形成工艺可以包括在介电层116中形成开口以露出下面的RDL 112，然后形成导电凸块114。对应的介电层116可以包括有机材料，诸如PBO、聚酰亚胺、BCB等，或包括无机介电材料，诸如氧化硅、氮化硅、氮氧化硅等。形成工艺还包括形成金属晶种层、形成镀敷掩模、镀敷金属材料、去除镀敷掩模、然后蚀刻金属晶种层的不期望的部分。
接下来，如图6所示，形成金属柱120。相应的工艺被示出为图28中示出的工艺流程200中的工艺212。形成工艺可以包括形成金属晶种层、在金属晶种层上方形成镀敷掩模(未示出，可以是光刻胶)、图案化镀敷掩模以露出下面的金属晶种层、然后在镀敷掩模的开口中镀敷金属材料。金属柱120替代地称为贯通孔或模制贯通孔，因为它们将穿过随后形成的密封材料(可以是模塑料)。镀敷的金属材料可以是铜或铜合金。金属柱120可以具有基本竖直和笔直的边缘。根据替代实施例，在先前工艺中不形成导电凸块114A。而是，它们以与形成金属柱120相同的工艺形成。
图7示出层级1管芯的放置/附接，其包括存储器管芯MD1和桥接管芯BD(也参见图1A)。相应的工艺被示出为图28中示出的工艺流程200中的工艺214。桥接管芯BD位于未示出的截面图中，因此未在图7中示出。根据一些实施例，层级1管芯MD1和BD朝下，并且层级1管芯MD1和BD中的电连接件122接合至导电凸块114。根据替代实施例，例如，如图16A、图16B和图16C所示，管芯MD1和BD可以朝上，并且器件管芯MD1和BD的后侧上的电连接件接合至导电凸块114。
存储器管芯MD1和桥接管芯BD可以具有预先形成为相应器件管芯的一部分的电连接件124A(诸如金属焊盘、金属凸块等)。电连接件124A位于相应管芯的后侧上。介电层126A也可以形成在存储器管芯MD1和桥接管芯BD的背面上。根据替代实施例，电连接件124A未预先形成在存储器管芯MD1和桥接管芯BD中。而是，贯通孔26A延伸到半导体衬底20的顶面和背面之间的中间水平，并且电连接件在存储器管芯MD1和桥接管芯BD被密封之后形成，并且在图8所示的工艺和图9所示的工艺之间形成。
接下来，如图8所示，将层级1管芯MD1和BD以及金属柱120密封在密封剂130中。相应的工艺被示出为图28中示出的工艺流程200中的工艺216。密封剂130填充相邻贯通孔120与层级1管芯MD1和BD之间的间隙。密封剂130可以包括模塑料、模制底部填充物、环氧树脂和/或树脂。当由模塑料形成时，密封剂130可以包括基础材料(其可以是聚合物、树脂、环氧树脂等)和基础材料中的填充剂颗粒。填充剂颗粒可以是SiO2、Al2O3、二氧化硅等的电介质颗粒，并且可以具有球形。而且，球形填充剂颗粒可以具有多种不同的直径。
然后，执行诸如化学机械抛光(CMP)步骤或机械研磨步骤的平坦化工艺以减薄密封剂130，直到暴露贯通孔120以及层级2管芯MD1和BD。由于平坦化工艺，贯通孔120的顶端与电连接件124A(如果预先形成的话)的顶面基本齐平(共面)，并且与密封剂130的顶面基本共面。贯穿说明书，层级1管芯和密封剂130统称为重构晶圆131。
参考图9，层级2管芯LD接合至层级1管芯MD1和BD以及贯通孔120(以及重构晶圆131)。相应的工艺被示出为图28中示出的工艺流程200中的工艺218。在所示的示例实施例中，层级2管芯LD直接接合至层级1管芯MD1和BD以及贯通孔120，之间没有RDL。根据替代实施例，包括介电层和RDL的附加扇出再分布结构(未示出)可以形成在层级1管芯MD1和BD以及贯通孔120上并与之连接，并且层级2管芯LD接合至附加扇出再分布结构。类似于层级1管芯，电连接件124B和介电层126B可以预先形成在层级2管芯LD中，或者可以形成在层级2管芯LD上方的另一附加扇出再分布结构中。
图10示出层级2管芯LD在密封剂132中的密封，其可以与密封剂130相似或相同。然后执行平坦化工艺以使层级2管芯LD和密封剂132的顶面齐平。相应的工艺被示出为图28中示出的工艺流程200中的工艺220。贯穿说明书，层级2管芯LD和密封剂132统称为重构晶圆133。
在图9和图10所示的示例实施例中，首先放置并密封层级1管芯以形成重构晶圆131，并且通过管芯-晶圆接合将离散的层级2管芯放置在重构晶圆131上。管芯-晶圆接合工艺的立体图如图23所示，其中重构晶圆131包括层级1管芯MD1和BD以及密封剂130。层级2管芯LD放置在重构晶圆131上。图24示出替代实施例，其中重构晶圆131和133都被预先形成，并且重构晶圆133通过晶圆-晶圆接合来接合至重构晶圆131。类似于图23和图24中所示，层级3管芯MD3也可以通过管芯-晶圆接合或晶圆-晶圆接合来接合至层级2管芯。
参考图11，层级3管芯MD3接合至层级2管芯LD(以及重构晶圆133)。相应的工艺被示出为图28中示出的工艺流程200中的工艺222。在所示的示例实施例中，层级3管芯MD3直接接合至层级2管芯LD，之间没有RDL。根据替代实施例，包括介电层和RDL的附加扇出再分布结构(未示出)可以形成在层级2管芯LD上并与之连接，并且层级3管芯MD3接合至附加扇出再分布结构。
图12示出层级3管芯MD3在密封剂134中的密封，其可以与密封剂130和/或132相似或相同。相应的工艺被示出为图28中示出的工艺流程200中的工艺224。然后执行平坦化工艺以使层级3管芯MD3和密封剂134的顶面齐平。层级3管芯MD3和密封剂134统称为重构晶圆135。贯穿说明书，包括介电层54和上面的结构的结构称为重构晶圆100，其也被称为计算系统封装件100。接下来，例如，通过将激光束投射到释放膜104上，使释放膜104分解，将重构晶圆100从载体102剥离(图11)。相应的工艺被示出为图28中示出的工艺流程200中的工艺226。
图13示出电连接件142的形成，其可以包括焊料区域、金属焊盘、金属柱或其组合。相应的工艺被示出为图28中示出的工艺流程200中的工艺228。形成工艺可以包括在介电层54中形成开口以及形成延伸到开口中以接触RDL 106的电连接件142。
图14示出将重构晶圆100接合至封装组件144，其可以是或可以包括印刷电路板、封装衬底、硅中间件、有机中间件、电源模块、插座等。相应的工艺被示出为图28中示出的工艺流程200中的工艺230。底部填充剂146被分配到重构晶圆100和封装组件144之间的间隙中。由此形成封装件148。根据一些实施例，可以是适配器、插座(包括用于插入销的销孔)等的连接件152可以形成在封装件148中，例如附接至封装组件144，使得封装件148中的电路可以电连接至外部组件。
根据一些实施例，未被锯切的整个重构晶圆100接合至封装组件144，并且包括在所得的封装件148中。因此，封装件148中的重构晶圆100可以具有圆形俯视图，类似于图23和图24所示。根据替代实施例，修整重构晶圆100以去除没有器件管芯和导线的部分，而不修整包括器件的部分和包含导线的部分。根据又一替代实施例，沿着划线141(图13)将重构晶圆100锯成多个相同的封装件，每个封装件包括如图13所示的所有示出的多个器件管芯，并且使用相同的封装件之一来形成如图14所示的封装件。
图27示出图14中的区域150的放大视图。如图27所示，密封剂130包括基础材料130A和基础材料130A中的填充剂颗粒130B。密封剂132包括基础材料132A和基础材料130A中的填充剂颗粒132B。密封剂134包括基础材料134A和基础材料134A中的填充剂颗粒134B。由于没有在密封剂130的底面上执行平坦化，所以与再分布结构50接触的球形颗粒130B被圆化，并且该圆化的表面与再分布结构50接触。密封剂130的与密封剂132接触的部分(或附加再分布结构(如果有的话))在图8所示的步骤中已经被平坦化。因此。在平坦化期间部分地抛光密封剂130的顶面处的球形颗粒130B，因此将具有基本为平面的顶面。类似地，在密封剂132和134的每一个中，底面处的球形颗粒132B/134B未被抛光，而是球形，而顶面处的球形颗粒132B/134B被抛光，并且是具有圆形底面和平坦顶面的部分为球形的颗粒。
图15A、图15B、图15C、图16A、图16B、图16C、图17A、图17B、图17C、图19A、图19B、图20A、图20B、图21A、图21B、图22A和图22B示出根据替代实施例的计算系统封装件100的截面图。这些实施例类似于图1A、图1B、图1C、图1D、图1E、图1F和图1G(以及图2至13)中所示的实施例，其中一些部分被修改。因此，只要适用，在先前实施例中提供的讨论也可以应用于这些实施例。
图15A、图15B、图15C、图16A、图16B、图16C、图17A、图17B和图17C所示的实施例也可以从图1B和图1C中参考截面1A-1A、1F-1F和1G-1G获得。
图15A、图15B和图15C示出根据一些实施例的计算系统封装件100。这些实施例类似于图1A、图1B、图1C、图1D、图1E、图1F和图1G(也是图13中的结构)中的实施例，除了在图13中，每个存储器管芯MD1和MD3是单个存储器管芯，而在图15A、图15B和图15C的实施例中，可以使用存储器堆叠件MD1’和MD3’，其分别包括多个堆叠的存储器管芯MD1和MD3。多个存储器管芯MD1可以通过形成在其中的衬底贯通孔互连。根据这些实施例，层级1管芯、层级2管芯和层级3管芯朝下。层级3管芯MD3也可以是管芯堆叠件MD3’的一部分。
图16A、图16B和图16C示出根据一些实施例的计算系统封装件100。这些实施例类似于图1A、图1B、图1C、图1D、图1E、图1F和图1G(也是图13中的结构)中的实施例，除了在图13中，层级1管芯MD1和BD朝下，而在图16A、图16B和图16C的实施例中，层级1管芯MD1和BD朝上。层级2管芯LD和层级3管芯MD3仍然朝下。
图17A、图17B和图17C示出根据一些实施例的计算系统封装件100。这些实施例类似于图15A、图15B和图15C中的实施例，除了在图15A、图15B和图15C中，存储器管芯MD1和桥接管芯BD朝下，而在图17A、图17B和图17C的实施例中，存储器管芯MD1和桥接管芯BD朝上。层级2管芯LD和层级3管芯MD3仍然朝下。
图18A和图18B分别示出根据一些实施例的计算系统封装件100的俯视图和仰视图，这些实施例与图1B和图1C所示的实施例相似，除了互连四个逻辑管芯的桥接管芯BD(标记为BD1)之外，可以添加桥接管芯BD(标记为BD2)以互连两个相邻的逻辑管芯LD。根据替代实施例，不形成桥接管芯BD1，而形成桥接管芯BD2。在随后的图19A、图19B、图20A、图20B、图21A、图21B、图22A和图22B中，其附图标记包括字母“A”的附图是从图18A和图18B中的参考截面A-A获得的，附图标记包括字母“B”的附图是从图18A和图18B中的参考截面B-B获得的。
图19A和图19B示出根据一些实施例的计算系统封装件100。这些实施例类似于图1A、图1B、图1C、图1D、图1E、图1F和图1G(也是图13中的结构)中的实施例，除了添加了桥接管芯BD2，并且每个所示的桥接管芯BD2互连两个层级2管芯LD，而不是互连四个层级2管芯作为桥接管芯BD1。层级1和层级3中的存储器管芯是单个存储器管芯。
图20A和图20B示出根据一些实施例的计算系统封装件100。这些实施例类似于图19A和图19B中的实施例，除了在图20A和图20B中，使用存储器管芯堆叠件MD1’和MD3’。
图21A和图21B示出根据一些实施例的计算系统封装件100。这些实施例类似于图19A和图19B中的实施例，除了在图19A和图19B中，层级1管芯MD1和BD1朝下，而在图21A和图21B中，层级1管芯MD1和BD1朝上。
图22A和图22B示出根据一些实施例的计算系统封装件100。这些实施例类似于图20A和图20B中的实施例，除了在图20A和图20B中，桥接管芯BD和存储器管芯堆叠件MD1’中的层级1管芯MD1朝下，而在图22A和图22B中，桥接管芯BD和存储器管芯堆叠件MD1’中的层级1管芯MD1朝上。
本发明的实施例具有一些有利特征。通过形成包括三个层级的计算系统封装件，其中中间层级具有逻辑管芯，而在上部层级和下部层级中具有存储器管芯，逻辑管芯具有到存储器管芯的最短路径。形成桥接管芯以互连相邻的逻辑管芯。由于采用了逻辑管芯、存储器管芯和桥接管芯的阵列，所以系统的可扩展性得到改进。可以提高计算效率，可以增加系统的带宽，并且可以减少延迟。
根据本公开的一些实施例，方法包括形成重构晶圆，包括：在载体上方形成再分布结构；在再分布结构上方接合第一多个存储器管芯；在再分布结构上方接合多个桥接管芯；在第一多个存储器管芯和多个桥接管芯上方接合多个逻辑管芯，其中，多个桥接管芯中的每个互连多个逻辑管芯中的四个，并且与多个逻辑管芯中的四个的角部区域重叠；以及在多个逻辑管芯上方接合第二多个存储器管芯，其中，多个逻辑管芯形成第一阵列，并且第二多个存储器管芯形成第二阵列。根据实施例，该方法还包括将封装组件接合至重构晶圆以形成附加封装件。根据实施例，在将封装组件接合至重构晶圆时，重构晶圆包括第一阵列和第二阵列。根据实施例，该方法还包括将插座附接至附加封装件，其中，在附接插座之后的时间，重构晶圆包括第一阵列和第二阵列两者。根据实施例，该方法还包括：将第一多个存储器管芯和多个桥接管芯密封在第一密封剂中；将多个逻辑管芯密封在第二密封剂中；以及将第二多个存储器管芯密封在第三密封剂中。根据实施例，重构晶圆在第一密封剂和第三密封剂中没有逻辑管芯，并且在第二密封剂中没有存储器管芯。根据实施例，多个逻辑管芯具有与第一密封剂的顶面物理接触的底面。根据实施例，第二密封剂被密封在第一密封剂上方并且与第一密封剂物理接触。根据实施例，第一多个存储器管芯彼此相同，多个逻辑管芯彼此相同，并且第二多个存储器管芯彼此相同。根据实施例，多个逻辑管芯通过混合接合来接合至第一多个存储器管芯。根据实施例，通过管芯-晶圆接合来执行在第一多个存储器管芯和多个桥接管芯上方接合多个逻辑管芯。根据实施例，通过晶圆-晶圆接合工艺来执行在第一多个存储器管芯和多个桥接管芯上方接合多个逻辑管芯包括：密封第一多个存储器管芯和多个桥接管芯以形成第一重构晶圆；密封多个逻辑管芯以形成第二重构晶圆；以及通过晶圆-晶圆接合将第二重构晶圆接合至第一重构晶圆。
根据本公开的一些实施例，封装件包括：再分布结构；第一多个存储器管芯，位于再分布结构上方；多个桥接管芯，位于再分布结构上方；多个逻辑管芯，位于第一多个存储器管芯和多个桥接管芯上方，其中，多个桥接管芯中的每个互连多个逻辑管芯中的至少两个并且与多个逻辑管芯中的至少两个的角部区域重叠，其中，多个逻辑管芯彼此相同；以及第二多个存储器管芯，位于多个逻辑管芯上方并与之接合，其中，多个逻辑管芯形成第一阵列，并且第二多个存储器管芯形成第二阵列。根据实施例，第一多个存储器管芯彼此相同，第二多个存储器管芯彼此相同，多个逻辑管芯彼此相同，并且多个桥接管芯彼此相同。根据实施例，多个桥接管芯中还包括电容器。根据实施例，封装件还包括：第一密封剂，其中密封第一多个存储器管芯；第二密封剂，其中密封多个逻辑管芯，其中，多个逻辑管芯的底面接触第一密封剂的顶面；以及第三密封剂，其中密封第二多个存储器管芯。根据实施例，第三密封剂与第二密封剂物理接触。
根据本公开的一些实施例，封装件包括重构晶圆，该重构晶圆包括：再分布结构，包括多条再分布线；多个桥接管芯，位于再分布结构上方并与之接合；多个逻辑管芯，位于多个桥接管芯上方并与之接合，其中，多个桥接管芯中的至少一个接合至多个逻辑管芯中的四个的角部区域；以及第二多个存储器管芯，位于多个逻辑管芯上方并与之接合，其中，第二多个存储器管芯接合至多个逻辑管芯。根据实施例，封装件还包括接合至重构晶圆的封装组件。根据实施例，封装件还包括接合至封装组件的插座。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种形成封装件的方法，包括：
形成重构晶圆，包括：
在载体上方形成再分布结构；
在所述再分布结构上方接合第一多个存储器管芯；
在所述再分布结构上方接合多个桥接管芯；
在所述第一多个存储器管芯和所述多个桥接管芯上方接合多个逻辑管芯，其中，所述多个桥接管芯中的每个互连所述多个逻辑管芯中的四个并且与所述多个逻辑管芯中的四个的角部区域重叠；以及
在所述多个逻辑管芯上方接合第二多个存储器管芯，其中，所述多个逻辑管芯形成第一阵列，并且所述第二多个存储器管芯形成第二阵列。
2.根据权利要求1所述的方法，还包括：
将封装组件接合至所述重构晶圆以形成附加封装件。
3.根据权利要求2所述的方法，其中，在将所述封装组件接合至所述重构晶圆时，所述重构晶圆包括所述第一阵列和所述第二阵列。
4.根据权利要求3所述的方法，还包括：将插座附接至所述附加封装件，其中，在附接所述插座之后时，所述重构晶圆包括所述第一阵列和所述第二阵列两者。
5.根据权利要求1所述的方法，还包括：
将所述第一多个存储器管芯和所述多个桥接管芯密封在第一密封剂中；
将所述多个逻辑管芯密封在第二密封剂中；以及
将所述第二多个存储器管芯密封在第三密封剂中。
6.根据权利要求5所述的方法，其中，所述重构晶圆在所述第一密封剂和所述第三密封剂中没有逻辑管芯，并且在所述第二密封剂中没有存储器管芯。
7.根据权利要求5所述的方法，其中，所述多个逻辑管芯具有与所述第一密封剂的顶面物理接触的底面。
8.根据权利要求5所述的方法，其中，所述第二密封剂被密封在所述第一密封剂上方并且与所述第一密封剂物理接触。
9.一种封装件，包括：
再分布结构；
第一多个存储器管芯，位于所述再分布结构上方；
多个桥接管芯，位于所述再分布结构上方；
多个逻辑管芯，位于所述第一多个存储器管芯和所述多个桥接管芯上方，其中，所述多个桥接管芯中的每个互连所述多个逻辑管芯中的至少两个并且与所述多个逻辑管芯中的至少两个的角部区域重叠；以及
第二多个存储器管芯，位于所述多个逻辑管芯上方并与所述多个逻辑管芯接合，其中，所述多个逻辑管芯形成第一阵列，并且所述第二多个存储器管芯形成第二阵列。
10.一种封装件，包括：
重构晶圆，包括：
再分布结构，包括多条再分布线；
多个桥接管芯，位于所述再分布结构上方并接合至所述再分布结构；
多个逻辑管芯，位于所述多个桥接管芯上方并接合至所述多个桥接管芯，其中，所述多个桥接管芯中的至少一个接合至所述多个逻辑管芯中的四个的角部区域；以及
第二多个存储器管芯，位于所述多个逻辑管芯上方并接合至所述多个逻辑管芯，其中，所述第二多个存储器管芯接合至所述多个逻辑管芯。
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US9065722B2 (en) * 2012-12-23 2015-06-23 Advanced Micro Devices, Inc. Die-stacked device with partitioned multi-hop network
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US10289796B2 (en) * 2016-12-06 2019-05-14 Synopsys, Inc. Automated place-and-route method for HBM-based IC devices
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US11469206B2 (en) 2018-06-14 2022-10-11 Intel Corporation Microelectronic assemblies
US10825696B2 (en) 2018-07-02 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Cross-wafer RDLs in constructed wafers
US20200098692A1 (en) * 2018-09-26 2020-03-26 Intel Corporation Microelectronic assemblies having non-rectilinear arrangements
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US11621244B2 (en) 2019-11-15 2023-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
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