CN114678434B - Heterojunction battery capable of improving photoelectric conversion efficiency - Google Patents
Heterojunction battery capable of improving photoelectric conversion efficiency Download PDFInfo
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 143
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 66
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 66
- 239000010703 silicon Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 69
- 238000000151 deposition Methods 0.000 description 36
- XUIMIQQOPSSXEZ-NJFSPNSNSA-N silicon-30 atom Chemical compound [30Si] XUIMIQQOPSSXEZ-NJFSPNSNSA-N 0.000 description 26
- 230000008021 deposition Effects 0.000 description 21
- 230000000052 comparative effect Effects 0.000 description 9
- 238000007650 screen-printing Methods 0.000 description 9
- 239000002356 single layer Substances 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000001174 ascending effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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Abstract
A heterojunction battery for improving photoelectric conversion efficiency belongs to the technical field of solar cells and comprises an n-type silicon substrate and intrinsic amorphous silicon deposited on the front side and the back side of the n-type silicon substrate; the front surface of the n-type silicon substrate is sequentially provided with a front electrode, a first TCO layer, a mixed layer and intrinsic amorphous silicon from top to bottom, and the back surface of the n-type silicon substrate is sequentially provided with a back electrode, a second TCO layer, doped amorphous silicon and intrinsic amorphous silicon from bottom to top; wherein the mixed layer comprises a first p-type doped amorphous silicon andThe film layer, the first p-type doped amorphous silicon adopts a hollowed-out design, theThe film layer is filled and arranged at the hollowed-out part of the first p-type doped amorphous silicon, and the doped amorphous silicon is first n-type doped amorphous silicon; by the design of the mixed phase film layer, the upper limit of the HJT battery on the photo-generated current can be broken on the premise of ensuring that other parameters of the HJT battery are kept at the same level, so that the higher conversion efficiency can be achieved.
Description
Cross Reference to Related Applications
The application is based on the application number 2021116201937, and the application date is as follows: 2021, 12 months, 18 days, the name of the application is: a divisional application of a heterojunction battery for improving photoelectric conversion efficiency.
Technical Field
The invention belongs to the technical field of solar cell processing, and particularly relates to a heterojunction cell for improving photoelectric conversion efficiency.
Background
The front surface of the conventional HJT battery structure is generally made of intrinsic amorphous silicon superimposed with n-type amorphous silicon, the intrinsic amorphous silicon has a good passivation effect, the n-type amorphous silicon has an effect of electron selective transmission, the p-type amorphous silicon has an effect of hole selective transmission, but the photo-generated current of the HJT battery cannot be further improved all the time due to the fact that the intrinsic amorphous silicon and the n-type amorphous silicon have larger parasitic absorption.
Disclosure of Invention
The present invention is directed to a heterojunction battery with improved photoelectric conversion efficiency, so as to solve the problems set forth in the background art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
A heterojunction cell for improving photoelectric conversion efficiency comprises an n-type silicon substrate and intrinsic amorphous silicon deposited on the front and back surfaces of the n-type silicon substrate; the front surface of the n-type silicon substrate is sequentially provided with a front electrode, a first TCO layer, a mixed layer and intrinsic amorphous silicon from top to bottom, and the back surface of the n-type silicon substrate is sequentially provided with a back electrode, a second TCO layer, doped amorphous silicon and intrinsic amorphous silicon from bottom to top; wherein the mixed layer comprises a first p-type doped amorphous silicon and The film layer, the first p-type doped amorphous silicon adopts a hollowed-out design, and the/>The film layer is filled and arranged at the hollowed-out part of the first p-type doped amorphous silicon, and the doped amorphous silicon is first n-type doped amorphous silicon.
Compared with the prior art, the technical scheme has the following effects:
By the design of the mixed phase film layer, the upper limit of the HJT battery on the photo-generated current can be broken on the premise of ensuring that other parameters of the HJT battery are kept at the same level, so that the higher conversion efficiency can be achieved.
Preferably, the mixed layer comprises a second n-type doped amorphous silicon andThe second n-type doped amorphous silicon adopts a hollowed-out design, and the/>And the film layer filling is arranged at the hollow part of the second n-type doped amorphous silicon.
Preferably, the doped amorphous silicon is a second p-type doped amorphous silicon.
Preferably, the front electrode/back electrode is an all-metal electrode.
Preferably, the all-metal electrode includes a silver electrode or a copper electrode.
Preferably, the thickness of the first TCO layer is 80nm, and the thickness of the second TCO layer is 200nm.
Preferably, the thickness of the mixed layer is less than 10nm.
Drawings
FIG. 1 is a schematic overall structure of a first embodiment of the present invention;
FIG. 2 is a schematic overall structure of a second embodiment of the present invention;
FIG. 3 is a first schematic diagram of the test data table of the examples and comparative examples of the present invention;
FIG. 4 is a second schematic diagram of the test data table of the examples and comparative examples of the present invention.
In the figure: a 1-n type silicon substrate; 2-intrinsic amorphous silicon; 3-a mixed layer; 30-a first p-type doped amorphous silicon; 31-A film layer; 30' -second n-type doped amorphous silicon; 31' -/>A film layer; 4-a first TCO layer; 5-front electrode; 6-a first n-type doped amorphous silicon; a 6' -p-type doped amorphous silicon, a 7-second TCO layer; 8-a back electrode.
Detailed Description
The following description of the embodiments of the present invention will be made with reference to the accompanying drawings, in which it is evident that the embodiments described are only some embodiments of the present invention, but not all embodiments.
A heterojunction cell for improving photoelectric conversion efficiency as shown in fig. 1-2 comprises an n-type silicon substrate 1, and intrinsic amorphous silicon 2 deposited on the front and back surfaces of the n-type silicon substrate 1; the front surface of the n-type silicon substrate 1 is sequentially provided with a front electrode 5, a first TCO layer 4, a mixed layer 3 and intrinsic amorphous silicon 2 from top to bottom, and the back surface of the n-type silicon substrate 1 is sequentially provided with a back electrode 8, a second TCO layer 7, doped amorphous silicon and intrinsic amorphous silicon 2 from bottom to top; the front electrode 5/the back electrode 8 are all-metal electrodes, and the all-metal electrodes comprise silver electrodes or copper electrodes, so that the upper limit of the HJT battery to photo-generated current can be broken on the premise of ensuring that other parameters of the HJT battery keep the same level through the design of the mixed-phase film layer, and the higher conversion efficiency can be achieved.
To further illustrate the mixed phase film design described in the above effects, in a first embodiment, the mixed layer 3 includes a first p-type doped amorphous silicon 30 andThe film 31, the first p-type doped amorphous silicon 30 is hollow out, and the/>The film layer 31 is filled and arranged at the hollowed-out part of the first p-type doped amorphous silicon 30; the conventional first p-type doped amorphous silicon 30 contained in the film layer has good hole selective transmission property and better contact with the first TCO layer 4; additional part of the film/>The film 31 has a certain hole selective transport, and at the same time, has high transparency, so that the photo-generated current level can be greatly improved.
Specifically, when a silicon wafer is deposited on a CVD apparatus, it is required to deposit a film layer on a carrier plate in a deposition chamber inside the CVD apparatus, and thus, the preparation of the mixed layer 3 specifically includes the steps of:
1. Firstly, placing a silicon wafer to be prepared on a carrier plate, then fixing a mask plate designed in advance on the upper surface of the silicon wafer, wherein the hollowed-out part of the mask plate corresponds to a structure of a film layer to be deposited, and the rest part is shielded;
2. Similarly, after one film in the mixed layer 3 is prepared, the mask plate is replaced, so that the shielding area corresponds to the previous deposition area, the previous shielding area is changed into a hollowed-out area, and finally, the mixed layer 3 structure is formed by deposition;
the mask plate designed in advance in the step 1 is hollowed out, so that the deposited film layer is attached to the surface of the silicon wafer to be prepared through the hollowed-out part.
In addition, for simplicity of explanation, the preparation process of the hybrid layer 3 is referred to as "hard mask method" in the following preparation process.
In addition, in order to ensure a stable structure of the heterojunction cell, the doped amorphous silicon is a first n-type doped amorphous silicon 6.
In a second embodiment, the hybrid layer 3 comprises a second n-type doped amorphous silicon 30' andFilm layer 31 ', wherein the second n-type doped amorphous silicon 30' adopts a hollowed-out design, and the/>The film layer 31 'is filled in the hollow part of the second n-type doped amorphous silicon 30'; the second n-type doped amorphous silicon 30' contained in the film layer has good electron selective transmission property and better contact with the first TCO layer 4; at the same time, another part of the film layer/>The film 31' has certain electron selective transmission, has higher transparency, and can greatly improve the photo-generated current level.
In addition, the doped amorphous silicon is second p-type doped amorphous silicon 6'.
It is noted that the thickness of the first TCO layer 4 is 80nm, the thickness of the second TCO layer 7 is 200nm, and the thickness of the mixed layer 3 is less than 10nm.
In order to more clearly express the structural constitution of the heterojunction cell in the above scheme, the specific steps for preparing the heterojunction cell in the above scheme are as follows:
Example 1:
firstly, selecting a textured n-type silicon substrate 1, and preparing the textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
next, deposition of back intrinsic amorphous silicon 2 on the n-type silicon substrate 1;
Secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
Then, the front surface of the n-type silicon substrate 1 is deposited with intrinsic amorphous silicon 2;
Then, adopting a hard mask method to deposit a mixed layer 3 on the front surface of the battery, wherein the thickness of the mixed layer 3 is 9nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and A film layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6 ', the mixed layer 3 is the second n-type doped amorphous silicon 30' and/>The film layer 31', specifically, the hard mask method respectively deposits a single layer in the mixed layer 3 through templates;
further, TCO film deposition is carried out on the front side and the back side of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Example 2:
firstly, selecting a textured n-type silicon substrate 1, and preparing the textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
next, deposition of back intrinsic amorphous silicon 2 on the n-type silicon substrate 1;
Secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
Then, the front surface of the n-type silicon substrate 1 is deposited with intrinsic amorphous silicon 2;
then, adopting a hard mask method to deposit a mixed layer 3 on the front surface of the battery, wherein the thickness of the mixed layer 3 is 5nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and A film layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6 ', the mixed layer 3 is the second n-type doped amorphous silicon 30' and/>The film layer 31', specifically, the hard mask method respectively deposits a single layer in the mixed layer 3 through templates;
further, TCO film deposition is carried out on the front side and the back side of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Example 3:
firstly, selecting a textured n-type silicon substrate 1, and preparing the textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
next, deposition of back intrinsic amorphous silicon 2 on the n-type silicon substrate 1;
Secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
Then, the front surface of the n-type silicon substrate 1 is deposited with intrinsic amorphous silicon 2;
Then, adopting a hard mask method to deposit a mixed layer 3 on the front surface of the battery, wherein the thickness of the mixed layer 3 is 1nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and A film layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6 ', the mixed layer 3 is the second n-type doped amorphous silicon 30' and/>The film layer 31', specifically, the hard mask method respectively deposits a single layer in the mixed layer 3 through templates;
further, TCO film deposition is carried out on the front side and the back side of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 1:
firstly, selecting a textured n-type silicon substrate 1, and preparing the textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
next, deposition of back intrinsic amorphous silicon 2 on the n-type silicon substrate 1;
Secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
Then, the front surface of the n-type silicon substrate 1 is deposited with intrinsic amorphous silicon 2;
then, depositing first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6' is 9nm;
further, TCO film deposition is carried out on the front side and the back side of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 2:
firstly, selecting a textured n-type silicon substrate 1, and preparing the textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
next, deposition of back intrinsic amorphous silicon 2 on the n-type silicon substrate 1;
Secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
Then, the front surface of the n-type silicon substrate 1 is deposited with intrinsic amorphous silicon 2;
then, depositing first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6' is 5nm;
further, TCO film deposition is carried out on the front side and the back side of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 3:
firstly, selecting a textured n-type silicon substrate 1, and preparing the textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
next, deposition of back intrinsic amorphous silicon 2 on the n-type silicon substrate 1;
Secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
Then, the front surface of the n-type silicon substrate 1 is deposited with intrinsic amorphous silicon 2;
then, depositing first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6' is 1nm;
further, TCO film deposition is carried out on the front side and the back side of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 4:
firstly, selecting a textured n-type silicon substrate 1, and preparing the textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
next, deposition of back intrinsic amorphous silicon 2 on the n-type silicon substrate 1;
Secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
Then, the front surface of the n-type silicon substrate 1 is deposited with intrinsic amorphous silicon 2;
Then, depositing first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30' is 9nm;
further, TCO film deposition is carried out on the front side and the back side of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 5:
firstly, selecting a textured n-type silicon substrate 1, and preparing the textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
next, deposition of back intrinsic amorphous silicon 2 on the n-type silicon substrate 1;
Secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
Then, the front surface of the n-type silicon substrate 1 is deposited with intrinsic amorphous silicon 2;
then, depositing first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30' is 5nm;
further, TCO film deposition is carried out on the front side and the back side of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 6:
firstly, selecting a textured n-type silicon substrate 1, and preparing the textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
next, deposition of back intrinsic amorphous silicon 2 on the n-type silicon substrate 1;
Secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
Then, the front surface of the n-type silicon substrate 1 is deposited with intrinsic amorphous silicon 2;
then, depositing first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30' is 1nm;
further, TCO film deposition is carried out on the front side and the back side of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
It should be noted that in the present embodiment, the comparative example is not used，/>The reasons for (2) are as follows: the direct application of the single-layer film layer in the heterojunction battery can bring a lot of performance attenuation, and the single-layer film still has a larger gap from amorphous silicon from the commercialization perspective or the technical advantages and disadvantages, so that the comparison of relevant data is mainly carried out on the single-layer film layer such as n-type doped amorphous silicon and p-type doped amorphous silicon and the mixed phase film layer designed by us, and the comparison data are shown in fig. 3 and 4:
Wherein A in the table represents Mixed phase film layer, B represents/>The mixed phase film layer, C represents p-type doped amorphous silicon, D represents n-type doped amorphous silicon, and comparison data shows that the voltage value is obviously in an ascending change along with the gradual increase of the thickness of the film layer, and in addition, under the condition that the film layers are in the same specification, the current density, the filling factor and the conversion efficiency are improved to a certain extent.
In the description of the present invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a number" is two or more. In addition, the term "include" and any variations thereof are intended to cover a non-exclusive inclusion.
The invention has been described in terms of embodiments, and the device can be modified and improved without departing from the principles of the invention. It should be noted that all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.
Claims (1)
1. A heterojunction cell for improving photoelectric conversion efficiency comprises an n-type silicon substrate (1) and intrinsic amorphous silicon (2) deposited on the front and back surfaces of the n-type silicon substrate (1); the method is characterized in that: the front surface of the n-type silicon substrate (1) is sequentially provided with a front electrode (5), a first TCO layer (4), a mixed layer (3) and intrinsic amorphous silicon (2) from top to bottom, and the back surface of the n-type silicon substrate (1) is sequentially provided with a back electrode (8), a second TCO layer (7), doped amorphous silicon and intrinsic amorphous silicon (2) from bottom to top; wherein the hybrid layer (3) comprises a first p-type doped amorphous silicon (30) andThe film layer (31) is formed by adopting a hollowed-out design of the first p-type doped amorphous silicon (30), and the/>The film layer (31) is filled at the hollowed-out part of the first p-type doped amorphous silicon (30); the doped amorphous silicon is first n-type doped amorphous silicon (6), the front electrode (5)/the back electrode (8) is an all-metal electrode, the all-metal electrode comprises a silver electrode or a copper electrode, the thickness of the first TCO layer (4) is 80nm, the thickness of the second TCO layer (7) is 200nm, and the thickness of the mixed layer (3) is smaller than 10nm.
Priority Applications (1)
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| CN113990972A (en) | 2022-01-28 |
| CN113990972B (en) | 2022-06-21 |
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