CN113990972B - Heterojunction battery for improving photoelectric conversion efficiency - Google Patents
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 137
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 67
- 239000010703 silicon Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000013461 design Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000012528 membrane Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 74
- 238000000151 deposition Methods 0.000 description 49
- XUIMIQQOPSSXEZ-NJFSPNSNSA-N silicon-30 atom Chemical compound [30Si] XUIMIQQOPSSXEZ-NJFSPNSNSA-N 0.000 description 26
- 230000008021 deposition Effects 0.000 description 13
- 230000000052 comparative effect Effects 0.000 description 9
- 238000007650 screen-printing Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 6
- 239000002356 single layer Substances 0.000 description 5
- 238000012360 testing method Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000001174 ascending effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
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- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
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- H01L31/03529—Shape of the potential jump barrier or surface barrier
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0376—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
- H01L31/03762—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors including only elements of Group IV of the Periodic System
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Abstract
A heterojunction cell for improving photoelectric conversion efficiency belongs to the technical field of solar cells and comprises an n-type silicon substrate and intrinsic amorphous silicon deposited on the front surface and the back surface of the n-type silicon substrate; the front surface of the n-type silicon substrate is sequentially provided with a front surface electrode, a first TCO layer, a mixed layer and intrinsic amorphous silicon from top to bottom, and the back surface of the n-type silicon substrate is sequentially provided with a back surface electrode, a second TCO layer, doped amorphous silicon and intrinsic amorphous silicon from bottom to top; by the film layer design of the mixed phase, the upper limit of the HJT battery to the photo-generated current can be broken on the premise of ensuring that other parameters of the HJT battery keep the same level, so that the HJT battery can achieve higher conversion efficiency.
Description
Technical Field
The invention belongs to the technical field of solar cell processing, and particularly relates to a heterojunction cell for improving photoelectric conversion efficiency.
Background
The front surface of the existing HJT cell structure generally adopts intrinsic amorphous silicon superposed with n-type amorphous silicon, the intrinsic amorphous silicon has a good passivation effect, the n-type amorphous silicon generally has more effect of electron selective transmission, the p-type amorphous silicon generally has more effect of hole selective transmission, but the two have larger parasitic absorption, so the photoproduction current of the HJT cell can not be further improved all the time.
Disclosure of Invention
The present invention is directed to a heterojunction battery with improved photoelectric conversion efficiency, which solves the above-mentioned problems of the prior art.
In order to achieve the purpose, the invention provides the following technical scheme:
a heterojunction cell for improving photoelectric conversion efficiency comprises an n-type silicon substrate and intrinsic amorphous silicon deposited on the front surface and the back surface of the n-type silicon substrate; the front surface of the n-type silicon substrate is sequentially provided with a front surface electrode, a first TCO layer, a mixed layer and intrinsic amorphous silicon from top to bottom, and the back surface of the n-type silicon substrate is sequentially provided with a back surface electrode, a second TCO layer, doped amorphous silicon and intrinsic amorphous silicon from bottom to top.
Compared with the prior art, the technical scheme has the following effects:
by the film layer design of the mixed phase, the upper limit of the HJT battery to the photo-generated current can be broken on the premise of ensuring that other parameters of the HJT battery keep the same level, so that the HJT battery can achieve higher conversion efficiency.
Preferably, the mixed layer includes p-type doped amorphous silicon and
a film layer, the p-type doped amorphous silicon adopts a hollow design, the film layer
The film layer is filled in the hollow-out position of the p-type doped amorphous silicon.
Preferably, the doped amorphous silicon is n-type doped amorphous silicon.
Preferably, the mixed layer includes n-type doped amorphous silicon and
a film layer, wherein the n-type doped amorphous silicon adopts a hollow design, the film layer
And the film layer is filled in the hollow-out part of the n-type doped amorphous silicon.
Preferably, the doped amorphous silicon is p-type doped amorphous silicon.
Preferably, the front/back electrodes are all metal electrodes.
Preferably, the all-metal electrode includes a silver electrode or a copper electrode.
Preferably, the thickness of the first TCO layer is 80nm and the thickness of the second TCO layer is 200 nm.
Preferably, the thickness of the mixed layer is less than 10 nm.
Drawings
FIG. 1 is a schematic view of the overall structure of a first embodiment of the present invention;
FIG. 2 is a schematic view of the overall structure of a second embodiment of the present invention;
FIG. 3 is a first schematic view of a test data table of examples and comparative examples of the present invention;
FIG. 4 is a second schematic diagram of a test data table of examples and comparative examples in the present invention.
In the figure: a 1-n type silicon substrate; 2-intrinsic amorphous silicon; 3-mixing layer; 30-first p-type doped amorphous silicon; 31-
A film layer; 30' -a second n-type doped amorphous silicon; 31-
A film layer; 4-a first TCO layer; 5-a front electrode; 6-first n-type doped amorphous silicon; 6' -p-type doped amorphous silicon, 7-a second TCO layer; 8-back electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be described below in detail and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments.
1-2, a heterojunction cell for improving photoelectric conversion efficiency comprises an n-type silicon substrate 1, and intrinsic amorphous silicon 2 deposited on the front and back surfaces of the n-type silicon substrate 1; the front surface of the n-type silicon substrate 1 is sequentially provided with a front surface electrode 5, a first TCO layer 4, a mixed layer 3 and intrinsic amorphous silicon 2 from top to bottom, and the back surface of the n-type silicon substrate 1 is sequentially provided with a back surface electrode 8, a second TCO layer 7, doped amorphous silicon and intrinsic amorphous silicon 2 from bottom to top; the front electrode 5/the back electrode 8 are all-metal electrodes, the all-metal electrodes comprise silver electrodes or copper electrodes, and the upper limit of the HJT cell on the photoproduction current can be broken through by the film layer design of the mixed phase on the premise of ensuring that other parameters of the HJT cell are kept at the same level, so that the higher conversion efficiency can be achieved.
To further illustrate the film layer design of the mixed phase in the above effect, in the first embodiment, the mixed layer 3 includes a first p-type dopantHetero amorphous silicon 30 and
a film layer 31, the first p-type doped amorphous silicon 30 adopts a hollow design, the film layer
The film layer 31 is filled in the hollow part of the first p-type doped amorphous silicon 30; the effect is that the conventional first p-type doped amorphous silicon 30 contained in the film layer has good hole selective transmission property and is in good contact with the first TCO layer 4; another part of the film layer
The film layer 31 has a certain hole selective transmission, and meanwhile, the transparency is high, so that the level of photo-generated current can be greatly improved.
Specifically, when a silicon wafer is deposited on a CVD apparatus, the silicon wafer needs to be placed on a carrier plate and enter a deposition chamber inside the CVD apparatus for film deposition, and therefore, the preparation of the mixed layer 3 specifically comprises the following steps:
1. firstly, placing a silicon wafer to be prepared on a carrier plate, fixing a pre-designed mask plate on the upper surface of the silicon wafer, wherein the hollow part of the mask plate corresponds to a film layer structure to be deposited, and the rest part is shielded;
2. similarly, after preparing one film in the mixed layer 3, replacing the mask plate to enable the shielding area to correspond to the previous deposition area, wherein the previous shielding area is changed into a hollow area, and finally depositing to form a mixed layer 3 structure;
the mask plate designed in advance in the step 1 is used for hollowing out the complete mask plate, so that the deposited film layer is attached to the surface of the silicon wafer to be prepared through the hollow part.
In addition, for the sake of simplicity of explanation, the processes for producing the hybrid layer 3 are referred to in the following production processes and are all named "hard mask method".
In addition, in order to ensure a stable structure of the heterojunction cell, the doped amorphous silicon is first n-type doped amorphous silicon 6.
In the second embodiment, the mixed layer 3 includes the second n-type doped amorphous silicon 30 ″, and
a film layer 31 ', the second n-type doped amorphous silicon 30' being designed by hollowing, the second n-type doped amorphous silicon being a film layer of a predetermined thickness
The film layer 31 'is filled and arranged in the hollow part of the second n-type doped amorphous silicon 30'; the effect is that the second n-type doped amorphous silicon 30' contained in the film layer has good electron selective transmission property and is in good contact with the first TCO layer 4; at the same time, the other part of the film layer
The film layer 31' has certain electron selective transmission, has high transparency, and can greatly improve the level of photo-generated current.
In addition, the doped amorphous silicon is second p-type doped amorphous silicon 6'.
It is noted that the thickness of the first TCO layer 4 is 80nm, the thickness of the second TCO layer 7 is 200nm and the thickness of the hybrid layer 3 is less than 10 nm.
In order to express the structure of the heterojunction battery in the above scheme more clearly, the specific steps for preparing the heterojunction battery in the above scheme are as follows:
example 1:
firstly, selecting a textured n-type silicon substrate 1, and preparing a texture surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
then, depositing intrinsic amorphous silicon 2 on the back surface of the n-type silicon substrate 1;
secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
then, depositing intrinsic amorphous silicon 2 on the front surface of the n-type silicon substrate 1;
then, the deposition of the mixed layer 3 is carried out on the front surface of the battery by adopting a hard mask method, therebyThe thickness of the mixed layer 3 is 9 nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and
a membrane layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6', the mixed layer 3 is the second n-type doped amorphous silicon 30 ″, and
film layer 31', specifically, the hard mask method is to deposit the single layer in the mixed layer 3 through templates respectively;
further, TCO film deposition is carried out on the front surface and the back surface of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Example 2:
firstly, selecting a textured n-type silicon substrate 1, and preparing a texture surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
then, depositing intrinsic amorphous silicon 2 on the back surface of the n-type silicon substrate 1;
secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
then, depositing intrinsic amorphous silicon 2 on the front side of the n-type silicon substrate 1;
then, depositing a mixed layer 3 on the front surface of the battery by adopting a hard mask method, wherein the thickness of the mixed layer 3 is 5 nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and
a membrane layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6 ″, the mixed layer 3 is the second n-type doped amorphous silicon 30 ″, and
film layer 31', specifically, the hardmask method is to deposit the monolayers in the mixed layer 3 through templates respectively;
further, TCO film deposition is carried out on the front surface and the back surface of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Example 3:
firstly, selecting a textured n-type silicon substrate 1, and preparing a texture surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
then, depositing intrinsic amorphous silicon 2 on the back surface of the n-type silicon substrate 1;
secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
then, depositing intrinsic amorphous silicon 2 on the front surface of the n-type silicon substrate 1;
then, depositing a mixed layer 3 on the front surface of the battery by adopting a hard mask method, wherein the thickness of the mixed layer 3 is 1 nm; wherein, when the doped amorphous silicon in S3 is selected as the first n-type doped amorphous silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and
a membrane layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6', the mixed layer 3 is the second n-type doped amorphous silicon 30 ″, and
film layer 31', specifically, the hard mask method is to deposit the single layer in the mixed layer 3 through templates respectively;
further, TCO film deposition is carried out on the front surface and the back surface of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 1:
firstly, selecting a textured n-type silicon substrate 1, and preparing a texture surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
then, depositing intrinsic amorphous silicon 2 on the back surface of the n-type silicon substrate 1;
secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
then, depositing intrinsic amorphous silicon 2 on the front surface of the n-type silicon substrate 1;
then, depositing first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6' is 9 nm;
further, TCO film deposition is carried out on the front surface and the back surface of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 2:
firstly, selecting a textured n-type silicon substrate 1, and preparing a textured surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
then, depositing intrinsic amorphous silicon 2 on the back surface of the n-type silicon substrate 1;
secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
then, depositing intrinsic amorphous silicon 2 on the front side of the n-type silicon substrate 1;
then, depositing first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6' is 5 nm;
further, TCO film deposition is carried out on the front surface and the back surface of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 3:
firstly, selecting a textured n-type silicon substrate 1, and preparing a texture surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
then, depositing intrinsic amorphous silicon 2 on the back surface of the n-type silicon substrate 1;
secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
then, depositing intrinsic amorphous silicon 2 on the front surface of the n-type silicon substrate 1;
then, depositing first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first p-type doped amorphous silicon 30/second p-type doped amorphous silicon 6' is 1 nm;
further, TCO film deposition is carried out on the front surface and the back surface of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 4:
firstly, selecting a textured n-type silicon substrate 1, and preparing a texture surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
then, depositing intrinsic amorphous silicon 2 on the back surface of the n-type silicon substrate 1;
secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
then, depositing intrinsic amorphous silicon 2 on the front surface of the n-type silicon substrate 1;
then, depositing first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30' is 9 nm;
further, TCO film deposition is carried out on the front surface and the back surface of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 5:
firstly, selecting a textured n-type silicon substrate 1, and preparing a texture surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
then, depositing intrinsic amorphous silicon 2 on the back surface of the n-type silicon substrate 1;
secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
then, depositing intrinsic amorphous silicon 2 on the front surface of the n-type silicon substrate 1;
then, depositing first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30' is 5 nm;
further, TCO film deposition is carried out on the front surface and the back surface of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 is prepared by screen printing techniques.
Comparative example 6:
firstly, selecting a textured n-type silicon substrate 1, and preparing a texture surface, namely constructing a pyramid-shaped light trapping structure on the surface of the n-type silicon substrate 1;
then, depositing intrinsic amorphous silicon 2 on the back surface of the n-type silicon substrate 1;
secondly, depositing doped amorphous silicon on the intrinsic amorphous silicon 2 on the back surface;
then, depositing intrinsic amorphous silicon 2 on the front surface of the n-type silicon substrate 1;
then, depositing first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30 'on the front surface of the battery by adopting a hard mask method, wherein the thickness of the first n-type doped amorphous silicon 6/second n-type doped amorphous silicon 30' is 1 nm;
further, TCO film deposition is carried out on the front surface and the back surface of the n-type silicon substrate 1;
finally, the front electrode 5/back electrode 8 are prepared by screen printing techniques.
It is worth mentioning that in this example, the comparative example is not used
，
The reason for (a) is as follows: the current single-layer film directly applied to the heterojunction cell brings many performance attenuation, and the single-layer film still has a large gap with amorphous silicon in terms of commercialization and technology superiority, so the comparison of the relevant data is mainly performed on the single-layer film of n-type doped amorphous silicon and p-type doped amorphous silicon and the mixed-phase film designed by us, and the comparison data is shown in fig. 3 and fig. 4:
wherein A in the table represents
Mixed phase film layer, B represents
The mixed phase film layer, C represents p-type doped amorphous silicon, D represents n-type doped amorphous silicon, and the comparison data shows that the voltage value obviously changes in an ascending way along with the gradual increase of the thickness of the film layer.
In the description of the present invention, it is to be understood that the terms "central," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientations and positional relationships indicated in the figures, which are based on the orientations and positional relationships shown in the figures, and are used for convenience in describing the invention and for simplicity in description, but do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a number" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
The present invention has been described in terms of embodiments, and several variations and modifications can be made to the device without departing from the principles of the present invention. It should be noted that all the technical solutions obtained by means of equivalent substitution or equivalent transformation, etc., fall within the protection scope of the present invention.
Claims (5)
1. A heterojunction cell for improving photoelectric conversion efficiency comprises an n-type silicon substrate (1) and intrinsic amorphous silicon (2) deposited on the front and back surfaces of the n-type silicon substrate (1); the method is characterized in that: the front surface of the n-type silicon substrate (1) is sequentially provided with a front surface electrode (5), a first TCO layer (4), a mixing layer (3) and intrinsic amorphous silicon (2) from top to bottom, and the back surface of the n-type silicon substrate (1) is sequentially provided with a back surface electrode (8), a second TCO layer (7), doped amorphous silicon and intrinsic amorphous silicon (2) from bottom to top; wherein the mixed layer (3) comprises a second n-type doped amorphous silicon (30') and
a membrane layer (31 '), the second n-type doped amorphous silicon (30') being of a hollowed-out design, the membrane layer being of a substantially planar structure
A film layer (31 ') is filled in the hollow-out part of the second n-type doped amorphous silicon (30 '), and the doped amorphous silicon is second p-type doped amorphous silicon (6 ').
2. The heterojunction cell of claim 1 wherein: the front electrode (5)/the back electrode (8) are all metal electrodes.
3. The heterojunction cell of claim 2 wherein said heterojunction cell comprises: the all-metal electrode comprises a silver electrode or a copper electrode.
4. The heterojunction cell of claim 1 wherein: the thickness of the first TCO layer (4) is 80nm, and the thickness of the second TCO layer (7) is 200 nm.
5. The heterojunction cell of claim 1 wherein: the thickness of the mixed layer (3) is less than 10 nm.
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