CN114464669A - 超结frd结构及其制作方法 - Google Patents

超结frd结构及其制作方法 Download PDF

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CN114464669A
CN114464669A CN202210192035.4A CN202210192035A CN114464669A CN 114464669 A CN114464669 A CN 114464669A CN 202210192035 A CN202210192035 A CN 202210192035A CN 114464669 A CN114464669 A CN 114464669A
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程炜涛
姚阳
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Shanghai Aiji Semiconductor Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/861Diodes
    • H01L29/868PIN diodes

Abstract

本发明提供了一种超结FRD结构及其制作方法,超结FRD结构包括正面金属区和背面金属区,还包括:N‑基区,所述N‑基区与所述正面金属区接触;N+基区,设置在所述N‑基区和所述背面金属区之间;所述N‑基区内设置有若干个P型区,且所述P型区与所述N‑基区形成横向PN结;所述P型区的侧方设置有P+区,且所述P+区与所述N‑基区形成纵向PN结。该结构通过引入横向的PN结结构,能够在器件反向耐压时,横向PN结和纵向PN结能够一起承担耐压,从而可以在不增厚N‑基区厚度、不改变N‑基区浓度的基础上提高器件的耐压值。

Description

超结FRD结构及其制作方法
技术领域
本发明涉及功率半导体技术领域,尤指一种超结FRD结构及其制作方法。
背景技术
IGBT(Insulated Gate Bipolar Transistor),绝缘栅双极型晶体管,是由BJT(双极型三极管)和MOS(绝缘栅型场效应管)组成的复合全控型电压驱动式功率半导体器件,兼有MOSFET的高输入阻抗和GTR的低导通压降两方面的优点。IGBT在使用时通常需要搭配FRD,用以在IGBT关断时续流。FRD常规是PIN结构,由纵向的PN结承担耐压,N-基区的厚度以及浓度决定其耐压值。随着FRD耐压值的升高,N-基区的厚度增大、浓度降低,伴随而来的问题是导通压降会增大,相应的静态损耗会增加。因此,需要一种能够在保证耐压的前提下,不改变FRD的N-基区厚度和浓度的FRD结构。
发明内容
本发明的目的是提供一种超结FRD结构及其制作方法,以解决高压FRD增加N-区厚度、降低N-区浓度带来的导通压降增大、静态损耗增加的技术问题。
本发明提供的技术方案如下:
本发明提供一种超结FRD结构,包括正面金属区和背面金属区,还包括:
N-基区,所述N-基区与所述正面金属区接触;
N+基区,设置在所述N-基区和所述背面金属区之间;
所述N-基区内设置有若干个P型区,且所述P型区与所述N-基区形成横向PN结;
所述P型区的侧方设置有P+区,且所述P+区与所述N-基区形成纵向PN结。
通过在正面金属区和背面金属区之间设置N-基区和N+基区,N-基区与正面金属区接触,N+基区设置在N-基区和背面金属区之间,且N-基区内设置有若干个P型区,P型区与N-基区形成横向PN结,P型区的侧方设置有P+区,P+区与N-基区形成纵向PN结,使得在器件反向耐压时,横向PN结和纵向PN结能够一起承担耐压,从而可以在不增厚N-基区厚度、不改变N-基区浓度的基础上提高器件的耐压值。
在一些实施方式中,所述P型区垂直于所述正面金属区和所述背面金属区设置,
所述P型区的一端与所述正面金属区接触,且所述P型区的另一端与所述N+基区存在间隙。
在一些实施方式中,所述N-基区与所述正面金属区之间形成肖特基接触。
在一些实施方式中,所述P+区的一侧均与所述正面金属区之间形成第一欧姆接触。
在一些实施方式中,所述肖特基接触区的宽度和所述第一欧姆接触区的宽度按照预设比例设置。
通过在N-基区与正面金属区之间形成肖特基接触,P+区的一侧与正面金属区之间形成第一欧姆接触,使得可以通过调节肖特基接触区的宽度与第一欧姆接触区的宽度的比例来调节器件的静态损耗和动态损耗,实现静动态参数的最优折中。具体的,相同尺寸条件下,肖特基接触区宽度占比越大,器件的动态损耗越优,从而利于高频应用使用;第一欧姆接触区的宽度占比越大,器件的静态损耗越优,从而利于低频应用使用。
在一些实施方式中,所述N+基区与所述背面金属区之间形成第二欧姆接触。
在一些实施方式中,若干个所述P型区均匀设置,且所述P型区的两侧均设置有所述P+区。
在一些实施方式中,所述N-基区内设置有若干个深槽,深槽内填充P型Si材料形成所述P型区。
另外,本发明还提供一种超结FRD结构的制作方法,包括步骤:
设置N+基区基底;
在所述N+基区基底上外延N-基区;
在所述N-基区上挖掘若干深槽,并在深槽内填充P型Si材料形成P型区;
在所述P型区的侧方通过涂胶、掩膜、显影、光刻、离子注入、热扩散形成P+区;
在正面沉积绝缘介质层,并通过光刻、刻蚀绝缘介质层形成孔开口;
在正面通过金属溅射或蒸金形成正面金属区;
在背面通过金属溅射或蒸金形成背面金属区。
另外,本发明还提供一种超结FRD结构的制作方法,包括步骤:
设置N-基区基底;
在所述N-基区基底上挖掘若干深槽,并在深槽内填充P型Si材料形成P型区;
在所述P型区的侧方通过掩膜、涂胶、光刻、离子注入、热扩散形成P+区;
在正面沉积绝缘介质层,并通过光刻、刻蚀绝缘介质层形成孔开口;
在正面通过金属溅射或蒸金形成正面金属区;
在背面通过离子注入、热扩散形成N+基区;
在背面通过金属溅射或蒸金形成背面金属区。
根据本发明提供的一种超结FRD结构及其制作方法,通过在正面金属区和背面金属区之间设置N-基区和N+基区,N-基区与正面金属区接触,N+基区设置在N-基区和背面金属区之间,且N-基区内设置有若干个P型区,P型区与N-基区形成横向PN结,P型区的侧方设置有P+区,P+区与N-基区形成纵向PN结,使得在器件反向耐压时,横向PN结和纵向PN结能够一起承担耐压,从而可以在不增厚N-基区厚度、不改变N-基区浓度的基础上提高器件的耐压值。
附图说明
下面将以明确易懂的方式,结合附图说明优选实施方式,对本方案的上述特性、技术特征、优点及其实现方式予以进一步说明。
图1是本发明实施例的整体结构示意图;
图2是本发明实施例的一种超结FRD结构制作方法流程示意图;
图3是本发明实施例的另一种超结FRD结构制作方法流程示意图。
图中标号:1-N+基区;2-N-基区;3-P型区;4-P+区;5-正面金属区;6-背面金属区。
具体实施方式
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对照附图说明本发明的具体实施方式。显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图,并获得其他的实施方式。
为使图面简洁,各图中只示意性地表示出了与本发明相关的部分,它们并不代表其作为产品的实际结构。另外,以使图面简洁便于理解,在有些图中具有相同结构或功能的部件,仅示意性地绘示了其中的一个,或仅标出了其中的一个。在本文中,“一个”不仅表示“仅此一个”,也可以表示“多于一个”的情形。
在一个实施例中,参考说明书附图图1,本发明提供一种超结FRD结构,包括正面金属区5和背面金属区6,还包括N-基区2和N+基区1。N-基区2与正面金属区5接触;N+基区1设置在N-基区2和背面金属区6之间。
N-基区2内设置有若干个P型区3,且P型区3与N-基区2形成横向PN结;P型区3的侧方设置有P+区4,且P+区4与N-基区2形成纵向PN结。
优选的,在本实施例中,若干个P型区3均匀设置,且P型区3的两侧均设置有P+区4。在其它实施例中,还可以根据需求,设置P型区3和P+区4不同的分布形式。
通过在正面金属区5和背面金属区6之间设置N-基区2和N+基区1,N-基区2与正面金属区5接触,N+基区1设置在N-基区2和背面金属区6之间,且N-基区2内设置有若干个P型区3,P型区3与N-基区2形成横向PN结,P型区3的侧方设置有P+区4,P+区4与N-基区2形成纵向PN结,使得在器件反向耐压时,横向PN结和纵向PN结能够一起承担耐压,从而可以在不增厚N-基区2厚度、不改变N-基区2浓度的基础上提高器件的耐压值。
在一个实施例中,P型区3垂直于正面金属区5和背面金属区6设置,P型区3的一端与正面金属区5接触,且P型区3的另一端与N+基区1存在间隙。
优选的,N-基区2内设置有若干个深槽,深槽内填充P型Si材料形成P型区3。
在一个实施例中,N-基区2与正面金属区5之间形成肖特基接触。
肖特基接触是指金属和半导体材料相接触的时候,在界面处半导体的能带弯曲,形成肖特基势垒,势垒的存在才导致了大的界面电阻。肖特基势垒是指具有整流特性的金属-半导体接触,就如同二极管具有整流特性,是金属-半导体边界上形成的具有整流作用的区域。
在一个实施例中,P+区4的一侧均与正面金属区5之间形成第一欧姆接触。
半导体与金属接触时,多会形成势垒层,但当半导体掺杂浓度很高时,电子可借隧道效应穿过势垒,从而形成低阻值的欧姆接触。
优选的,肖特基接触区的宽度和第一欧姆接触区的宽度按照预设比例设置。
通过在N-基区2与正面金属区5之间形成肖特基接触,P+区4的一侧与正面金属区5之间形成第一欧姆接触,使得可以通过调节肖特基接触区的宽度与第一欧姆接触区的宽度的比例来调节器件的静态损耗和动态损耗,实现静动态参数的最优折中。具体的,相同尺寸条件下,肖特基接触区宽度占比越大,器件的动态损耗越优,从而利于高频应用使用;第一欧姆接触区的宽度占比越大,器件的静态损耗越优,从而利于低频应用使用。
在一个实施例中,N+基区1与背面金属区6之间形成第二欧姆接触。
在一个实施例中,参考说明书附图图2,本发明还提供一种超结FRD结构的制作方法,包括步骤:
S10、设置N+基区基底。
S20、在N+基区基底上外延N-基区。
S30、在N-基区上挖掘若干深槽,并在深槽内填充P型Si材料形成P型区。
S40、在P型区的侧方通过涂胶、掩膜、显影、光刻、离子注入、热扩散形成P+区。
S50、在正面沉积绝缘介质层,并通过光刻、刻蚀绝缘介质层形成孔开口。
S60、在正面通过金属溅射或蒸金形成正面金属区。
S70、在背面通过金属溅射或蒸金形成背面金属区。
通过该方法能够制作上述的超结FRD结构,以实现在保证耐压的前提下,不改变FRD的N-基区厚度和浓度。
在一个实施例中,参考说明书附图图3,本发明还提供一种超结FRD结构的制作方法,包括步骤:
S11、设置N-基区基底。
S21、在N-基区基底上挖掘若干深槽,并在深槽内填充P型Si材料形成P型区。
S31、在P型区的侧方通过掩膜、涂胶、光刻、离子注入、热扩散形成P+区。
S41、在正面沉积绝缘介质层,并通过光刻、刻蚀绝缘介质层形成孔开口。
S51、在正面通过金属溅射或蒸金形成正面金属区。
S61、在背面通过离子注入、热扩散形成N+基区。
S71、在背面通过金属溅射或蒸金形成背面金属区。
通过该方法也能够制作上述的超结FRD结构,以实现在保证耐压的前提下,不改变FRD的N-基区厚度和浓度,具体制作方式,可以根据使用场景进行选择。
应当说明的是,上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。

Claims (10)

1.一种超结FRD结构,包括正面金属区和背面金属区,其特征在于,还包括:
N-基区,所述N-基区与所述正面金属区接触;
N+基区,设置在所述N-基区和所述背面金属区之间;
所述N-基区内设置有若干个P型区,且所述P型区与所述N-基区形成横向PN结;
所述P型区的侧方设置有P+区,且所述P+区与所述N-基区形成纵向PN结。
2.根据权利要求1所述的一种超结FRD结构,其特征在于,所述P型区垂直于所述正面金属区和所述背面金属区设置,
所述P型区的一端与所述正面金属区接触,且所述P型区的另一端与所述N+基区存在间隙。
3.根据权利要求1所述的一种超结FRD结构,其特征在于,所述N-基区与所述正面金属区之间形成肖特基接触。
4.根据权利要求3所述的一种超结FRD结构,其特征在于,所述P+区的一侧均与所述正面金属区之间形成第一欧姆接触。
5.根据权利要求4所述的一种超结FRD结构,其特征在于,所述肖特基接触区的宽度和所述第一欧姆接触区的宽度按照预设比例设置。
6.根据权利要求1所述的一种超结FRD结构,其特征在于,所述N+基区与所述背面金属区之间形成第二欧姆接触。
7.根据权利要求1所述的一种超结FRD结构,其特征在于,若干个所述P型区均匀设置,且所述P型区的两侧均设置有所述P+区。
8.根据权利要求1-7任一所述的一种超结FRD结构,其特征在于,所述N-基区内设置有若干个深槽,深槽内填充P型Si材料形成所述P型区。
9.一种基于权利要求1-8任一所述的超结FRD结构的制作方法,其特征在于,包括步骤:
设置N+基区基底;
在所述N+基区基底上外延N-基区;
在所述N-基区上挖掘若干深槽,并在深槽内填充P型Si材料形成P型区;
在所述P型区的侧方通过涂胶、掩膜、显影、光刻、离子注入、热扩散形成P+区;
在正面沉积绝缘介质层,并通过光刻、刻蚀绝缘介质层形成孔开口;
在正面通过金属溅射或蒸金形成正面金属区;
在背面通过金属溅射或蒸金形成背面金属区。
10.一种基于权利要求1-8任一所述的超结FRD结构的制作方法,其特征在于,包括步骤:
设置N-基区基底;
在所述N-基区基底上挖掘若干深槽,并在深槽内填充P型Si材料形成P型区;
在所述P型区的侧方通过掩膜、涂胶、光刻、离子注入、热扩散形成P+区;
在正面沉积绝缘介质层,并通过光刻、刻蚀绝缘介质层形成孔开口;
在正面通过金属溅射或蒸金形成正面金属区;
在背面通过离子注入、热扩散形成N+基区;
在背面通过金属溅射或蒸金形成背面金属区。
CN202210192035.4A 2022-02-28 2022-02-28 超结frd结构及其制作方法 Pending CN114464669A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115000016A (zh) * 2022-08-08 2022-09-02 泰科天润半导体科技(北京)有限公司 一种提高电流能力的碳化硅mosfet的制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115000016A (zh) * 2022-08-08 2022-09-02 泰科天润半导体科技(北京)有限公司 一种提高电流能力的碳化硅mosfet的制造方法
CN115000016B (zh) * 2022-08-08 2022-11-04 泰科天润半导体科技(北京)有限公司 一种提高电流能力的碳化硅mosfet的制造方法

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