CN103681811A - 一种非完全发射区的绝缘栅双极晶体管及其制备方法 - Google Patents
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
本发明公开了一种非完全发射区的绝缘栅双极晶体管,本发明的绝缘栅双极晶体管将器件背面部分区域设置为P+发射区,通过器件导通时电流自动调节P+发射区的开启导通,调节背P+发射区向N型基区注入空穴的效率,提高器件的高频特性应用范围。本发明还提供了一种非完全发射区的绝缘栅双极晶体管的制备方法。
Description
技术领域
本发明涉及到一种非完全发射区的绝缘栅双极晶体管,本发明还涉及一种非完全发射区的绝缘栅双极晶体管的制备方法。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor,简称IGBT)是一种集金属氧化物半导体场效应管(MOSFET)的栅电极电压控制特性和双极晶体管(BJT)的低导通电阻特性于一身的半导体功率器件,具有电压控制、输入阻抗大、驱动功率小、导通电阻小、开关损耗低及工作频率高等特性,是比较理想的半导体功率开关器件,有着广阔的发展和应用前景。
一般说来,从IGBT的正面结构区分,可以把IGBT分为平面型和沟槽栅型两种结构;从IGBT击穿特性区分,可以分为穿通型和非穿通型两种结构,穿通型在器件背面P+表面具有N+缓冲层,其通态压降比非穿通型要小,同时穿通型器件也增加了器件的制造难度。
发明内容
本发明提供一种非完全发射区的绝缘栅双极晶体管及其制备方法。
一种非完全发射区的绝缘栅双极晶体管,其特征在于:包括:N型基区,由N+缓冲层和N-基区叠加组成;P型基区、N+集电区、栅氧化层和栅极介质,位于N型基区上方;背P+发射区,位于N型基区的N+缓冲层下方部分区域,同时器件背面N+缓冲层表面为欧姆接触区或肖特基势垒结,其中器件背面的背P+发射区的最大宽度小于等于10um,器件背面的N+缓冲层的最大宽度小于等于10um。
一种绝缘栅双极晶体管的制备方法,其特征在于:包括如下步骤:对N型片进行双面N型杂质扩散;通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层:在上表面形成P型基区、N+集电区、栅氧化层和栅极介质;在下表面通过掩膜注入P型杂质,然后退火形成背P+发射区。
传统绝缘栅双极晶体管的背P+发射区完全覆盖器件背面,本发明的绝缘栅双极晶体管将器件背面部分区域设置为P+发射区,通过器件导通时电流自动调节P+发射区的开启导通,调节背P+发射区向N型基区注入空穴的效率,提高器件高频特性的应用范围。
附图说明
图1为本发明的一种非完全发射区的绝缘栅双极晶体管剖面示意图;
图2为本发明的第二种非完全发射区的绝缘栅双极晶体管剖面示意图。
其中,1、背P+发射区;2、N+缓冲层;3、N-基区;4、P型基区;5、N+集电区;6、栅氧化层;7、栅极介质;8、肖特基势垒结;9、欧姆接触区。
具体实施方式
实施例1
图1为本发明的一种非完全发射区的绝缘栅双极晶体管的剖面图,下面结合图1详细说明本发明的半导体装置。
一种绝缘栅双极晶体管,包括:N+缓冲层2,为N传导类型的半导体硅材料,磷原子掺杂浓度为5E13cm-3~1E16cm-3,厚度为30um;背P+发射区1,为P传导类型半导体硅材料,均匀分布N+缓冲层2背面,宽度和间距为5um,深度为5um,硼原子表面掺杂浓度为5E18cm-3;N-基区3,位于N+缓冲层2之上,为N传导类型的半导体硅材料,厚度为200um,磷原子掺杂浓度为5E13cm-3;P型基区4,位于N-基区3之上,为硼原子重掺杂的半导体硅材料,厚度为5um;N+集电区5,位于P型基区4之上,为磷原子重掺杂的半导体硅材料,厚度为2um;栅氧化层6,为硅材料的氧化物,位于器件表面;栅极介质7,位于栅氧化层6表面,为重掺杂的多晶半导体硅材料;肖特基势垒结8,位于器件N+缓冲层2表面,为金属与半导体材料形成的肖特基势垒结。
本实施例的工艺制造流程如下:
第一步,对N型硅片进行双面磷杂质扩散;
第二步,通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层,形成N+缓冲层2和N-基区3:
第三步,在上表面形成P型基区4、N+集电区5、栅氧化层6和栅极介质7;
第四步,在下表面光刻腐蚀形成胶掩膜,注入硼杂质退火形成背P+发射区1,背面淀积金属烧结形成肖特基势垒结8,如图1所示。
然后在此基础上,淀积金属铝,然后光刻腐蚀进行反刻铝,为器件引出集电极和栅电极,通过背面金属化工艺为器件引出发射极。
实施例2
图2为本发明的第二种非完全发射区的绝缘栅双极晶体管的剖面图,下面结合图2详细说明本发明的半导体装置。
一种绝缘栅双极晶体管,包括:N+缓冲层2,为N传导类型的半导体硅材料,磷原子掺杂浓度为5E13cm-3~1E17cm-3,厚度为30um;背P+发射区1,为P传导类型半导体硅材料,均匀分布N+缓冲层2背面,宽度和间距为5um,厚度为5um,硼原子表面掺杂浓度为5E18cm-3;N-基区3,位于N+缓冲层2之上,为N传导类型的半导体硅材料,厚度为200um,磷原子掺杂浓度为5E13cm-3;P型基区4,位于N-基区3之上,为硼原子重掺杂的半导体硅材料,厚度为5um;N+集电区5,位于P型基区4之上,为磷原子重掺杂的半导体硅材料,厚度为2um;栅氧化层6,为硅材料的氧化物,位于器件沟槽内;栅极介质7,位于沟槽内栅氧化层6表面,为重掺杂的多晶半导体硅材料。
本实施例的工艺制造流程如下:
第一步,对N型硅片进行双面磷杂质扩散;
第二步,通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层,形成N+缓冲层2和N-基区3:
第三步,在上表面形成P型基区4、N+集电区5、沟槽结构栅氧化层6和沟槽结构栅极介质7;
第四步,在下表面光刻腐蚀形成胶掩膜,注入硼杂质退火形成背P+发射区1,如图2所示。
然后在此基础上,淀积金属铝,然后光刻腐蚀进行反刻铝,为器件引出集电极和栅电极,通过背面金属化工艺为器件引出发射极。
通过上述实例阐述了本发明,同时也可以采用其它实例实现本发明,本发明不局限于上述具体实例,因此本发明由所附权利要求范围限定。
Claims (10)
1.一种非完全发射区的绝缘栅双极晶体管,其特征在于:包括:
N型基区,由N+缓冲层和N-基区叠加组成;
P型基区、N+集电区、栅氧化层和栅极介质,位于N型基区上方;
背P+发射区,位于N型基区下方部分区域,同时器件背面N+缓冲层表面为欧姆接触区或肖特基势垒结。
2.如权利要求1所述的绝缘栅双极晶体管,其特征在于:所述的背P+发射区均匀分布于N型基区的N+缓冲层下方表面内,器件背面的背P+发射区的最大宽度小于等于10um,器件背面表面的N+缓冲层的最大宽度小于等于10um。
3.如权利要求1所述的绝缘栅双极晶体管,其特征在于:所述的背P+发射区表面的掺杂浓度大于等于1E17cm-3。
4.如权利要求1所述的绝缘栅双极晶体管,其特征在于:所述的N+缓冲层的厚度5um~30um。
5.如权利要求1所述的绝缘栅双极晶体管,其特征在于:所述的N+缓冲层的掺杂浓度1E14cm-3~1E17cm-3。
6.如权利要求1所述的绝缘栅双极晶体管,其特征在于:所述的N+缓冲层的掺杂浓度从下向上逐渐降低。
7.如权利要求1所述的绝缘栅双极晶体管,其特征在于:所述的N-基区的掺杂浓度为1E13cm-3~1E17cm-3。
8.如权利要求1所述的绝缘栅双极晶体管,其特征在于:所述的栅氧化层和栅极介质可以位于器件表面,为平面结构。
9.如权利要求1所述的绝缘栅双极晶体管,其特征在于:所述的栅氧化层和栅极介质可以位于器件沟槽内,为沟槽结构。
10.如权利要求1所述的一种绝缘栅双极晶体管的制备方法,其特征在于:包括如下步骤:
1)对N型片进行双面N型杂质扩散;
2)通过减薄抛光去除上表面N型杂质扩散层和去除下表面部分N型杂质扩散层:
3)在上表面形成P型基区、N+集电区、栅氧化层和栅极介质;
4)在下表面通过掩膜注入P型杂质,然后退火形成背P+发射区。
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