CN114242779A - 一种带有沟槽的碳化硅积累态mosfet - Google Patents

一种带有沟槽的碳化硅积累态mosfet Download PDF

Info

Publication number
CN114242779A
CN114242779A CN202210168948.2A CN202210168948A CN114242779A CN 114242779 A CN114242779 A CN 114242779A CN 202210168948 A CN202210168948 A CN 202210168948A CN 114242779 A CN114242779 A CN 114242779A
Authority
CN
China
Prior art keywords
silicon carbide
layer
accumulation
source
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210168948.2A
Other languages
English (en)
Other versions
CN114242779B (zh
Inventor
王中健
罗杰馨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Gongcheng Semiconductor Co ltd
Original Assignee
Chengdu Gongcheng Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Gongcheng Semiconductor Co ltd filed Critical Chengdu Gongcheng Semiconductor Co ltd
Priority to CN202210168948.2A priority Critical patent/CN114242779B/zh
Publication of CN114242779A publication Critical patent/CN114242779A/zh
Application granted granted Critical
Publication of CN114242779B publication Critical patent/CN114242779B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种带有沟槽的碳化硅积累态MOSFET，包括：碳化硅衬底和生长在碳化硅衬底上的碳化硅外延层，碳化硅外延层上刻蚀有沟槽，沟槽表面生长有氧化层，氧化层上设有栅极多晶硅电极，碳化硅外延层上设有源极注入区和与其连接的积累层，解决了现有技术存在的沟道迁移率低的问题，其应用时增加沟道迁移率，导通电阻显著降低。

Description

一种带有沟槽的碳化硅积累态MOSFET
技术领域
本发明涉及半导体技术领域，具体涉及一种带有沟槽的碳化硅积累态MOSFET。
背景技术
基于碳化硅的宽带隙半导体因其低导通损耗，优异的耐高温性和高导热特性，越来越受市场的欢迎。另外，碳化硅还拥有高临界场，高体迁移率，高饱和速度等独特的电学性能。特别是高临界场特性，使碳化硅功率器件与相同电压应用条件下的常规硅器件相比，有更高的掺杂浓度和更薄的漂移层厚度，从而实现更低的导通电阻。碳化硅MOSFET有较低的开关损耗和较高的工作频率，非常贴合电力电子的应用需求。
现有平面栅碳化硅MOSFET结构单元间距较大，成本高。平面栅碳化硅MOSFET结构的SiO2（栅氧化物）/ SiC界面处的界面的沟道迁移率较低，相应的导通电阻较大。常规的反型MOSFET沟道迁移率没有积累态高，沟道电阻没有积累态MOSFET低，导通电阻仍有降低的空间。
发明内容
本发明提供了一种带有沟槽的碳化硅积累态MOSFET，解决了现有技术存在的沟道迁移率低问题，其应用时可提高沟道迁移率，导通电阻显著降低。
为了解决该技术问题，本发明提供了如下技术方案：
一种带有沟槽的碳化硅积累态MOSFET，包括：碳化硅衬底和生长在碳化硅衬底上的碳化硅外延层， 碳化硅外延层上刻蚀有沟槽，沟槽表面生长有氧化层，所述沟槽由底部至开口依次设有栅极保护区和栅极多晶硅电极，同时碳化硅外延层上设有源级注入区、耐压注入区和阻断注入层，在所述源极注入区和氧化层之间设有积累层。
所述碳化硅衬底的掺杂类型为第一导电类型，碳化硅外延层的掺杂类型为第一导电类型，所述源极注入区的掺杂类型为第一导电类型，耐压注入区的掺杂类型为第二导电类型，阻断注入层的掺杂类型为第二导电类型，栅极保护区的掺杂类型为第二导电类型，积累层的掺杂类型为第一导电类型。
本方案在碳化硅外延层上刻蚀有沟槽，在沟槽表面生长有氧化层，氧化层上设有栅极多晶硅电极，形成MOSFET的栅极区，控制器件的开通与关断。在栅极多晶硅电极上施加正压即可实现器件的开启。电子从源极注入区开始进入器件，在积累层附近形成电子沟道，经过碳化硅外延层、碳化硅衬底形成导通。
其中，积累层的长度、厚度以及掺杂浓度需要精确控制，以使此区被完全耗尽，保证器件为常闭型器件。积累层的存在，可降低沟道电阻，从而大幅降低导通电阻。另外，积累层还可以使得器件在开通时，电子沟道远离栅氧表面，避免了因栅氧质量水平引起的高导通电阻以及可靠性问题。阻断注入层用于保持MOSFET为常闭型器件，阻断注入层与碳化硅外延层形成PiN结构增加反向耐压。耐压注入区用于增加反向耐压。
所述第一导电类型可以为N，也可以为P。
优选的，所述积累层沿所述氧化层周向间隔设置。
为保证器件为常闭型器件，使积累层沿所述氧化层周向间隔设置，积累层的在氧化层周向的分布面积小于50%，使此区被完全耗尽；在此方案下积累层的厚度可稍作提升，减轻工艺制作的难度，同时可以在减少沟道电阻的同时使此区被完全耗尽，在栅极未开启条件下保持沟道关闭。
在栅极沟槽下设有栅极保护区，防止栅压过高时器件穿通。
优选的，源极注入区上设有源极金属电极。
源极注入区与源极金属电极形成源极区，电子从源极金属电极进入，从源极注入区开始进入器件。
优选的，源极金属电极和栅极多晶硅电极之间设有绝缘层。
栅极多晶硅电极和源极金属电极间设有绝缘层，以实现电学隔离。
优选的，所述碳化硅衬底背面覆盖有漏极金属电极。
本方案在碳化硅衬底背面覆盖有漏极金属电极，形成MOSFET的漏极区；
所述第二导电类型与第一导电类型不同；当第一导电类型为N，第二导电类型为P；当第一导电类型为P时，第二导电类型为N。
优选的，所述碳化硅衬底的掺杂浓度与类型为N+，碳化硅外延层掺杂浓度与类型为N-，所述源极注入区掺杂浓度与类型为N+，积累层的掺杂浓度与类型为N-，栅极保护区的掺杂浓度与类型为P+，阻断注入层掺杂浓度与类型为P，耐压注入区的掺杂浓度与类型为P+。
本发明和现有技术相比，具有以下优点：
本发明的带有沟槽的碳化硅积累态MOSFET在保持较高反向耐压的特性下，还可同时降低导通电阻。
本发明栅氧表面沟道迁移率比常规平面栅碳化硅MOSFET结构中的沟道迁移率大2-3倍。另外，与目前在商业生产市场上占主导地位的平面栅MOSFET结构相比，本发明的沟槽栅MOSFET设计可实现更小的单元间距。结合减小间距和增加沟道迁移率的优势，沟槽栅MOSFET设计与传统的平面栅设计相比，导通电阻显著降低。
同时，积累态MOSFET与常规反型MOSFET相比有更高的沟道迁移率，使导通电阻进一步降低。积累层的存在，可降低沟道电阻，从而大幅降低导通电阻。另外，积累层还可以使得器件在开通时，电子沟道远离栅氧表面，避免了因栅氧质量水平带来的高导通电阻以及可靠性问题。同时积累层的分布面积小于50%，保证了器件的阈值电压以及反向耐压能力。
附图说明
此处所说明的附图用来提供对本发明实施例的进一步理解，构成本申请的一部分，并不构成对本发明实施例的限定。在附图中：
图1为本发明带有沟槽的碳化硅积累态MOSFET的结构示意图；
图2为图1中A-A'截面的结构示意图；
图3为图1中B-B'截面的结构示意图；
附图中标记及对应的结构名称：
101、碳化硅衬底；102、碳化硅外延层；103、阻断注入层；104、源极注入区；105、积累层；106、栅极保护区；107、氧化层；108、栅极多晶硅电极；109、绝缘层；110、源极金属电极；111、漏极金属电极；112、耐压注入区。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，下面结合实施例，对本发明作进一步的详细说明，本发明的示意性实施方式及其说明仅用于解释本发明，并不作为对本发明的限定。
实施例1
如图1所示，带有沟槽的碳化硅积累态MOSFET，以第一导电类型为N，第二导电类型为P为例，包括碳化硅衬底101，其中该衬底掺杂浓度与类型为N+。在碳化硅衬底101上生长有碳化硅外延层102，其中该外延层掺杂浓度与类型为N-。在碳化硅衬底101背面覆盖有漏极金属电极111，形成MOSFET的漏极区。
碳化硅外延层102上刻蚀有沟槽，沟槽表面生长有氧化层107，氧化层107上设有栅极多晶硅电极108，形成MOSFET的栅极区，控制器件的开通与关断，在栅极多晶硅电极108上施加正压即可实现器件的开启。所述沟槽底部设有栅极保护区106，栅极保护区106可防止栅压过高时器件穿通，其掺杂浓度与类型为P+。碳化硅外延层102上设有源极注入区104和与其连接的积累层105。积累层105的掺杂浓度与类型为N-，源极注入区104的掺杂浓度与类型为N+。源极注入区104覆盖有源极金属电极110，源极金属电极110和栅极多晶硅电极108之间设有用于实现电学隔离的绝缘层109。电子从源极金属电极110进入，经源极注入区104进入器件，在积累层105附近形成电子沟道，经过碳化硅外延层102、碳化硅衬底101以及漏极金属电极111形成导通。积累层105的厚度需设置为50nm-200nm，掺杂浓度设置为1×1013cm-3-1×1015 cm-3，以使此区能够被完全耗尽，保证器件为常闭型器件。积累层105的存在，可降低沟道电阻，从而大幅降低导通电阻。另外，积累层105还可以使得器件在开通时，电子沟道远离栅氧表面，避免了因栅氧质量水平带来的高导通电阻以及可靠性问题。
碳化硅外延层102与源极注入区104之间还设有与积累层105接触的阻断注入层103，其掺杂浓度与类型为P，阻断注入层103用于保持MOSFET为常闭型器件，阻断注入层103与碳化硅外延层102形成PiN结构增加反向耐压。源极金属电极110和阻断注入层103之间设有与源极注入区104接触的耐压注入区112，耐压注入区112的掺杂浓度与类型为P+，耐压注入区112用于增加反向耐压。
本实施例为常闭型MOSFET，工作时在栅极多晶硅电极108上施加正压即可实现器件的开启。电子从源极金属电极110进入，经源极注入区104进入器件，在积累层105附近形成电子沟道，经过碳化硅外延层102、碳化硅衬底101以及漏极金属电极111形成导通。
实施例2
如图2-3所示，本实施例在实施例1的基础上，进一步限定，所述积累层105沿所述氧化层107周向间隔设置；为保证器件为常闭型器件的前提下同时提高阈值电压，设置积累层105沿所述氧化层107周向间隔分布。优选地，在氧化层107周向的分布面积小于50%。在此方案下积累层105的厚度可稍作提升，减轻工艺制作的难度，同时可以在减轻沟道电阻的同时使此区被完全耗尽，在栅极未开启条件下保持沟道关闭。
实施例3
本实施例和实施例1的区别在于，第一导电类型为P，第二导电类型为N，即所述碳化硅衬底101、碳化硅外延层102、源极注入区104、积累层105的导电类型为P型；阻断注入层103和耐压注入区112的导电类型为N型；作为优选的方式，所述碳化硅衬底101的掺杂浓度与类型为P+，所述碳化硅外延层102掺杂浓度与类型为P-，所述源极注入区104掺杂浓度与类型为P+，所述积累层105的掺杂浓度与类型为P-，栅极保护区106的掺杂浓度与类型为N+，阻断注入层103掺杂浓度与类型为N，耐压注入区112的掺杂浓度与类型为N+。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (8)

1.一种带有沟槽的碳化硅积累态MOSFET，包括：碳化硅衬底（101）和生长在碳化硅衬底（101）上的碳化硅外延层（102），其特征在于，
碳化硅外延层（102）上刻蚀有沟槽，沟槽表面生长有氧化层（107），氧化层（107）上设有栅极多晶硅电极（108），碳化硅外延层（102）上设有源极注入区（104）和连接碳化硅外延层（102）与源极注入区（104）的积累层（105）。
2.根据权利要求1所述的一种带有沟槽的碳化硅积累态MOSFET，其特征在于，所述积累层（105）沿所述氧化层（107）周向间隔设置。
3.根据权利要求1所述的一种带有沟槽的碳化硅积累态MOSFET，其特征在于，所述沟槽底部设有栅极保护区（106）。
4.根据权利要求1所述的一种带有沟槽的碳化硅积累态MOSFET，其特征在于，源极注入区（104）覆盖有源极金属电极（110）。
5.根据权利要求4所述的一种带有沟槽的碳化硅积累态MOSFET，其特征在于，源极金属电极（110）和栅极多晶硅电极（108）之间设有绝缘层（109）。
6.根据权利要求4所述的一种带有沟槽的碳化硅积累态MOSFET，其特征在于，碳化硅外延层（102）与源极注入区（104）之间还设有阻断注入层（103）。
7.根据权利要求6所述的一种带有沟槽的碳化硅积累态MOSFET，其特征在于，源极金属电极（110）和阻断注入层（103）之间设有位于源极注入区（104）外侧的耐压注入区（112）。
8.根据权利要求1所述的一种带有沟槽的碳化硅积累态MOSFET，其特征在于，所述碳化硅衬底（101）背面覆盖有漏极金属电极（111）。
CN202210168948.2A 2022-02-24 2022-02-24 一种带有沟槽的碳化硅积累态mosfet Active CN114242779B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210168948.2A CN114242779B (zh) 2022-02-24 2022-02-24 一种带有沟槽的碳化硅积累态mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210168948.2A CN114242779B (zh) 2022-02-24 2022-02-24 一种带有沟槽的碳化硅积累态mosfet

Publications (2)

Publication Number Publication Date
CN114242779A true CN114242779A (zh) 2022-03-25
CN114242779B CN114242779B (zh) 2022-05-10

Family

ID=80747834

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210168948.2A Active CN114242779B (zh) 2022-02-24 2022-02-24 一种带有沟槽的碳化硅积累态mosfet

Country Status (1)

Country Link
CN (1) CN114242779B (zh)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069042A (ja) * 2001-08-29 2003-03-07 Denso Corp 炭化珪素半導体装置及びその製造方法
US20080079065A1 (en) * 2006-09-29 2008-04-03 Qingchun Zhang Novel U-Shape Metal-Oxide-Semiconductor (UMOS) Gate Structure For High Power MOS-Based Semiconductor Devices
US20090114969A1 (en) * 2007-11-06 2009-05-07 Denso Corporation Silicon carbide semiconductor device and related manufacturing method
US20100163935A1 (en) * 2008-12-22 2010-07-01 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
CN105047721A (zh) * 2015-08-26 2015-11-11 国网智能电网研究院 一种碳化硅沟槽栅功率MOSFETs器件及其制备方法
CN106158973A (zh) * 2016-07-06 2016-11-23 电子科技大学 一种积累型dmos
CN107887431A (zh) * 2016-09-30 2018-04-06 英飞凌科技股份有限公司 功率半导体装置
CN109904155A (zh) * 2019-01-31 2019-06-18 电子科技大学 一种集成高速反向续流二极管的碳化硅mosfet器件
CN110326109A (zh) * 2016-06-29 2019-10-11 Abb瑞士股份有限公司 短沟道沟槽功率mosfet
JP2019195007A (ja) * 2018-05-01 2019-11-07 良孝 菅原 半導体装置およびその製造方法
CN112186027A (zh) * 2020-08-28 2021-01-05 派恩杰半导体（杭州）有限公司 一种带有栅极沟槽结构的碳化硅mosfet
CN112382655A (zh) * 2020-11-12 2021-02-19 中国科学院半导体研究所 一种宽禁带功率半导体器件及制备方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069042A (ja) * 2001-08-29 2003-03-07 Denso Corp 炭化珪素半導体装置及びその製造方法
US20080079065A1 (en) * 2006-09-29 2008-04-03 Qingchun Zhang Novel U-Shape Metal-Oxide-Semiconductor (UMOS) Gate Structure For High Power MOS-Based Semiconductor Devices
US20090114969A1 (en) * 2007-11-06 2009-05-07 Denso Corporation Silicon carbide semiconductor device and related manufacturing method
US20100163935A1 (en) * 2008-12-22 2010-07-01 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
CN105047721A (zh) * 2015-08-26 2015-11-11 国网智能电网研究院 一种碳化硅沟槽栅功率MOSFETs器件及其制备方法
CN110326109A (zh) * 2016-06-29 2019-10-11 Abb瑞士股份有限公司 短沟道沟槽功率mosfet
CN106158973A (zh) * 2016-07-06 2016-11-23 电子科技大学 一种积累型dmos
CN107887431A (zh) * 2016-09-30 2018-04-06 英飞凌科技股份有限公司 功率半导体装置
JP2019195007A (ja) * 2018-05-01 2019-11-07 良孝 菅原 半導体装置およびその製造方法
CN109904155A (zh) * 2019-01-31 2019-06-18 电子科技大学 一种集成高速反向续流二极管的碳化硅mosfet器件
CN112186027A (zh) * 2020-08-28 2021-01-05 派恩杰半导体（杭州）有限公司 一种带有栅极沟槽结构的碳化硅mosfet
CN112382655A (zh) * 2020-11-12 2021-02-19 中国科学院半导体研究所 一种宽禁带功率半导体器件及制备方法

Also Published As

Publication number Publication date
CN114242779B (zh) 2022-05-10

Similar Documents

Publication Publication Date Title
CN110148629B (zh) 一种沟槽型碳化硅mosfet器件及其制备方法
CN109920854B (zh) Mosfet器件
US20070007537A1 (en) Semiconductor device
JP2012059841A (ja) 半導体装置
CN110277439B (zh) 一种碳化硅倒t形掩蔽层结构的mosfet器件及其制备方法
KR100762545B1 (ko) Ｌｍｏｓｆｅｔ 및 그 제조 방법
CN114843332B (zh) 低功耗高可靠性半包沟槽栅mosfet器件及制备方法
CN217086575U (zh) 一种碳化硅沟槽式mosfet
CN116110796B (zh) 集成sbd的碳化硅sgt-mosfet及其制备方法
CN116230774B (zh) 一种非对称碳化硅槽栅mosfet及其制造方法
CN112186027A (zh) 一种带有栅极沟槽结构的碳化硅mosfet
CN113990919A (zh) 碳化硅半导体结构、器件及制备方法
CN110993691A (zh) 双沟道横向超结双扩散金属氧化物宽带隙半导体场效应管及其制作方法
CN110190128B (zh) 一种碳化硅双侧深l形基区结构的mosfet器件及其制备方法
CN115148826A (zh) 一种深沟槽碳化硅jfet结构的制作方法
CN113594255A (zh) 沟槽型mosfet器件及其制备方法
CN113972261A (zh) 碳化硅半导体器件及制备方法
CN116525683B (zh) 一种深阱型SiC Mosfet器件及制备方法
CN115172466B (zh) 一种超结vdmos新结构及其制备方法
CN116613210A (zh) 一种高耐压碳化硅umosfet器件及其制备方法
CN114242779B (zh) 一种带有沟槽的碳化硅积累态mosfet
KR20010102278A (ko) 게이트 항복을 방지한 실리콘 탄화물 횡형 금속 산화물반도체 전계 효과 트랜지스터
CN213366599U (zh) 带有栅极沟槽结构的碳化硅mosfet
CN209804661U (zh) 一种碳化硅双侧深l形基区结构的mosfet器件
CN112018162B (zh) 一种4H-SiC侧栅集成SBD MOSFET器件及其制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant