CN114093861A - 三维扇出型集成封装结构及其封装方法和无线耳机 - Google Patents

三维扇出型集成封装结构及其封装方法和无线耳机 Download PDF

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CN114093861A
CN114093861A CN202111373008.9A CN202111373008A CN114093861A CN 114093861 A CN114093861 A CN 114093861A CN 202111373008 A CN202111373008 A CN 202111373008A CN 114093861 A CN114093861 A CN 114093861A
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layer
semiconductor chip
packaging
metal
chip
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CN114093861B (zh
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陈彦亨
林正忠
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to US17/989,224 priority patent/US20230163114A1/en
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Abstract

本发明提供一种三维扇出型集成封装结构及其封装方法和无线耳机，所述三维扇出型集成封装结构包括第一重新布线层、第二重新布线层、金属连接柱、第一半导体芯片、第二半导体芯片、第一填充层、第一封装层、功能芯片、第二填充层、第二封装层及凸块，该结构通过将两半导体芯片进行堆叠设置，有效减小了封装面积，可实现高密度高集成度的器件封装，同时使得最小线宽线距可降至1.5μm/1.5μm。而且本发明的三维扇出型集成封装结构可以同时整合GPU/PMU/DDR/毫米波天线/电容/电感/电晶体/闪存/滤波器等各种功能芯片和元器件，实现系统级封装，不仅能够降低成本，而且通过采用物理隔离的方式减少器件干扰，提高了封装结构的效能。

Description

三维扇出型集成封装结构及其封装方法和无线耳机
技术领域
本发明涉及半导体封装技术领域，特别是涉及一种三维扇出型集成封装结构及其封装方法和无线耳机。
背景技术
随着电子设备朝着小型化及多功能化发展，需要集成封装在一起的芯片品种和数量也日益增加，因此对于封装结构与封装工艺的要求逐步提高。当前半导体封装广泛采用扇出型封装工艺，并沿高度方向通过堆叠的方式将复杂多样的芯片与无源被动器件进行集成封装，以构成一个体积小、功耗低且功能强大的系统，这也成为半导体先进封装领域的一大挑战。
随着电子硬件不断演进，过去产品的成本及性能优势面临发展瓶颈，先进的半导体封装技术不仅可以增加功能、提升产品价值，还能有效降低成本，于是芯片级封装(CSP)、晶圆级封装(WLP)、系统级封装(SiP)等一系列先进封装技术应运而生。与其他封装类型相比，系统级封装最大的特点是能够满足复杂的异质集成需求，将各类性能迥异的有源器件与可选无源器件整合为单个标准封装件，以形成一个系统或者子系统，苹果从近期发布的Airpods pro开始导入系统级封装，虽投入巨大，但是对耳机产品性能的提升帮助很大，而且节省的空间可以做更多的增量特性，培养对消费者的更多黏性，比如主动降噪(ANC)功能的引入。而以Apple Watch为例，仅在边长为25～30mm的正方形范围内，集成了约1000颗左右的有源器件及无源器件，所以系统级封装技术将是未来一大趋势。然而，当前系统级封装技术还存在封装面积大、整合性低、集成度小的缺陷，而无法满足超高密度的元器件封装需求。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种三维扇出型集成封装结构及其封装方法和无线耳机，用于解决现有技术中的扇出型封装结构的封装面积大、整合性低、集成度小的问题。
为实现上述目的及其他相关目的，本发明提供一种三维扇出型集成封装结构，所述三维扇出型集成封装结构包括：
平行设置的第一重新布线层及第二重新布线层；
金属连接柱，位于所述第一重新布线层与所述第二重新布线层之间，且两端分别与所述第一重新布线层与所述第二重新布线层电连接；
第一半导体芯片及堆叠在所述第一半导体芯片上的第二半导体芯片，均位于所述第一重新布线层与所述第二重新布线层之间，所述第一半导体芯片与所述第二半导体芯片电连接，其中所述第二半导体芯片还与所述第一重新布线层电连接；
第一填充层，填充在所述第一半导体芯片和所述第二半导体芯片之间；
第一封装层，位于所述第一重新布线层和所述第二重新布线层之间，且包覆所述金属连接柱、所述第一半导体芯片及所述第二半导体芯片；
功能芯片，位于所述第二重新布线层远离所述第一封装层的表面上，并与所述第二重新布线层电连接；
第二填充层，填充在所述功能芯片与所述第二重新布线层之间；
第二封装层，位于所述第二重新布线层远离所述第一封装层的表面上，并包覆所述功能芯片；
凸块，位于所述第一重新布线层远离所述第一封装层的表面上，并与所述第一重新布线层电连接。
可选地，所述第一半导体芯片包括射频芯片，所述第二半导体芯片包括单片机，所述功能芯片包括存储芯片。
可选地，所述第二半导体芯片包括若干第一焊盘，部分所述第一焊盘通过位于所述第一封装层中的金属柱与所述第一重新布线层电连接，另一部分所述第一焊盘通过位于所述第一填充层中的金属导电层与所述第一半导体芯片电连接；所述功能芯片包括若干第二焊盘，所述第二焊盘上形成有焊料连接结构，所述焊料连接结构与所述第二重新布线层连接。
进一步地，所述焊料连接结构包括焊球和导电柱，所述导电柱的一端与所述第二焊盘连接，另一端与所述焊球连接；所述焊球再与所述第二重新布线层连接。
可选地，所述第二半导体芯片与所述第二重新布线层之间设有粘接层，所述粘接层用于固定所述第二半导体芯片。
可选地，所述第一重新布线层包括第一介质层和位于所述第一介质层中的第一金属线层，所述第一介质层和所述第一金属线层交替层叠；所述第二重新布线层包括第二介质层和位于所述第二介质层中的第二金属线层，所述第二介质层和所述第二金属线层交替层叠。
进一步地，所述第一介质层的材料包括环氧树脂、氧化硅、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第二介质层的材料包括环氧树脂、氧化硅、聚酰亚胺及硅胶中的一种或两种以上的组合。
可选地，所述第一封装层的材料包括环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第二封装层的材料包括环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第一填充层的材料包括环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第二填充层的材料包括环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合。
可选地，所述凸块包括铜凸块、锡凸块、铝凸块及镍凸块中的一种或两种以上的组合。
可选地，所述三维扇出型集成封装结构还包括被动元件，所述被动元件包括电容、电阻和电感，所述被动元件位于所述第二重新布线层远离所述第一封装层的表面上，并与所述第二重新布线层电连接。
本发明还提供一种无线耳机，所述无线耳机包括如上所述三维扇出型集成封装结构。
本发明还提供一种三维扇出型集成封装结构的制备方法，所述制备方法包括以下步骤：
提供支撑基底，于所述支撑基底上形成分离层；
于所述分离层上形成第二重新布线层，所述第二重新布线层包括第二介质层和位于所述第二介质层中的第二金属线层；
于所述第二重新布线层上形成金属连接柱，将所述金属连接柱与所述第二金属线层电连接；
提供第二半导体芯片，将所述第二半导体芯片与所述第二重新布线层粘合；
提供第一半导体芯片，将所述第一半导体芯片堆叠在所述第二半导体芯片上并与所述第二半导体芯片电连接；
于所述第一半导体芯片与所述第二半导体芯片之间形成第一填充层；
于所述第二重新布线层上形成第一封装层，所述第一封装层包覆所述金属连接柱、所述第一半导体芯片及所述第二半导体芯片；
于所述第一封装层上形成第一重新布线层，所述第一重新布线层包括第一介质层和位于所述第一介质层中的第一金属线层，将所述第一金属线层与所述第二半导体芯片及所述金属连接柱电连接；
于所述第一重新布线层远离所述第一封装层的表面上形成凸块，将所述凸块与所述第一金属线层电连接；
提供承载体，将前述步骤得到的封装结构倒放于所述承载体上；
基于所述分离层剥离所述支撑基底，以暴露出所述第二重新布线层远离所述第一封装层的表面；
提供功能芯片，将所述功能芯片与所述第二金属线层电连接；
于所述功能芯片与所述第二重新布线层之间形成第二填充层；
于所述第二重新布线层远离所述第一封装层的表面上形成第二封装层，所述第二封装层包覆所述功能芯片；
去除所述承载体。
可选地，所述支撑基底选自玻璃基底、金属基底、半导体基底、聚合物基底及陶瓷基底中的一种；所述承载体选自玻璃基底、金属基底、半导体基底、聚合物基底及陶瓷基底中的一种；所述分离层选自胶带层或聚合物层，通过旋涂工艺将所述分离层涂覆于所述支撑基底表面，然后使用激光固化或紫外固化或热固化工艺使所述分离层固化成型。
可选地，形成所述第一重新布线层及所述第二重新布线层的步骤包括：
采用化学气相沉积工艺或物理气相沉积工艺形成第一沉积介质层及第二沉积介质层，对所述第一沉积介质层进行刻蚀形成图形化的所述第一介质层，对所述第二沉积介质层进行刻蚀形成图形化的所述第二介质层；
采用化学气相沉积工艺、物理气相沉积工艺、蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺于所述第一介质层及所述第二介质层的表面对应形成第一金属层及第二金属层，对所述第一金属层进行刻蚀形成所述第一金属线层，对所述第二金属层进行刻蚀形成所述第二金属线层，将所述第一金属线层及所述第二金属线层通过所述金属连接柱电连接。
如上所述，本发明的三维扇出型集成封装结构及其封装方法和无线耳机，具有以下有益效果：本发明的三维扇出型集成封装结构通过将两半导体芯片进行堆叠设置，有效减小了封装面积，可实现高密度高集成度的器件封装，同时使得最小线宽线距可降至1.5μm/1.5μm，远小于传统基板的20μm/20μm。另外，本发明的三维扇出型集成封装结构可以同时整合GPU/PMU/DDR/毫米波天线/电容/电感/电晶体/闪存/滤波器等各种功能芯片和元器件，实现系统级封装，不仅能够降低成本，而且通过采用物理隔离的方式减少器件干扰，提高了封装结构的效能。
附图说明
图1显示为本发明实施例一中的三维扇出型集成封装结构的结构示意图。
图2显示为本发明实施例二中的三维扇出型集成封装结构的封装方法的流程图。
图3～图18显示为本发明实施例二中的三维扇出型集成封装结构的封装方法中各步骤所呈现的结构示意图。
元件标号说明
10 支撑基底
20 分离层
30 第二重新布线层
31 第二介质层
32 第二金属线层
40 金属连接柱
50 粘接层
60 第二半导体芯片
61 第一焊盘
70 第一半导体芯片
80 金属导电层
90 第一填充层
100 第一封装层
110 第一重新布线层
111 第一介质层
112 第一金属线层
120 金属柱
130 凸块
140 承载体
150 功能芯片
151 第二焊盘
160 焊料连接结构
170 第二填充层
180 第二封装层
S1～S15 步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量、位置关系及比例可在实现本技术方案的前提下随意改变，且其组件布局形态也可能更为复杂。
实施例一
传统的三维扇出型封装结构的两颗半导体芯片平放于封装结构内部，增加了横向面积，最小线宽/线距只能做到20μm/20μm，这已经无法满足当前封装结构集成度越来越高的需求。本申请的发明人经研究而提出了一种改善方案，能够使最小线宽线距降至1.5μm/1.5μm，具体如下所述。
如图1所示，本发明提供一种三维扇出型集成封装结构，所述三维扇出型集成封装结构包括第一重新布线层110、第二重新布线层30、金属连接柱40、第一半导体芯片70、第二半导体芯片60、第一填充层90、第一封装层100、功能芯片150、第二填充层170、第二封装层180及凸块130，其中，所述第一重新布线层110及所述第二重新布线层30平行设置；所述金属连接柱40位于所述第一重新布线层110与所述第二重新布线层30之间，且两端分别与所述第一重新布线层110与所述第二重新布线层30电连接；所述第二半导体芯片60堆叠在所述第一半导体芯片70上，所述第一半导体芯片70及所述第二半导体芯片60均位于所述第一重新布线层110与所述第二重新布线层30之间，所述第一半导体芯片70与所述第二半导体芯片60电连接，其中所述第二半导体芯片60还与所述第一重新布线层110电连接；所述第一填充层90填充在所述第一半导体芯片70和所述第二半导体芯片60之间；所述第一封装层100位于所述第一重新布线层110和所述第二重新布线层30之间，且包覆所述金属连接柱40、所述第一半导体芯片70及所述第二半导体芯片60；所述功能芯片150位于所述第二重新布线层30远离所述第一封装层100的表面上，并与所述第二重新布线层30电连接；所述第二填充层170填充在所述功能芯片150与所述第二重新布线层30之间；所述第二封装层180位于所述第二重新布线层30远离所述第一封装层100的表面上，并包覆所述功能芯片150；所述凸块130位于所述第一重新布线层110远离所述第一封装层100的表面上，并与所述第一重新布线层110电连接。需要说明的是，所述第一重新布线层110包括第一介质层111和位于所述第一介质层111中的第一金属线层112，所述第一金属线层112部分显露于所述第一介质层111的表面，用于电连接；所述第二重新布线层30包括第二介质层31和位于所述第二介质层31中的第二金属线层32，所述第二金属线层32部分显露于所述第二介质层31的表面，用于电连接。
作为示例，所述第一介质层111的材料包括但不限于环氧树脂、氧化硅、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第二介质层31的材料包括但不限于环氧树脂、氧化硅、聚酰亚胺及硅胶中的一种或两种以上的组合。所述第一金属线层112的材料包括但不限于铜、镍、金、银、铝及钛等金属中的一种或两种以上的组合；所述第二金属线层32的材料包括但不限于铜、镍、金、银、铝及钛等金属中的一种或两种以上的组合。
作为示例，在所述第一重新布线层110中，所述第一介质层111和所述第一金属线层112均可以为单层或者多层结构，所述第一介质层111和所述第一金属线层112交替层叠，同时保证不同层的第一金属线层112之间能够相互电连接。所述第二重新布线层30的结构可参照所述第一重新布线层110的结构设置，在此不再赘述。
作为示例，所述金属连接柱40的材料包括但不限于金、银、铜、钛及铝中的一种或两种以上的组合，优选地，所述金属连接柱40的材料为铜。
作为示例，所述第一封装层100的材料包括但不限于环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第二封装层180的材料包括但不限于环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第一填充层90的材料包括但不限于环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第二填充层170的材料包括但不限于环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合。
所述第一填充层90通过填充所述第一半导体芯片70和所述第二半导体芯片60之间的间隙，形成保护层，不仅避免水汽、氧气等的影响，而且提高所述第一半导体芯片70和所述第二半导体芯片60的结合强度。所述第二填充层170填充在所述功能芯片150与所述第二重新布线层30之间，其作用与所述第一填充层90相同，在此不再赘述。
作为示例，所述凸块130包括但不限于铜凸块、锡凸块、铝凸块及镍凸块中的一种或两种以上的组合。
作为示例，所述第一半导体芯片70可以为射频芯片(RF)，所述第二半导体芯片60可以为单片机(MCU)，所述功能芯片150可以为存储芯片，例如DDR(双倍速率同步动态随机存储器)及闪存，也可以采用GPU(图形处理器)、PMU(电源管理单元)、毫米波天线、电晶体及滤波器等各种器件。本发明并不限制所述第一半导体芯片70、所述第二半导体芯片60及所述功能芯片150的形式(裸芯片或封装芯片)、数量及种类，可根据实际需求进行设置。
作为示例，所述第二半导体芯片60包括若干第一焊盘61，部分所述第一焊盘61通过位于所述第一封装层100中的金属柱120与所述第一金属线层112电连接，另一部分所述第一焊盘61通过位于所述第一填充层90中的金属导电层80与所述第一半导体芯片70电连接；所述功能芯片150包括若干第二焊盘151，所述第二焊盘151上形成有焊料连接结构160，所述焊料连接结构160与所述第二金属线层32连接。其中，所述金属柱120及所述金属导电层80的材料包括但不限于金、银、铜、钛及铝中的一种或两种以上的组合。
具体的，所述焊料连接结构160包括焊球和导电柱，所述导电柱的一端与所述第二焊盘151连接，另一端与所述焊球连接；所述焊球再与所述第二金属线层32连接；所述焊料连接结构160也可以只有焊球，所述焊球与所述第二焊盘151及所述第二金属线层32连接。
作为示例，所述第二半导体芯片60与所述第二重新布线层30之间还设有粘接层50，所述粘接层50用于固定所述第二半导体芯片60，防止所述第二半导体芯片60在使用过程中发生移动。所述粘接层50的材料可以选择双面均具有粘性的胶带或者粘合胶，也可以选择其他具有粘合性能的材料。
作为示例，所述三维扇出型集成封装结构还包括被动元件，所述被动元件包括但不限于电容、电阻和电感，所述被动元件位于所述第二重新布线层30远离所述第一封装层100的表面上，并与所述第二金属线层32电连接。
本实施例还提供一种无线耳机，所述无线耳机包括上述三维扇出型集成封装结构。
实施例二
如图2所示，本发明提供一种三维扇出型集成封装结构的制备方法，所述制备方法用于制得上述实施例一的三维扇出型集成封装结构，其中的各部件的封装材料以及所能达到的有益效果已在实施例一中进行了说明，在本实施例中不再赘述。所述制备方法具体包括以下步骤：
如图2-图4所示，首先进行步骤S1，提供支撑基底10，于所述支撑基底10上形成分离层20。
作为示例，如图3所示，所述支撑基底10包括玻璃基底、金属基底、半导体基底、聚合物基底及陶瓷基底中的一种。所述支撑基底10的形状可以为晶圆状、方形面板状或其他任意所需形状，本实施例通过所述支撑基底10防止半导体芯片在后续的制备过程中发生开裂、翘曲、断裂等问题。
另外，如图4所示，所述分离层20选自胶带层或聚合物层，通过旋涂工艺将所述分离层20涂覆于所述支撑基底10表面，然后使用激光固化、紫外固化或热固化工艺使所述分离层20固化成型。
如图2及图5所示，进行步骤S2，于所述分离层20上形成第二重新布线层30，所述第二重新布线层30包括第二介质层31和位于所述第二介质层31中的第二金属线层32。
形成所述第二重新布线层30的具体步骤包括：采用化学气相沉积工艺或物理气相沉积工艺形成第二沉积介质层，对所述第二沉积介质层进行刻蚀形成图形化的所述第二介质层31；
采用化学气相沉积工艺、物理气相沉积工艺、蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺于所述第二介质层31的表面形成第二金属层，对所述第二金属层进行刻蚀形成所述第二金属线层32。
如图2及图6所示，进行步骤S3，于所述第二重新布线层30上形成金属连接柱40，将所述金属连接柱40与所述第二金属线层32电连接。形成所述金属连接柱40的工艺可选择焊线、电镀及化学镀中的一种，也可根据需要进行选择，此处不作限制。
如图2及图7所示，进行步骤S4，提供第二半导体芯片60，将所述第二半导体芯片60与所述第二重新布线层30粘合，具体的，可通过粘接层50实现粘合。
如图2及图8所示，进行步骤S5，提供第一半导体芯片70，将所述第一半导体芯片70堆叠在所述第二半导体芯片60上并与所述第二半导体芯片60电连接。具体的，所述第二半导体芯片60包括若干第一焊盘61，部分所述第一焊盘61通过金属导电层80与所述第一半导体芯片70实现电连接。
如图2及图9所示，进行步骤S6，于所述第一半导体芯片70与所述第二半导体芯片60之间形成第一填充层90，使所述第一填充层90包覆所述金属导电层80。
如图2及图10所示，进行步骤S7，于所述第二重新布线层30上形成第一封装层100，所述第一封装层100包覆所述金属连接柱40、所述第一半导体芯片70及所述第二半导体芯片60。
具体的，形成所述第一封装层100的方法包括但不限于压缩成型、传递模塑成型、液封成型、真空层压及旋涂中的一种。另外，如图11所示，在形成所述第一封装层100后，还可采用研磨或抛光的方法作用于所述第一封装层100的上表面，以提供平整的所述第一封装层100，并使所述第一封装层100的上表面与所述金属连接柱40的上表面平齐。
如图2及图12所示，进行步骤S8，于所述第一封装层100上形成第一重新布线层110，所述第一重新布线层110包括第一介质层111和位于所述第一介质层111中的第一金属线层112，将所述第一金属线层112与所述第二半导体芯片60及所述金属连接柱40电连接。其中，所述第一金属线层112可通过金属柱120与所述第二半导体芯片60的所述第一焊盘61实现电连接。
形成所述第一重新布线层110的具体步骤包括：采用化学气相沉积工艺或物理气相沉积工艺形成第一沉积介质层，对所述第一沉积介质层进行刻蚀形成图形化的所述第一介质层111；
采用化学气相沉积工艺、物理气相沉积工艺、蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺于所述第一介质层111的表面形成第一金属层，对所述第一金属层进行刻蚀形成所述第一金属线层112。
如图2及图13所示，进行步骤S9，需要先对所述第一重新布线层110进行刻蚀，以显露所述第一重新布线层110中的所述第一金属线层112，然后于所述第一重新布线层110远离所述第一封装层100的表面上形成凸块130，将所述凸块130与所述第一金属线层112电连接。
如图2及图14所示，进行步骤S10，提供承载体140，将前述步骤得到的封装结构倒放于所述承载体140上(所述凸块130朝下)。作为示例，所述承载体140选自玻璃基底、金属基底、半导体基底、聚合物基底及陶瓷基底中的一种
如图2、图14及图15所示，进行步骤S11，基于所述分离层20剥离所述支撑基底10，可使用曝光的方法降低分离层20粘性，实现剥离，以暴露出所述第二重新布线层30远离所述第一封装层100的表面。
如图2及图16所示，进行步骤S12，提供功能芯片150，将所述功能芯片150与所述第二金属线层32电连接。具体的，所述功能芯片150包括若干第二焊盘151，所述第二焊盘151上形成有焊料连接结构160，所述功能芯片150与所述第二金属线层32之间通过所述焊料连接结构160实现电连接。另外，还可提供电容、电阻和电感等被动元件，将所述被动元件与所述第二金属线层32电连接。
如图2及图17所示，进行步骤S13，于所述功能芯片150与所述第二重新布线层30之间形成第二填充层170。
如图2及图18所示，进行步骤S14，于所述第二重新布线层30远离所述第一封装层100的表面上形成第二封装层180，所述第二封装层180包覆所述功能芯片150，具体形成所述第二封装层180的方法请参阅所述第一封装层100的形成方法，在此不再赘述。
进行步骤S15，去除所述承载体，得到如图1所示的本发明的三维扇出型集成封装结构。
综上所述，本发明提供一种三维扇出型集成封装结构及其封装方法和无线耳机，形成的三维扇出型集成封装结构通过将两半导体芯片进行堆叠设置，有效减小了封装面积，可实现高密度高集成度的器件封装，同时使得最小线宽线距可降至1.5μm/1.5μm，远小于传统基板的20μm/20μm。另外，本发明的三维扇出型集成封装结构可以同时整合GPU/PMU/DDR/毫米波天线/电容/电感/电晶体/闪存/滤波器等各种功能芯片和元器件，实现系统级封装，不仅能够降低成本，而且通过采用物理隔离的方式减少器件干扰，提高了封装结构的效能。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (14)

1.一种三维扇出型集成封装结构，其特征在于，所述三维扇出型集成封装结构包括：
平行设置的第一重新布线层及第二重新布线层；
金属连接柱，位于所述第一重新布线层与所述第二重新布线层之间，且两端分别与所述第一重新布线层与所述第二重新布线层电连接；
第一半导体芯片及堆叠在所述第一半导体芯片上的第二半导体芯片，均位于所述第一重新布线层与所述第二重新布线层之间，所述第一半导体芯片与所述第二半导体芯片电连接，其中所述第二半导体芯片还与所述第一重新布线层电连接；
第一填充层，填充在所述第一半导体芯片和所述第二半导体芯片之间；
第一封装层，位于所述第一重新布线层和所述第二重新布线层之间，且包覆所述金属连接柱、所述第一半导体芯片及所述第二半导体芯片；
功能芯片，位于所述第二重新布线层远离所述第一封装层的表面上，并与所述第二重新布线层电连接；
第二填充层，填充在所述功能芯片与所述第二重新布线层之间；
第二封装层，位于所述第二重新布线层远离所述第一封装层的表面上，并包覆所述功能芯片；
凸块，位于所述第一重新布线层远离所述第一封装层的表面上，并与所述第一重新布线层电连接。
2.根据权利要求1所述的三维扇出型集成封装结构，其特征在于：所述第一半导体芯片包括射频芯片，所述第二半导体芯片包括单片机，所述功能芯片包括存储芯片。
3.根据权利要求1所述的三维扇出型集成封装结构，其特征在于：所述第二半导体芯片包括若干第一焊盘，部分所述第一焊盘通过位于所述第一封装层中的金属柱与所述第一重新布线层电连接，另一部分所述第一焊盘通过位于所述第一填充层中的金属导电层与所述第一半导体芯片电连接；所述功能芯片包括若干第二焊盘，所述第二焊盘上形成有焊料连接结构，所述焊料连接结构与所述第二重新布线层连接。
4.根据权利要求3所述的三维扇出型集成封装结构，其特征在于：所述焊料连接结构包括焊球和导电柱，所述导电柱的一端与所述第二焊盘连接，另一端与所述焊球连接；所述焊球再与所述第二重新布线层连接。
5.根据权利要求1所述的三维扇出型集成封装结构，其特征在于：所述第二半导体芯片与所述第二重新布线层之间设有粘接层，所述粘接层用于固定所述第二半导体芯片。
6.根据权利要求1所述的三维扇出型集成封装结构，其特征在于：所述第一重新布线层包括第一介质层和位于所述第一介质层中的第一金属线层，所述第一介质层和所述第一金属线层交替层叠；所述第二重新布线层包括第二介质层和位于所述第二介质层中的第二金属线层，所述第二介质层和所述第二金属线层交替层叠。
7.根据权利要求6所述的三维扇出型集成封装结构，其特征在于：所述第一介质层的材料包括环氧树脂、氧化硅、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第二介质层的材料包括环氧树脂、氧化硅、聚酰亚胺及硅胶中的一种或两种以上的组合。
8.根据权利要求1所述的三维扇出型集成封装结构，其特征在于：所述第一封装层的材料包括环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第二封装层的材料包括环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第一填充层的材料包括环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合；所述第二填充层的材料包括环氧树脂、聚酰亚胺及硅胶中的一种或两种以上的组合。
9.根据权利要求1所述的三维扇出型集成封装结构，其特征在于：所述凸块包括铜凸块、锡凸块、铝凸块及镍凸块中的一种或两种以上的组合。
10.根据权利要求1所述的三维扇出型集成封装结构，其特征在于：所述三维扇出型集成封装结构还包括被动元件，所述被动元件包括电容、电阻和电感，所述被动元件位于所述第二重新布线层远离所述第一封装层的表面上，并与所述第二重新布线层电连接。
11.一种无线耳机，其特征在于：所述无线耳机包括如权利要求1-10任一所述三维扇出型集成封装结构。
12.一种三维扇出型集成封装结构的制备方法，其特征在于，所述制备方法包括以下步骤：
提供支撑基底，于所述支撑基底上形成分离层；
于所述分离层上形成第二重新布线层，所述第二重新布线层包括第二介质层和位于所述第二介质层中的第二金属线层；
于所述第二重新布线层上形成金属连接柱，将所述金属连接柱与所述第二金属线层电连接；
提供第二半导体芯片，将所述第二半导体芯片与所述第二重新布线层粘合；
提供第一半导体芯片，将所述第一半导体芯片堆叠在所述第二半导体芯片上并与所述第二半导体芯片电连接；
于所述第一半导体芯片与所述第二半导体芯片之间形成第一填充层；
于所述第二重新布线层上形成第一封装层，所述第一封装层包覆所述金属连接柱、所述第一半导体芯片及所述第二半导体芯片；
于所述第一封装层上形成第一重新布线层，所述第一重新布线层包括第一介质层和位于所述第一介质层中的第一金属线层，将所述第一金属线层与所述第二半导体芯片及所述金属连接柱电连接；
于所述第一重新布线层远离所述第一封装层的表面上形成凸块，将所述凸块与所述第一金属线层电连接；
提供承载体，将前述步骤得到的封装结构倒放于所述承载体上；
基于所述分离层剥离所述支撑基底，以暴露出所述第二重新布线层远离所述第一封装层的表面；
提供功能芯片，将所述功能芯片与所述第二金属线层电连接；
于所述功能芯片与所述第二重新布线层之间形成第二填充层；
于所述第二重新布线层远离所述第一封装层的表面上形成第二封装层，所述第二封装层包覆所述功能芯片；
去除所述承载体。
13.根据权利要求12所述的三维扇出型集成封装结构的制备方法，其特征在于：所述支撑基底选自玻璃基底、金属基底、半导体基底、聚合物基底及陶瓷基底中的一种；所述承载体选自玻璃基底、金属基底、半导体基底、聚合物基底及陶瓷基底中的一种；所述分离层选自胶带层或聚合物层，通过旋涂工艺将所述分离层涂覆于所述支撑基底表面，然后使用激光固化或紫外固化或热固化工艺使所述分离层固化成型。
14.根据权利要求12所述的三维扇出型集成封装结构的制备方法，其特征在于：形成所述第一重新布线层及所述第二重新布线层的步骤包括：
采用化学气相沉积工艺或物理气相沉积工艺形成第一沉积介质层及第二沉积介质层，对所述第一沉积介质层进行刻蚀形成图形化的所述第一介质层，对所述第二沉积介质层进行刻蚀形成图形化的所述第二介质层；
采用化学气相沉积工艺、物理气相沉积工艺、蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺于所述第一介质层及所述第二介质层的表面对应形成第一金属层及第二金属层，对所述第一金属层进行刻蚀形成所述第一金属线层，对所述第二金属层进行刻蚀形成所述第二金属线层，将所述第一金属线层及所述第二金属线层通过所述金属连接柱电连接。
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