CN113874848A - 用于促进网络接口控制器(nic)中对加速器的操作管理的系统和方法 - Google Patents

用于促进网络接口控制器(nic)中对加速器的操作管理的系统和方法 Download PDF

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Publication number
CN113874848A
CN113874848A CN202080029985.4A CN202080029985A CN113874848A CN 113874848 A CN113874848 A CN 113874848A CN 202080029985 A CN202080029985 A CN 202080029985A CN 113874848 A CN113874848 A CN 113874848A
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China
Prior art keywords
nic
accelerator
network interface
interface controller
trigger
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Inventor
D·罗威斯
A·S·科普瑟
K·坎德拉
L·S·卡普兰
I·戈罗德斯基
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Hewlett Packard Enterprise Development LP
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Hewlett Packard Enterprise Development LP
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Abstract

提供了一种能够对主机加速器进行高效操作管理的网络接口控制器(NIC)。NIC可以配备有主机接口和触发逻辑块。在操作期间，主机接口可以将NIC耦接到主机设备。触发逻辑块可以经由主机接口从主机设备获得与主机设备的加速器相关联的操作。触发逻辑块可以基于从加速器接收到的指示符来确定是否已满足对于该操作的触发条件。如果已满足触发条件，则触发逻辑块可以从存储器位置获得产生于加速器的数据片段并使用该数据片段来执行该操作。

Description

用于促进网络接口控制器(NIC)中对加速器的操作管理的系 统和方法
发明人：D·罗威斯、A·S·科普瑟、K·坎德拉、L·S·卡普兰以及I·戈罗德斯基
背景
技术领域
这通常涉及网络化的技术领域。更具体地，本公开涉及用于促进网络接口控制器(NIC)对主机加速器的高效操作管理的系统和方法。
相关技术
随着支持网络的设备和应用变得越来越普及，各种类型的流量以及不断增加的网络负载继续要求来自底层网络架构的更高性能。例如，诸如高性能计算(HPC)、媒体串流和物联网(IOT)之类的应用可以产生具有鲜明特性的不同类型的流量。结果，除了常规的网络性能指标(诸如，带宽和延迟)之外，网络架构继续面临诸如可扩展性、多功能性和效率之类的挑战。
发明内容
提供了一种能够对主机加速器进行高效操作管理的网络接口控制器(NIC)。NIC可以配备有主机接口和触发逻辑块。在操作期间，主机接口可以将NIC耦接到主机设备。触发逻辑块可以经由主机接口从主机设备获得与主机设备的加速器相关联的操作。触发逻辑块可以基于从加速器接收到的指示符来确定是否已满足对于该操作的触发条件。如果已满足触发条件，则触发逻辑块可以从存储器位置获得产生于加速器的数据片段并使用该数据片段来执行该操作。
附图说明
图1示出了示例性网络。
图2A示出了带有多个NIC的示例性NIC芯片。
图2B示出了NIC的示例性架构。
图3示出了NIC中的对主机加速器的示例性操作管理。
图4A示出了NIC的主机设备中的触发操作产生过程的流程图。
图4B示出了NIC中的触发操作管理过程的流程图。
图4C示出了NIC中的触发操作执行过程的流程图。
图5示出了配备有NIC的示例性计算机系统，该NIC促进对主机加速器的高效操作管理。
在附图中，相似的附图标记指代相同的附图元素。
具体实施方式
对所公开的实施例的各种修改对于本领域技术人员来说将是显而易见的，并且在不脱离本公开的精神和范围的情况下，可将本文中所定义的一般原理应用于其他实施例和应用。因此，本发明并不限于所示的实施例。
概述
本公开描述了促进网络接口控制器(NIC)中对主机加速器的操作管理的系统和方法。NIC允许主机与数据驱动的网络进行通信。
本文中所描述的实施例通过以下方式来解决促进针对加速器的高效通信操作的问题：(i)由主机处理器产生针对加速器的通信操作，以及(ii)向NIC提供这些通信操作并允许加速器在NIC处触发这些操作。通过这种方式，加速器可以在不实施协议栈的情况下进行通信。
在操作期间，可以在NIC的主机设备上操作的应用程序可以发布涉及重要和复杂计算的命令。主机设备可使用加速器(诸如，图形处理单元(GPU)或张量处理单元(TPU))来高效地执行这种计算。然而，加速器可促进标量计算，这可能不是非常适合运行通信栈。此外，促进计算结果到主机处理器(例如，主机设备的中央处理器)会是耗时的。结果，从加速器发布通信操作可能是低效的，并且在向远程设备提供计算结果时引起延迟。
为了解决这个问题，NIC可以存储由主机处理器产生的通信操作并允许加速器在NIC处触发操作。在操作期间，主机处理器可预先准备通信操作并将操作存储在命令队列中，该命令队列可以存储在主机设备的存储器设备中。在完成一组计算时，加速器可将计算的结果或成果存储在预定位置中。该位置可以在主机设备的存储器设备或NIC的存储器设备中。
NIC可预取该操作并将该操作存储在NIC的预取队列中。然后，加速器可以通过通知NIC来触发该操作。作为响应，NIC可从命令队列或NIC的预取队列获得通信操作。NIC也可以从预定位置获得结果。随后，NIC可以以结果作为有效负载或参数来发布通信操作。在一些实施例中，通信操作是远程直接存储器访问(RDMA)操作，诸如“GET”或“PUT”命令。通过这种方式，NIC可以促进针对加速器的高效通信操作，而无需加速器实施通信栈。由于通信操作是可以触发的预先产生的操作，因此可以将这种操作称为触发操作。NIC可基于计数事件来促进触发操作。NIC可以维持计数器(例如，硬件实施的计数器)和计数事件的阈值。基于接口的命令可引起导致NIC递增计数器。例如，加速器可执行多个线程或进程。当线程或进程完成所分配的计算时，该线程或进程可以向NIC发布基于接口的命令。
基于接口的命令可以包括计数器的句柄(例如，指针或标识符)。在接收到命令时，NIC可以递增计数器。当计数器值变得大于或等于阈值时，NIC可以确定已满足触发条件。因此，NIC可以触发通信操作。此处，阈值可以对应于线程(或进程)的数量。通过这种方式，每个线程或进程可以独立地通知NIC，并且针对加速器所有线程的计算的完成可以作为触发器操作。
本发明的一个实施例提供了一种NIC，其可以配备有主机接口和触发逻辑块。在操作期间，主机接口可以将NIC耦接到主机设备。触发逻辑块可以经由主机接口从主机设备获得与主机设备的加速器相关联的操作。触发逻辑块可以基于从加速器接收到的指示符来确定是否已满足对于该操作的触发条件。如果已满足触发条件，则触发逻辑块可以从存储器位置获得产生于加速器的数据片段并使用该数据片段来执行该操作。在关于此实施例的变型中，存储器位置包括以下各者中的一者或多者：(i)主机设备的存储器设备的位置，以及(ii)NIC的存储器设备的位置。
在关于此实施例的变型中，其中，NIC可以包括计数器电路。触发逻辑块可以基于从加速器接收到的指示符来递增由计数器电路存储的计数器值。
在进一步的变型中，触发逻辑块可以通过将计数器值与由操作指示的阈值进行比较来确定是否已满足触发条件。
在进一步的变型中，如果尚未满足触发条件，则触发逻辑块可以将操作插入存储与计数器电路相关联的一个或多个操作的数据结构中。
在进一步的变型中，触发逻辑块可以从加速器接收多个指示符并针对相应的指示符来递增由计数器电路存储的计数器值。
在关于此实施例的变型中，触发逻辑块可以基于直接存储器访问(DMA)命令来获得该数据片段。
在关于此实施例的变型中，该操作是在产生该数据片段之前产生的。
在关于此实施例的变型中，触发逻辑块可以从主机设备的存储器设备中的命令队列获得该操作并将该操作存储在网络接口控制器的预取队列中。
在关于此实施例的变型中，主机接口可以是外围部件互连快速(PCIe)接口。触发逻辑块可基于PCIe命令来接收指示符。
在本公开中，结合图1的描述与网络架构相关联，并且结合图2A及以后的描述提供了关于与NIC相关联的架构和操作的更多详细信息，该NIC支持对主机加速器的高效操作管理。
图1示出了示例性网络。在此示例中，交换机的网络100(其也可以被称为“交换机结构”)可以包括交换机102、104、106、108和110。每个交换机在交换机结构100内可以具有唯一的地址或ID。各种类型的设备和网络均可以耦接到交换机结构。例如，存储阵列112可以经由交换机110耦接到交换机结构100；基于无限带宽(IB)的HPC网络114可以经由交换机108耦接到交换机结构100；多个终端主机(诸如，主机116)可以经由交换机104耦接到交换机结构100；并且IP/以太网网络118可以经由交换机102耦接到交换机结构100。一般来说，交换机可以具有边缘端口和结构端口。边缘端口可以耦接到结构外部的设备。结构端口可以经由结构链路耦接到结构内的另一个交换机。通常，流量可以经由边缘交换机的入口端口注入到交换机结构100中，并且经由另一个(或同一个)边缘交换机的出口端口离开交换机结构100。入口链路可以将边缘设备(例如，HPC终端主机)的NIC耦接到边缘交换机的入口边缘端口。然后，交换机结构100可以将流量传输到出口边缘交换机，该出口边缘交换机进而可以经由另一个NIC将流量传递到目的地边缘设备。
示例性NIC架构
图2A示出了带有多个NIC的示例性NIC芯片。参考图1中的示例，NIC芯片200可以是定制的专用集成电路(ASIC)，其被设计用于使主机116与交换机结构100一起工作。在此示例中，芯片200可以提供两个独立的NIC 202和204。芯片200的相应NIC可以配备有主机接口(HI)(例如，用于连接到主机处理器的接口)和一个高速网络接口控制器(HNI)，该HNI用于与耦接到图1的交换机结构100的链路进行通信。例如，NIC 202可以包括HI 210和HNI 220，且NIC 204可以包括HI 211和HNI 221。在一些实施例中，HI 210可以是外围部件互连(PCI)或外围部件互连快速(PCIe)接口。HI 210可以经由主机连接201耦接到主机，该主机连接可以包括N个(例如，在一些芯片中N可以是16)能够以每道高达25Gbps的信号发送速率操作的PCIe Gen 4道。HNI 210可以促进高速网络连接件203，该高速网络连接件可以与图1的交换机结构100中的链路进行通信。HNI 210可以使用M个(例如，在一些芯片中M可以是4)全双工串行道以100Gbps抑或200Gbps的聚合速率操作。M个道中的每一个可以分别基于不归零(NRZ)调制或脉冲幅度调制4(PAM4)以25Gbps或50Gbps操作。HNI 220可以支持电气和电子工程师协会(IEEE)802.3的基于以太网的协议以及增强帧格式，该增强帧格式提供对更高速率的小消息的支持。
NIC 202可以支持以下各者中的一者或多者：基于消息传递接口(MPI)的点对点消息传递、远程存储器访问(RMA)操作、批量数据集合操作的卸载和进展、以及以太网包处理。当主机发布MPI消息时，NIC 202可以匹配对应的消息类型。此外，NIC 202可以为MPI实施紧迫协议和汇聚协议两者，从而从主机卸载对应的操作。
此外，由NIC 202支持的RMA操作可以包括PUT、GET和原子存储器操作(AMO)。NIC202可以提供可靠的传输。例如，如果NIC 202是源NIC，则NIC 202可以为幂等操作提供重试机制。此外，基于连接的错误检测和重试机制可以用于可操纵目标状态的有序操作。NIC202的硬件可以维持重试机制所必要的状态。通过这种方式，NIC 202可以减轻主机(例如，软件)上的负担。决定重试机制的策略可以由主机通过软件来指定，从而确保NIC 202的灵活性。
此外，NIC 202可以促进触发操作、用于卸载的通用机制、以及相依性操作序列(诸如，批量数据集合)的进展。NIC 202可以支持应用程序编程接口(API)(例如，libfabricAPI)，该API促进由图1的交换机结构100向主机116上运行的应用程序提供的结构通信服务。NIC 202还可以支持低级网络编程接口，诸如门户API。另外，NIC 202可以提供高效的以太网包处理，该以太网包处理可以包括高效传输(如果NIC 202是发送者)、流转向(如果NIC202是目标)以及检查和计算。此外，NIC 202可以支持虚拟化(例如，使用容器或虚拟机)。
图2B示出了NIC的示例性架构。在NIC 202中，HNI 220的端口宏可以促进低级以太网操作，诸如物理编码子层(PCS)和媒体访问控制(MAC)。另外，NIC 202可以提供对链路层重试(LLR)的支持。传入包可以由解析器228进行解析并存储在缓冲区229中。缓冲区229可以是PFC缓冲区，其被提供来缓冲阈值量(例如，一微秒)的延迟带宽。HNI 220还可以包括分别用于管理传出包和传入包的控制传输单元224和控制接收单元226。
NIC 202可以包括命令队列(CQ)单元230。CQ单元230可以负责取得和发布主机侧命令。CQ单元230可以包括命令队列232和调度器234。命令队列232可以包括分别用于发起者命令(PUT、GET等)和目标命令(Append、搜索等)的独立的两组队列。命令队列232可以被实施为维持在NIC 202的存储器中的循环缓冲区。在主机上运行的应用程序可以直接写入到命令队列232。调度器234可以包括分别用于发起者命令和目标命令的两个单独的调度器。发起者命令基于散列函数被分类到流队列236中。流队列236中的一个可以被分配给独特的流。此外，CQ单元230可以进一步包括触发操作模块(或逻辑块)238，该触发操作模块负责排队和分派所触发的命令。
出站传输引擎(OXE)240可以从流队列236拉取命令，以便处理它们来进行分派。OXE 240可以包括地址转换请求单元(ATRU)244，该ATRU可以向地址转换单元(ATU)212发送地址转换请求。ATU 212可以代表不同的引擎(诸如，OXE 240、入站传输引擎(IXE)250和事件引擎(EE)216)来提供虚拟到物理地址转换。ATU 212可以维持大的转换高速缓存214。ATU212可以自己执行转换，抑或可使用基于主机的地址转换服务(ATS)。OXE 240还可以包括消息截断单元(MCU)246，该MCU可以将大的消息分段成大小对应于最大传输单元(MTU)的包。MCU 246可以包括多个MCU模块。当MCU模块变得可用时，MCU模块可以从所指派的流队列获得下一个命令。接收到的数据可以被写入到数据缓冲区242。然后，MCU模块可以向流量整形器248发送包报头、对应的流量类别和包大小。整形器248可以确定由MCU 246呈现的哪些请求可以进入网络。
随后，所选择的包可以被发送到包和连接跟踪(PCT)270。PCT 270可以将包存储在队列274中。PCT 270还可以维持出站命令的状态信息并且随着响应的返回来更新状态信息。PCT 270还可以维持包状态信息(例如，允许响应与请求匹配)、消息状态信息(例如，跟踪多包消息的进度)、发起者完成状态信息和重试状态信息(例如，在请求或响应丢失的情况下维持重试命令所需的信息)。如果在阈值时间内没有返回响应，则可以将对应的命令存储在重试缓冲区272中。PCT 270可以分别基于源表276和目标表278来促进对发起者命令和目标命令的连接管理。例如，PCT 270可以更新其源表276以跟踪可靠地传递包和消息完成通知所必要的状态。PCT 270可以将传出包转发到HNI 220，后者将这些包存储在出站队列222中。NIC 202还可以包括IXE 250，如果NIC 202是目标或目的地，则该IXE提供包处理。IXE 250可以从HNI 220获得传入包。解析器256可以对这些传入包进行解析并将对应的包信息传递到列表处理引擎(LPE)264或消息状态表(MST)266以进行匹配。LPE 264可以将传入消息与缓冲区进行匹配。LPE 264可以确定每个消息要使用的缓冲区和起始地址。LPE264还可以管理用于表示缓冲区和意外消息的列表条目262池。MST 266可以存储匹配结果和产生目标侧完成事件所需的信息。MST 266可以由不受限制的操作使用，所述不受限制的操作包括多包PUT命令以及单包和多包GET命令。
随后，解析器256可以将包存储在包缓冲区254中。IXE 250可以获得用于冲突检查的匹配结果。然后，DMA写入和AMO模块252可以向存储器发布由写入和AMO操作产生的更新。如果包括产生目标侧存储器读取操作(例如，GET响应)的命令，则该包可以被传递到OXE240。NIC 202还可以包括EE 216，该EE可以从NIC 202中的其他模块或单元接收产生事件通知的请求。事件通知可以指定产生填充事件抑或计数事件。EE216可以管理位于主机处理器存储器内的事件队列，它向该主机处理器存储器写入完整的事件。EE 216可以将计数事件转发到CQ单元230。
NIC中的操作管理
图3示出了NIC中的对主机加速器的示例性操作管理。在此示例中，主机设备300可以配备有NIC 330。设备300可以包括处理器302、存储器设备304、接口系统306和一组加速器308。NIC 330的HI 332可以耦接到设备330的接口系统306。在一些实施例中，HI 332可以是PCIe接口，并且接口系统306可以是为HI 332提供插槽的PCIe系统。加速器308可以包括多个加速器312、314、316和318。加速器可以是任何可以执行广泛计算和专门化计算的处理单元，诸如GPU或TPU。通常，可以在设备300上操作的应用程序可以发布涉及重要和复杂计算的命令。设备300可使用加速器312来高效地执行这种计算。然而，加速器312可促进标量计算，这可能不是非常适合运行通信栈。此外，促进计算结果到处理器302会是耗时的。结果，从加速器312发布通信操作可能是低效的，并且在经由NIC 330向远程设备提供计算结果时引起延迟。
为了解决这个问题，代替加速器312维持通信栈的是，处理器302可以产生针对加速器312的通信操作并向NIC 330提供这些通信操作。为了与远程设备进行通信，加速器312可以在NIC 330处触发这些操作并且可以在不实施通信栈(例如，协议栈)的情况下进行通信。在操作期间，处理器302可以在加速器312可能需要发布操作324之前准备通信操作324。处理器302可以将操作324存储在命令队列中，该命令队列可以存储在存储器设备304中。由于操作324是可以触发的预先产生的操作，因此操作324可以是触发操作。
在完成一组计算时，加速器312可将计算的结果322存储在预定位置中。该位置可以在存储器设备304或NIC 330的存储器设备中。NIC 330可经由HI 332预取操作324并将操作324存储在NIC 330的预取队列334中。然后，加速器312可以通过通知NIC330来触发操作324。作为响应，触发操作(TO)模块336可从命令队列或预取队列334获得操作324。TO模块336还可以从预定位置获得结果322。随后，TO模块336可以以结果322作为有效负载或参数来发布操作324。通过这种方式，NIC 330可以促进针对加速器312的高效通信操作，而无需加速器312实施通信栈。
应用程序可能不需要接收对各个计算的确认。如果NIC 330可以提供指示一组计算已成功完成的确认，则可以满足应用程序的要求。NIC 330可以促进事件机制(其可以被称为计数事件)，以促进这种累积确认。NIC 330可基于计数事件来促进操作324。TO模块336可以排队并激活NIC 330中的触发操作。NIC 330可以维持一组基于硬件的计数器342(例如，一组2048个计数器)。操作324可以包括该组计数器342中的计数器344的句柄(例如，指针或标识符)。操作324还可以包括阈值。当计数器344达到阈值时，TO模块336确定已满足对于操作324的触发条件。因此，TO模块336可以触发操作324。在从预取队列334获得操作324时，TO模块336可确定操作324和计数器344是否属于同一资源组。如果它们属于同一资源组，则TO模块336还可以检查计数器344的当前值是否大于或等于阈值。如果阈值更大(通常是这种情况)，则TO模块336可以将操作324添加到与计数器344相关联的触发操作列表340。
在一些实施例中，可以基于列表340中的操作的对应阈值对列表340进行分类。每次计数器344递增时，TO模块336便可以检查列表340中的相应操作是否已达到针对那个操作所定义的阈值。通过这种方式，可以使用同一个计数器344来表示多个操作。如果计数器344的值达到与操作324相关联的阈值，则TO模块336可以从列表340中移除操作324并将操作324插入到触发操作流队列338中的对应的流队列中。NIC 330可以调度从流队列对操作324的转发，如结合图2B所描述的。
在一些实施例中，加速器312可以发布基于接口的操作(例如，基于PCIe的事务)，该操作可以递增计数器344。加速器312可以通过运行一个或多个线程(或进程)来执行计算。每个线程可在计算的不同阶段发布基于接口的命令。线程可以独立地递增计数器而不需要使这些线程同步，因为每个基于接口的操作均可以促进经由HI 332的原子写入。处理器302可以为同一个计数器344提供具有不同阈值的多个触发操作。这可以允许加速器312上的不同计算阶段触发对应的通信操作。
当计数器344达到操作324的阈值时，NIC 330可以将指示符写回到存储器设备304的可由在加速器312上运行的线程访问的部分中。该指示符可以是阈值。线程触发操作324可周期性地轮询写回位置。在检测到写回位置处的变化时，线程可确定操作324已完成。
图4A示出了NIC的主机设备中的触发操作产生过程的流程图。在操作期间，主机设备可以产生针对加速器的触发操作(操作402)。然后，主机设备可以基于对应的计数器将计数事件与触发操作相关联(操作404)。随后，主机设备可为计数事件设定阈值水平(操作406)并将触发操作存储在本地命令队列中(操作408)。
图4B示出了NIC中的触发操作管理过程的流程图。在操作期间，NIC的TO模块可以从命令队列获得触发操作并存储在NIC的预取队列中(操作432)。然后，TO模块可以基于调度器从预取队列中检索触发操作(操作434)并识别与触发操作相关联的计数器(例如，基于句柄)(操作436)。TO模块可以确定计数器值是否小于阈值(操作438)。
如果计数器值小于阈值，则TO模块可以将触发操作存储在触发操作列表中(操作440)并以相应的增量来检查计数器值(操作442)。然后，TO模块可以继续确定计数器值是否小于阈值(操作438)。另一方面，如果计数器值已达到阈值，则TO模块可以设定触发器(操作444)。
图4C示出了NIC中的触发操作执行过程的流程图。在操作期间，NIC的TO模块可以确定操作已被触发(操作452)。然后，TO模块可以确定对应的数据是否存储在本地存储器中(操作454)。如果数据没有存储在本地存储器中，则TO模块可以基于DMA访问从主机设备的存储器设备获得相关联的数据(操作456)。另一方面，如果数据存储在本地存储器中，则TO模块可以基于DMA访问从本地存储器设备获得相关联的数据(操作458)。在获得相关联的数据(操作456或458)时，TO模块可以将操作和相关联的数据存储在对应的流队列中(操作460)。
示例性计算机系统
图5示出了配备有NIC的示例性计算机系统，该NIC促进对主机加速器的高效操作管理。计算机系统550包括处理器552、存储器设备554、存储设备556和加速器558。存储器设备554可以包括易失性存储器设备(例如，双列直插式存储器模块(DIMM))。此外，计算机系统550可以耦接到键盘562、指点设备564和显示设备566。存储设备556可以存储操作系统570。应用程序572可以在操作系统570上进行操作。
计算机系统550可以配备有主机接口，该主机接口使促进高效操作管理的NIC 520耦接。NIC 520可以向计算机系统550提供一个或多个HNI。NIC 520可以经由HNI中的一个耦接到交换机502。NIC 520可以包括TO逻辑块530，如结合图2B和图3所描述的。TO逻辑块530可以包括监视逻辑块532、触发逻辑块534和转发逻辑块536。
监视逻辑块532可以从存储器设备554中的命令队列获得触发操作并存储在NIC520的预取队列中。该触发操作可以由处理器552针对加速器558预先产生。监视逻辑块520可以监视与触发操作相关联的状态(例如，用于计数事件的计数器)。加速器558可以改变触发操作的状态。触发逻辑块534可以基于状态(例如，计数器已达到阈值)来确定触发该操作的条件是否已出现。如果该条件已出现，则触发逻辑块534可以触发该操作并从存储器位置获得相关联的数据。随后，转发逻辑块536可以执行与触发操作相关联的通信操作。
总之，本公开描述了一种促进对主机加速器的高效操作管理的NIC。NIC可以配备有主机接口和触发逻辑块。在操作期间，主机接口可以将NIC耦接到主机设备。触发逻辑块可以经由主机接口从主机设备获得与主机设备的加速器相关联的操作。触发逻辑块可以基于从加速器接收到的指示符来确定是否已满足对于该操作的触发条件。如果已满足触发条件，则触发逻辑块可以从存储器位置获得产生于加速器的数据片段并使用该数据片段来执行该操作。
上文所描述的方法和过程可以由硬件逻辑块、模块或装置来执行。硬件逻辑块、模块、逻辑块或装置可以包括但不限于专用集成电路(ASIC)芯片、现场可编程门阵列(FPGA)、在特定时间执行一段代码的专用或共享处理器、以及现在已知或以后开发的其他可编程逻辑设备。当硬件逻辑块、模块或装置被激活时，它们执行包含在其内的方法和过程。
本文中所描述的方法和过程也可以被体现为代码或数据，其可以存储在存储设备或计算机可读存储介质中。当处理器读取并执行所存储的代码或数据时，处理器可以执行这些方法和过程。
已仅出于图示和描述的目的呈现了本发明的实施例的前述描述。它们并非旨在为穷举的或将本发明限制于所公开的形式。因此，许多修改和变型对于本领域技术人员来说将是显而易见的。附加地，以上公开并非旨在限制本发明。本发明的范围由所附权利要求限定。

Claims (20)

1.一种网络接口控制器(NIC)，其包括：
主机接口，其将主机设备耦接；以及
触发逻辑块，其用于：
经由所述主机接口从所述主机设备获得与所述主机设备的加速器相关联的操作；
基于从所述加速器接收到的指示符来确定是否已满足对于所述操作的触发条件；以及
响应于确定已满足所述触发条件，从存储器位置获得产生于所述加速器的数据片段，并且使用所述数据片段来执行所述操作。
2.如权利要求1所述的网络接口控制器，其中，所述存储器位置包括以下各项中的一者或多者：
所述主机设备的存储器设备的位置；以及
所述网络接口控制器的存储器设备的位置。
3.如权利要求1所述的网络接口控制器，其进一步包括计数器电路；其中，所述触发逻辑块进一步用于基于从所述加速器接收到的所述指示符来递增由所述计数器电路存储的计数器值。
4.如权利要求3所述的网络接口控制器，其中，所述触发逻辑块进一步用于通过将所述计数器值与由所述操作指示的阈值进行比较来确定是否已满足所述触发条件。
5.如权利要求3所述的网络接口控制器，其中，响应于确定尚未满足所述触发条件，所述触发逻辑块进一步用于将所述操作插入存储与所述计数器电路相关联的一个或多个操作的数据结构中。
6.如权利要求3所述的网络接口控制器，其中，所述触发逻辑块进一步用于：
从所述加速器接收多个指示符；以及
针对相应的指示符来递增由所述计数器电路存储的所述计数器值。
7.如权利要求1所述的网络接口控制器，其中，所述触发逻辑块进一步用于基于直接存储器访问(DMA)命令来获得所述数据片段。
8.如权利要求1所述的网络接口控制器，其中，所述触发逻辑块进一步用于：
从所述主机设备的存储器设备中的命令队列获得所述操作；以及
将所述操作存储在所述网络接口控制器的预取队列中。
9.如权利要求1所述的网络接口控制器，其中，所述操作是在产生所述数据片段之前产生的。
10.如权利要求1所述的网络接口控制器，其中，所述主机接口是外围部件互连快速(PCIe)接口；并且
其中，所述触发逻辑块进一步用于基于PCIe命令来接收所述指示符。
11.一种用于促进网络接口控制器(NIC)中的高效操作管理的方法，所述方法包括：
经由将所述NIC耦接到主机设备的主机接口来获得与所述主机设备的加速器相关联的操作；
基于从所述加速器接收到的指示符来确定是否已满足对于所述操作的触发条件；以及
响应于确定已满足所述触发条件，从存储器位置获得产生于所述加速器的数据片段；以及使用所述数据片段来执行所述操作。
12.如权利要求11所述的方法，其中，所述存储器位置包括以下各项中的一者或多者：
所述主机设备的存储器设备的位置；以及
所述网络接口控制器的存储器设备的位置。
13.如权利要求11所述的方法，其进一步包括：基于从所述加速器接收到的所述指示符来递增所述NIC的计数器电路中的计数器值。
14.如权利要求13所述的方法，其进一步包括：通过将所述计数器值与由所述操作指示的阈值进行比较来确定是否已满足所述触发条件。
15.如权利要求13所述的方法，其中，响应于确定尚未满足所述触发条件，所述方法进一步包括将所述操作插入存储与所述计数器电路相关联的一个或多个操作的数据结构中。
16.如权利要求13所述的方法，其进一步包括：
从所述加速器接收多个指示符；以及
针对相应的指示符来递增由所述计数器电路存储的所述计数器值。
17.如权利要求11所述的方法，其进一步包括：基于直接存储器访问(DMA)命令来获得所述数据片段。
18.如权利要求11所述的方法，其进一步包括：
从所述主机设备的存储器设备中的命令队列获得所述操作；以及
将所述操作存储在所述网络接口控制器的预取队列中。
19.如权利要求11所述的方法，其中，所述操作是在产生所述数据片段之前产生的。
20.如权利要求11所述的方法，其中，所述主机接口是外围部件互连快速(PCIe)接口；并且
其中，所述方法进一步包括基于PCIe命令来接收所述指示符。
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