CN113711551A - 促进网络接口控制器（nic）中的动态命令管理的系统和方法 - Google Patents

促进网络接口控制器（nic）中的动态命令管理的系统和方法 Download PDF

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CN113711551A
CN113711551A CN202080029591.9A CN202080029591A CN113711551A CN 113711551 A CN113711551 A CN 113711551A CN 202080029591 A CN202080029591 A CN 202080029591A CN 113711551 A CN113711551 A CN 113711551A
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China
Prior art keywords
command
nic
queue
internal buffer
command queue
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CN202080029591.9A
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D·罗威斯
A·M·巴塔耶纳
E·L·弗洛伊斯
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Hewlett Packard Enterprise Development LP
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Hewlett Packard Enterprise Development LP
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Abstract

提供了一种能够进行高效命令管理的网络接口控制器(NIC)。所述NIC可以配备有主机接口、仲裁逻辑块和命令管理逻辑块。在操作期间，所述主机接口可以将所述NIC耦接到主机设备。所述仲裁逻辑块可以选择所述主机设备的命令队列来获得命令。所述命令管理逻辑块可以确定与所述命令队列相关联的内部缓冲区是否包含命令。如果所述内部缓冲区包含所述命令，则所述命令管理逻辑块可以从所述内部缓冲区获得所述命令。另一方面，如果所述内部缓冲区为空，则所述命令管理逻辑块可以经由所述主机接口从所述命令队列中获得所述命令。

Description

促进网络接口控制器（NIC）中的动态命令管理的系统和方法
背景
技术领域
本公开总体上涉及联网技术领域。更具体地，本公开涉及用于促进网络接口控制器 (NIC)进行高效命令管理的系统和方法。
相关技术
随着支持网络的设备和应用变得越来越普遍，各种类型的流量以及不断增加的网络负载继续要求底层网络架构提供更高的性能。例如，诸如高性能计算(HPC)、流媒体和物联网(IOT)等应用可以产生具有鲜明特征的不同类型的流量。因此，除了诸如带宽和延迟等传统网络性能指标外，网络架构师仍继续面临诸如可扩展性、多功能性和效率等挑战。
发明内容
提供了一种能够进行高效命令管理的网络接口控制器(NIC)。所述NIC可以配备有主机接口、仲裁模块和命令管理模块。在操作期间，所述主机接口可以将所述NIC耦接到主机设备。所述仲裁模块可以选择所述主机设备的命令队列来获得命令。所述命令管理模块可以确定与所述命令队列相关联的内部缓冲区是否包含命令。如果所述内部缓冲区包含所述命令，则所述命令管理模块可以从所述内部缓冲区获得所述命令。另一方面，如果所述内部缓冲区为空，则所述命令管理模块可以经由所述主机接口从所述命令队列中获得所述命令。
附图说明
图1示出了示例性网络。
图2A示出了具有多个NIC的示例性NIC芯片。
图2B示出了NIC的示例性架构。
图3A示出了NIC中的示例性动态命令管理过程。
图3B示出了用于促进NIC中的动态命令管理的示例性队列。
图4A示出了NIC中用于处理命令的动态队列选择过程的流程图。
图4B示出了主机设备的动态命令管理过程的流程图。
图4C示出了NIC中基于存储器的命令路径的动态命令管理过程的流程图。
图4D示出了NIC中低时延命令路径的动态命令管理过程的流程图。
图5示出了配备有促进动态命令管理的NIC的示例性计算机系统。
在这些附图中，相同的附图标记指代相同的附图元素。
具体实施方式
对所公开实施例的各种修改对于本领域技术人员来说将是显而易见的，并且在不脱离本公开的精神和范围的情况下，本文定义的一般原理可以应用于其他实施例和应用。因此，本发明不限于所示实施例。
概述
本公开描述了促进网络接口控制器(NIC)中的动态命令管理的系统和方法。NIC允许主机与数据驱动的网络进行通信。
本文描述的实施例通过以下方式来解决将命令高效地传输到NIC的问题：(i)促进主机设备中的命令队列和NIC中的内部命令缓冲区分别进行大规模和低时延的命令传输；以及(ii)在命令队列与内部缓冲区之间进行动态选择以接收命令。
在操作期间，NIC的主机设备可以向NIC发出用于数据操作的命令(例如，远程直接存储器存取(RDMA)的“GET”或“PUT”命令)。因此，主机设备可以将命令(例如，命令的直接存储器存取(DMA)描述符)传输到NIC。如果主机设备需要将大量命令传输到NIC，则主机设备可以将这些命令存储在主机设备的命令队列中。主机设备可以维持主机设备的存储器中的命令队列。当NIC准备好接收新命令(例如，具有可用于下一个命令的资源)时，NIC可以向主机设备请求命令。然后，主机设备的处理器可以将命令传输到NIC。
这种基于读取的方法基于NIC对主机设备的存储器进行存取。因此，基于读取的方法可以被称为基于存储器的命令路径。基于存储器的命令路径可以允许向NIC进行大规模传输并促进主机设备内部带宽的高效带宽利用。然而，基于存储器的命令路径可能具有较高的命令传输时延，因此可能要多次访问接口系统(或处理器接口)才能存取命令。
为了以低时延传输命令，主机设备可以将与少量数据相关联的命令传输到NIC的内部命令缓冲区。在一些实施例中，主机设备的处理器可以在NIC的内部缓冲区中进行写入。这种基于写入的方法可以提供低时延的数据传输。因此，基于写入的方法可以被称为低时延命令路径。然而，由于NIC的内部缓冲区的容量可能有限，因此低时延命令路径可能会限制传输量。
为了解决这一问题，NIC可以将两种方法结合起来，以促进低时延的高效传输速率。主机设备可以维持主机设备的存储器中用于相应命令流的命令队列(例如，基于流量分类)。如果应用程序为NIC发出命令，则所述命令可以存储在对应的命令队列中。然后，主机设备可以通过使写指针前进(advance)来向NIC通知新命令。由于任何应用程序都可以写入命令队列，因此这种方法可以不受应用程序的约束。然后，NIC可以向命令队列发出读操作并使所述队列的预取指针前进。当返回数据时，NIC可以处理命令并使读指针前进。
然而，如果命令队列可能为空(即，已知先前写入命令队列的任何命令已经或可能已经被NIC处理)，则主机设备可以将命令插入到NIC的内部缓冲区中。NIC可以维持用于主机设备的相应命令队列的内部缓冲区。缓冲区可以具有固定大小，可以托管有限数量的命令。由于命令可以直接写入内部缓冲区中，因此NIC可以避免经由内部通信通道(例如，快速外围部件互连(PCIe)通道)进行往返数据交换。通过这种方式，NIC可以降低向NIC发出命令的时延。通过在命令路径之间进行动态切换，主机设备可以选择可以高效传输命令的命令路径。
本发明的一个实施例提供了一种NIC，所述NIC可以配备有主机接口、仲裁逻辑块和命令管理逻辑块。在操作期间，所述主机接口可以将所述NIC耦接到主机设备。所述仲裁逻辑块可以选择所述主机设备的命令队列来获得命令。所述命令管理逻辑块可以经由所述主机接口接收所述命令，并确定与所述命令队列相关联的内部缓冲区是否包含命令。如果所述内部缓冲区包含所述命令，则所述命令管理逻辑块可以从所述内部缓冲区获得所述命令。另一方面，如果所述内部缓冲区为空，则所述命令管理逻辑块可以经由所述主机接口从所述命令队列中获得所述命令。
在本实施例的变体中，所述命令管理逻辑块可以为所述主机设备提供以下一项或多项：(i)与所述内部缓冲区相关联的处理信息；以及(ii)包括所述命令队列的读指针的状态信息。
在本实施例的变体中，所述命令管理逻辑块可以基于所述命令队列的写指针的前进 (advancement)来确定所述命令队列具有新命令。
在本实施例的变体中，所述仲裁逻辑块可以从所述主机设备的存储器中的多个命令队列中选择所述命令队列。
在进一步变体中，所述NIC还可以包括用于相应命令队列的对应内部缓冲区。
在本实施例的变体中，所述命令管理逻辑块可以在确定以下一项或多项后丢弃从所述主机接口接收到的并以所述内部缓冲区为目的地的新命令：(i)所述内部缓冲区的容量不足以容纳所述新命令；以及(ii)所述命令队列不为空。
在本实施例的变体中，响应于接收到所述新命令，所述命令管理逻辑块可以使所述命令队列的写指针前进，从而确定所述命令队列中存在命令。
在本实施例的变体中，所述命令管理逻辑块可以在请求所述命令后使所述命令队列的预取指针前进，并在接收到与所述命令相关联的数据后使所述命令队列的读指针前进。
在本实施例的变体中，所述主机接口可以是快速外围部件互连(PCIe)接口。所述命令管理逻辑块于是可以基于PCIe读取从所述命令队列中获得所述命令。
在本实施例的变体中，所述命令可以包括RDMA命令。
本发明的一个实施例提供了一种计算机系统，所述计算机系统可以包括存储器设备、主机接口和命令管理系统。所述存储器设备可以存储命令队列。所述主机接口可以使NIC 耦接，所述NIC可以维持与所述命令队列相关联的内部缓冲区。在操作期间，所述系统可以将命令写入所述命令队列，并基于所述命令队列的状态来确定所述内部缓冲区是否可以接受所述命令。如果所述内部缓冲区可以接受所述命令，则所述系统可以经由所述主机接口将所述命令写入所述内部缓冲区中。另一方面，如果所述内部缓冲区不能接受所述命令，则所述系统可以经由所述主机接口通知所述NIC所述命令已被写入所述命令队列中。
在本实施例的变体中，所述命令队列的状态指示所述命令队列是否为空。
在本实施例的变体中，所述系统可以获得与所述内部缓冲区的性能相关联的统计数据，并基于所获得的统计数据来推测性地确定预期所述命令队列是否为空。
在本实施例的变体中，通知所述NIC可以包括使所述命令队列的写指针前进。
在本实施例的变体中，所述存储器设备可以存储多个命令队列。
在本实施例的变体中，所述系统可以基于允许写入所述命令队列的粒度将多个命令写入所述命令队列中。随后，所述系统可以根据所述粒度来使所述命令队列的写指针前进。
在本实施例的变体中，如果所述内部缓冲区不能接受所述命令，则所述系统可以选择所述命令队列中的所述命令作为备份命令。
在进一步变体中，如果所述命令已经在所述内部缓冲区处被丢弃，则NIC可以经由所述主机接口从所述命令队列中获得所述命令。
在本实施例的变体中，所述主机接口可以是PCIe接口。然后，所述系统可以基于PCIe写入来将所述命令写入所述内部缓冲区中。
在本实施例的变体中，所述命令可以包括RDMA命令。
在本公开中，结合图1的描述与网络架构有关，并且结合图2A及之后的描述提供了关于与支持高效命令管理的NIC相关联的架构和操作的更多细节。
图1示出了示例性网络。在该示例中，交换机网络100(也可以被称为“交换机结构”)可以包括交换机102、104、106、108和110。每个交换机在交换机结构100内可以具有唯一的地址或ID。各种类型的设备和网络可以耦接到交换机结构。例如，存储阵列112可以经由交换机110耦接到交换机结构100；基于无限带宽(IB)的HPC网络114 可以经由交换机108耦接到交换机结构100；诸如主机116等多个终端主机可以经由交换机104耦接到交换机结构100；并且IP/以太网网络118可以经由交换机102耦接到交换机结构100。通常，交换机可以具有边缘端口和结构端口。边缘端口可以耦接到结构外部的设备。结构端口可以经由结构链路耦接到结构内的另一个交换机。通常，流量可以经由边缘交换机的入口端口注入到交换机结构100中，并经由另一个(或同一个)边缘交换机的出口端口离开交换机结构100。入口链路可以将边缘设备(例如，HPC终端主机)的NIC耦接到边缘交换机的入口边缘端口。然后，交换机结构100可以将流量传输到出口边缘交换机，所述出口边缘交换机进而可以经由另一个NIC将流量传递到目的地边缘设备。
示例性NIC架构
图2A示出了具有多个NIC的示例性NIC芯片。参考图1中的示例，NIC芯片200 可以是为主机116设计的定制专用集成电路(ASIC)以与交换机结构100一起工作。在该示例中，芯片200可以提供两个独立的NIC 202和204。芯片200的各个NIC可以配备有主机接口(HI)(例如，用于连接到主机处理器的接口)和一个高速网络接口(HNI)，以用于与耦接到图1的交换机结构100的链路进行通信。例如，NIC 202可以包括HI 210 和HNI 220，并且NIC 204可以包括HI 211和HNI 221。
在一些实施例中，HI 210可以是外围部件互连(PCI)接口或快速外围部件互连(PCIe) 接口。HI 210可以经由主机连接201耦接到主机，所述主机连接可以包括N个(例如，在一些芯片中N可以是16)PCIe Gen 4通道，能够以高达每通道25Gbps的信令速率进行操作。HNI 210可以促进高速网络连接203，这样可以与图1的交换机结构100中的链路进行通信。HNI 210可以使用M个(例如，在一些芯片中M可以是4)全双工串行通道以100Gbps或200Gbps的总速率进行操作。M个通道中的每一个都可以分别基于非归零(NRZ)调制或脉冲幅度调制4(PAM4)以25Gbps或50Gbps的速率进行操作。 HNI 220可以支持电气和电子工程师协会(IEEE)802.3基于以太网的协议、以及为更高速率的小消息提供支持的增强型帧格式。
NIC 202可以支持以下一项或多项：基于消息传递接口(MPI)的点对点消息传递、远程存储器存取(RMA)操作、批量数据集体操作的卸载和进度、以及以太网包处理。当主机发出MPI消息时，NIC 202可以匹配对应的消息类型。此外，NIC 202可以针对 MPI实施紧迫协议和约定协议两者，从而从主机卸载对应的操作。
此外，NIC 202所支持的RMA操作可以包括PUT、GET和原子存储器操作(AMO)。 NIC202可以提供可靠的传输。例如，如果NIC 202是源NIC，则NIC 202可以为幂等操作提供重试机制。此外，基于连接的错误检测和重试机制可以用于可能操纵目标状态的有序操作。NIC202的硬件可以维持重试机制所需的状态。通过这种方式，NIC 202可以减轻主机(例如，软件)上的负担。决定重试机制的策略可以由主机通过软件来指定，从而确保NIC 202的灵活性。
此外，NIC 202可以促进触发操作、通用卸载机制以及依赖性操作序列(诸如批量数据集体)的进度。NIC 202可以支持应用编程接口(API)(例如，libfabric API)，以促进由图1的交换机结构100向在主机116上运行的应用程序提供结构通信服务。NIC 202 还可以支持低级别网络编程接口，诸如Portals API。另外，NIC 202可以提供高效的以太网包处理，所述以太网包处理在NIC 202为发送方时可以包括有效发射，在NIC 202为目标时可以包括流操纵，以及校验和计算。此外，NIC 202可以支持虚拟化(例如，使用容器或虚拟机)。
图2B示出了NIC的示例性架构。在NIC 202中，HNI 220的端口宏可以促进低级别以太网操作，诸如物理编码子层(PCS)和媒体存取控制(MAC)。另外，NIC 202可以提供对链路层重试(LLR)的支持。传入包可以由解析器228解析并存储在缓冲区229 中。缓冲区229可以是PFC缓冲区，所述PFC缓冲区被供应用于缓冲阈值量(例如，一微秒)的延迟带宽。HNI 220还可以包括分别用于管理传出包和传入包的控制发射单元 224和控制接收单元226。
NIC 202可以包括命令队列(CQ)单元230。CQ单元230可以负责获取并发出主机端命令。CQ单元230可以包括命令队列232和调度器234。命令队列232可以包括分别用于启动器命令(PUT、GET等)和目标命令(Append、Search等)的两组独立的队列。命令队列232可以被实施为在NIC 202的存储器中维持的循环缓冲区。在主机上运行的应用程序可以直接写入命令队列232。调度器234可以包括分别用于启动器命令和目标命令的两个单独的调度器。启动器命令基于散列函数被分类到流队列236中。流队列236 之一可以分配到唯一的流。此外，CQ单元230可以进一步包括触发操作模块(或逻辑块) 238，所述触发操作模块负责对触发命令进行排队和分派。
出站传输引擎(OXE)240可以从流队列236中拉取命令，以对其进行处理以供分派。OXE 240可以包括地址转换请求单元(ATRU)244，所述地址转换请求单元可以将地址转换请求发送到地址转换单元(ATU)212。ATU 212可以代表不同的引擎提供虚拟到物理地址的转换，所述不同的引擎诸如OXE 240、入站传输引擎(IXE)250和事件引擎(EE)216。ATU 212可以维持较大的转换缓存214。ATU 212既可以自己执行转换，也可以使用基于主机的地址转换服务(ATS)执行转换。OXE 240还可以包括消息切分单元(MCU)246，所述消息切分单元可以将大的消息分割为与最大发射单元(MTU)相对应的大小的包。MCU 246可以包括多个MCU模块。当MCU模块可用时，MCU模块可以从指派的流队列中获得下一个命令。接收到的数据可以写入数据缓冲区242中。然后，MCU模块可以将包报头、对应的流量分类和包大小发送到流量整形器248。整形器 248可以确定由MCU 246提出的哪些请求可以进入网络。
随后，可以将所选择的包发送到包和连接跟踪(PCT)270。PCT 270可以将包存储在队列274中。PCT 270还可以维持出站命令的状态信息，并在返回响应时更新状态信息。PCT270还可以维持包状态信息(例如，允许将响应与请求匹配)、消息状态信息 (例如，跟踪多包消息的进度)、启动器完成状态信息、以及重试状态信息(例如，维持在请求或响应丢失时对命令进行重试所需的信息)。如果在阈值时间内未返回响应，则可以从重试缓冲区272中取得对应的命令。PCT 270可以促进分别基于源表276和目标表278对启动器命令和目标命令进行连接管理。例如，PCT 270可以更新其源表276，以跟踪可靠地传送包和消息完成通知所需的状态。PCT 270可以将传出包转发到HNI 220，所述HNI将包存储在出站队列222中。
NIC 202还可以包括IXE 250，所述IXE在NIC 202为目标或目的地时提供包处理。IXE 250可以从HNI 220获得传入包。解析器256可以解析传入包并将对应的包信息传递到列表处理引擎(LPE)264或消息状态表(MST)266以进行匹配。LPE 264可以将传入消息与缓冲区进行匹配。LPE 264可以确定每个消息要使用的缓冲区和起始地址。 LPE 264还可以管理用于表示缓冲区的列表条目池262、以及意外消息。MST 266可以存储匹配结果和生成目标端完成事件所需的信息。事件可以是用于在NIC 202的元件之间进行传送的内部控制消息。MST 266可以由不受限制的操作使用，包括多包PUT命令以及单包和多包GET命令。
随后，解析器256可以将包存储在包缓冲区254中。IXE 250可以获得匹配结果以进行冲突检查。然后，DMA写入和AMO模块252可以向存储器发出由写入和AMO操作生成的更新。如果包包括生成目标端存储器读操作的命令(例如，GET请求)，则可以将所述包传递到OXE240。NIC 202还可以包括EE 216，所述EE可以从NIC 202中的其他模块或单元接收生成事件通知的请求。事件通知可以指定生成完整事件或计数事件。 EE 216可以管理位于主机处理器存储器内的事件队列，其将完整事件写入所述主机处理器存储器。EE 216可以将计数事件转发到CQ单元230。
NIC中的动态命令管理
图3A示出了NIC中的示例性动态命令管理过程。在该示例中，主机设备300可以配备有NIC 330。设备300可以包括处理器302、存储器设备304和接口系统306。NIC 330的HI332可以耦接到设备300的接口系统306。在一些实施例中，HI 332可以是PCIe接口，并且接口系统306可以是为HI 332提供插槽的PCIe系统。NIC 330还可以包括命令队列单元334，以用于管理来自设备300的传入命令，如结合图2A所描述的。
在操作期间，设备300可以发出用于操作(例如，RDMA操作)的命令320。为了传输命令，主机300可以生成命令描述符(例如，DMA描述符)并将命令320传输到 NIC 330。如果命令320是大量命令之一，则设备300可以将命令320存储在存储器设备 304中的命令队列312中。当NIC 330具有可用于下一个命令的资源时，NIC 330可以向设备300请求命令。如果命令320是下一个命令，则处理器302可以经由HI 332将命令 320传输到NIC 330。这里，NIC330可以从主机300的存储器设备304读取命令。这种基于存储器的命令路径可以允许将大规模命令传输到NIC 300，从而促进接口系统306的高效带宽利用。
然而，基于存储器的命令路径可能具有较高的命令传输时延，因此可能要多次访问接口系统306才能存取命令320。可替代地，如果命令320与少量数据(例如，在阈值内)相关联，则设备300可以将命令320传输到NIC 330中的内部命令缓冲区314。在一些实施例中，处理器302可以在内部缓冲区314中进行写入。这种低时延命令路径可以提供低时延的数据传输。然而，由于内部缓冲区314的容量可能有限，因此低时延命令路径可能会限制传输量。
为了解决这一问题，NIC 330可以将两种命令路径结合起来，以促进低时延的高效传输速率。此外，设备300可以维持存储器设备304中的多个命令队列，每个命令队列用于相应的命令流。命令队列312可以是命令队列之一。当在设备300上运行的应用程序向NIC 330发出命令320时，命令320可以存储在命令队列312中。然后，设备300可以通过使命令队列312的写指针前进来向NIC 330通知命令320。然后，NIC 330可以经由HI 332向命令队列312发出读操作并使命令队列312的预取指针前进。当为命令320 返回数据时，NIC 330可以处理命令320并使命令队列312的读指针前进。
然而，如果命令队列312为空，则设备300可以将命令320插入到内部缓冲区314中。NIC 330可以维持用于设备300的相应命令队列的内部缓冲区。内部缓冲区314可以由命令队列单元334管理。内部缓冲区314可以具有固定大小，可以存储有限数量的命令。由于命令320可以直接写入内部缓冲区314中，因此NIC 330可以避免经由接口通道306与处理器302进行往返数据交换。通过这种方式，内部缓冲区314可以降低向NIC 330发出命令的时延。通过在命令队列312与内部缓冲区314之间进行动态切换，主机 300可以选择可以将命令高效地传输到NIC 330的命令路径。
在一些实施例中，在主机300的操作系统上运行的NIC 330的设备驱动程序308可以选择命令路径。驱动程序308可以针对相应的命令(即，逐个命令地)动态地确定是使用基于存储器的命令路径还是使用低时延命令路径。驱动程序308可以基于来自NIC 330的信息来确定命令队列312和内部缓冲区314中是否存在未完成命令。例如，NIC 330可以向驱动程序308提供命令队列312的一个或多个指针的当前位置。此外，NIC 330还可以提供关于如何有效使用内部缓冲区314的统计数据。驱动程序308可以确定是否选择内部缓冲区314来传输下一个命令。
此外，驱动程序308可以推测性地确定内部缓冲区314应当具有可用容量。基于所述确定，如果命令队列312的当前状态和内部缓冲区314满足选择标准，则驱动程序308 可以选择内部缓冲区314来发出命令。否则，驱动程序308可以使用命令队列312。相应地，如果可能的话，NIC 330可以从内部缓冲区314获得命令。否则，NIC 330可以从命令队列312中获得命令。
图3B示出了用于促进NIC中的动态命令管理的示例性队列。命令队列312上的操作可以基于循环缓冲区的操作。在操作期间，如果设备300确定应当向命令队列312发出命令362，则设备300可以格式化命令362。然后，设备300可以将命令362存储在命令队列312中的由写指针352指示的位置处。然后，设备300可以使写指针352前进到下一个存储器位置。使写指针352前进可以触发对NIC 330的通知(或“门铃”)。设备300可以在使写指针352前进之前将多个命令写入命令队列312。在一些实施例中，使写指针352前进的粒度可以在设备300处(例如，由用户)进行配置。
基于触发，NIC 330可以确定命令队列312具有新命令。如果NIC 330选择命令队列312进行处理(例如，基于命令队列之间的仲裁过程)，则NIC 330可以从命令队列312 中读取由预取指针354指示的命令并使预取指针354前进。例如，如果预取指针354表示命令362的位置，则NIC 330可以从命令队列312中读取命令362。当向NIC 330返回与命令362相关联的数据时，NIC 330可以处理命令362并使读指针356前进。
在一些实施例中，使读指针356前进可以包括根据队列特定策略来更新读指针356的应用可见副本。NIC 330可以继续从命令队列312中读取命令，直到NIC 330的处理资源(例如，结合图2B描述的执行单元)具有足够的命令来执行。如果预取指针354到达写指针352(例如，如果命令队列312为空)，则NIC 330可以停止读取命令。由于命令队列312可以是具有固定大小的循环队列，因此如果写指针352到达读指针356，则设备 330可以暂停向命令队列312发出命令。写指针352到达读指针356可以指示命令队列 312已满并且不能接受新命令。指针352、354和356可以指示在命令队列312中的定位或位置。例如，指针352、354和356可以表示命令队列312的索引(例如，数组索引)，或者表示指示存储器位置的存储器指针。
另一方面，如果设备300确定或推测命令队列312为空，则设备300可以确定应当向内部缓冲区314发出命令364。然后，设备300可以格式化命令364并将命令364存储在命令队列312中的由写指针352指示的位置处。然而，如果设备300确定或推测内部缓冲区314具有足够的容量来容纳命令364，则设备300可以不使写指针352前进，而是可以将命令364写入内部缓冲区364中。设备300可以使用基于PCIe的写操作来执行写操作。可以在对命令队列312和内部缓冲区314的相应写入之间使用写存储器屏障，诸如SFENCE指令。
在检测到内部缓冲区314中的写操作时，NIC 330可以使写指针358前进。当NIC330选择命令队列312来处理命令时，NIC 330确定内部缓冲区314存储有命令。相应地，NIC330从内部缓冲区314进行读取，而不是向命令队列312发出基于接口的读取 (诸如PCIe读取)。在从内部缓冲区314获得命令364后，NIC 330可以使预取指针354 前进。
应当注意，对内部缓冲区314的写操作可以乱序到达。此外，写操作的粒度可以小于某些命令的粒度。当内部缓冲区314的块内的写操作已经完成时，NIC 330可以跟踪对内部缓冲区314的部分写操作并使写指针352前进。如果内部缓冲区314仍然包含前一写操作的数据，或者在发出操作364时命令队列312尚不为空(即，预取指针354尚未等于写指针352)，则NIC 330可以丢弃命令364。于是，命令队列312中的命令364可以作为备份命令进行操作。当NIC 330具有可用于执行另一个命令的资源时，NIC 330可以从命令队列312中获得下一个命令。
图4A示出了NIC中用于处理命令的动态队列选择过程的流程图。在操作期间，NIC的主机设备可以获得命令队列的最后已知状态(操作402)。然后，设备可以确定命令队列是否为空(操作404)。如果命令队列不为空，则设备可以确定推测向内部缓冲区发出命令是否是有益的(操作406)。例如，如果命令队列可能为空，则推测向内部缓冲区发出命令可能是有益的。
如果推测发出命令不是有益的，则设备可以维持基于存储器的命令路径(操作408) 并继续获得命令队列的状态(操作402)。另一方面，如果推测命令队列为空(操作404)或者发出命令是有益的(操作406)，则设备可以切换到低时延命令路径(操作410)。应当注意，基于存储器的命令路径可以是设备的默认选项。除非切换到低时延命令路径，否则设备可以继续使用基于存储器的命令路径以将命令传输到NIC。
图4B示出了主机设备的动态命令管理过程的流程图。在操作期间，设备可以生成命令(例如，以设备的NIC可接受的格式)，将所述命令插入到与所述命令相关联的命令队列中(操作432)，并使设备的写指针副本(操作434)前进。然后，设备可以检查是否选择了低时延命令路径(操作436)。如果选择了低时延命令路径，则设备还可以将命令插入到与命令队列相关联的NIC内部缓冲区中(操作438)。
如果未选择低时延命令路径(操作434)，则设备可以使NIC中的写指针(操作440)前进。设备可以检查设备的写指针副本是否已经到达读指针(操作442)。如果写指针尚未到达读指针，则设备可以继续生成命令并将所述命令插入到与所述命令相关联的命令队列中(操作432)。然而，如果写指针已经到达读指针，则命令队列可能已满，并且设备可以避免发出更多命令(操作444)。
图4C示出了NIC中基于存储器的命令路径的动态命令管理过程的流程图。在操作期间，NIC可以选择命令队列来获得命令(例如，基于仲裁过程)(操作452)并检查对应的内部缓冲区是否包含命令(操作454)。如果内部缓冲区不包含命令，则NIC可以确定命令队列中是否存在命令(操作456)。如果命令队列中存在命令，则NIC可以向命令队列请求命令并使预取指针(操作456)前进。
然后，NIC可以等待返回所请求的命令(操作460)。另一方面，如果内部缓冲区包含命令，则NIC可以从与命令队列相关联的内部缓冲区获得命令并使预取指针(操作464) 前进。在获得命令(操作460或464)后，NIC可以使读指针(操作462)前进。
图4D示出了NIC中低时延命令路径的命令管理过程的流程图。在操作期间，NIC可以从主机设备接收命令(操作472)并确定命令队列是否为空(操作474)。如果命令队列为空，则NIC可以确定内部缓冲区是否有可用的容量来容纳接收到的命令(操作476)。如果内部缓冲区具有可用的容量，则NIC可以将命令插入到内部缓冲区中(操作478) 并使写指针的本地副本(即，NIC的副本)前进(操作480)。另一方面，如果命令队列不为空(操作474)或者内部缓冲区不具有可用容量(操作476)，则NIC可以继续使用基于存储器的命令路径(操作482)。
示例性计算机系统
图5示出了配备有促进动态命令管理的NIC的示例性计算机系统。计算机系统550包括处理器552、存储器设备554和存储设备556。存储器设备554可以包括易失性存储器设备(例如，双列直插式存储器模块(DIMM))。此外，计算机系统550可以耦接到键盘562、指向设备564和显示设备566。存储设备556可以存储操作系统570。应用程序572可以在操作系统570上操作。
计算机系统550可以配备有使促进高效命令管理的NIC 520耦接的主机接口。NIC520可以向计算机系统550提供一个或多个HNI。NIC 520可以经由HNI之一耦接到交换机502。NIC 520可以包括命令逻辑块530，如结合图2B和图3所描述的。命令逻辑块530可以包括检索逻辑块532和执行逻辑块534。检索逻辑块532可以经由HI向计算机系统550提供如命令逻辑块530所知的与命令队列560的状态相关联的信息。
在操作系统570上运行的NIC 520的设备驱动程序580可以基于所提供的信息来选择命令路径。驱动程序580可以基于存储器设备554中的命令队列560的当前状态动态地确定是使用基于存储器的命令路径还是使用低时延命令路径。此外，驱动程序580可以推测性地确定命令队列560可能为空并且内部缓冲区536应当具有可用容量。相应地，如果可能的话，NIC 520可以从内部缓冲区536获得命令。否则，NIC 520可以从命令队列560中获得命令。
检索逻辑块532可以确定NIC 220的内部缓冲区536是否包含命令。如果内部缓冲区536包含命令，则检索逻辑块532可以从内部缓冲区536获得所述命令。另一方面，如果内部缓冲区536不包含命令，则检索逻辑块532可以从存储器设备554中的命令队列560中获得命令。在任一种情况下，检索模块532都可以使预取指针前进。执行逻辑块534可以执行命令。然后，执行逻辑块534可以使读指针前进。
总之，本公开描述了一种促进高效命令管理的NIC。所述NIC可以配备有主机接口、仲裁逻辑块和命令管理逻辑块。在操作期间，所述主机接口可以将所述NIC耦接到主机设备。所述仲裁逻辑块可以选择所述主机设备的命令队列来获得命令。所述命令管理逻辑块可以确定与所述命令队列相关联的内部缓冲区是否包含命令。如果所述内部缓冲区包含所述命令，则所述命令管理逻辑块可以从所述内部缓冲区获得所述命令。另一方面，如果所述内部缓冲区为空，则所述命令管理逻辑块可以经由所述主机接口从所述命令队列中获得所述命令。
上述方法和过程可以由硬件逻辑块、模块或装置来执行。硬件逻辑块、模块、逻辑块或装置可以包括但不限于专用集成电路(ASIC)芯片、现场可编程门阵列(FPGA)、在特定时间执行代码的专用或共享处理器、以及现在已知或以后开发的其他可编程逻辑设备。硬件逻辑块、模块或装置在被激活时执行其内包括的方法和过程。
本文描述的方法和过程也可以体现为代码或数据，所述代码或数据可以存储在存储设备或计算机可读存储介质中。当处理器读取并执行所存储的代码或数据时，处理器可以执行这些方法和过程。
本发明的实施例的前述描述是仅出于说明和描述的目的而呈现的。所述描述并非旨在是穷举的或将本发明限制为所公开的形式。相应地，对于本领域普通技术人员而言，许多的修改和变化将是显而易见的。另外，以上公开内容并非旨在限制本发明。本发明的范围由所附权利要求限定。

Claims (20)

1.一种网络接口控制器(NIC)，包括：
主机接口，所述主机接口使主机设备耦接；
仲裁逻辑块，所述仲裁逻辑块用于选择所述主机设备的命令队列来获得命令；以及
命令管理逻辑块，所述命令管理逻辑块用于：
经由所述主机接口接收所述命令；
确定与所述命令队列相关联的内部缓冲区是否包含命令；
响应于确定所述内部缓冲区包含所述命令，从所述内部缓冲区获得所述命令；以及
响应于确定所述内部缓冲区为空，经由所述主机接口从所述命令队列中获得所述命令。
2.如权利要求1所述的网络接口控制器，其中，所述命令管理逻辑块进一步用于为所述主机设备提供如下中的一者或多者：
与所述命令队列相关联的处理信息；以及
包括所述命令队列的读指针的状态信息。
3.如权利要求1所述的网络接口控制器，其中，所述命令管理逻辑块进一步用于基于所述命令队列的写指针的前进来确定所述命令队列具有新命令。
4.如权利要求1所述的网络接口控制器，其中，所述仲裁逻辑块进一步用于从所述主机设备的存储器设备中的多个命令队列中选择所述命令队列。
5.如权利要求4所述的网络接口控制器，进一步包括用于相应命令队列的对应内部缓冲区。
6.如权利要求1所述的网络接口控制器，其中，所述命令管理逻辑块进一步用于响应于确定如下中的一者或多者而丢弃从所述主机接口接收到的并以所述内部缓冲区为目的地的新命令：
所述内部缓冲区的容量不足以容纳所述新命令；以及
所述命令队列不为空。
7.如权利要求6所述的网络接口控制器，其中，响应于接收到所述新命令，所述命令管理逻辑块进一步用于使所述命令队列的写指针前进，从而确定所述命令队列中存在命令。
8.如权利要求1所述的网络接口控制器，其中，所述命令管理逻辑块用于：
响应于请求所述命令而使所述命令队列的预取指针前进；以及
响应于接收到与所述命令相关联的数据而使所述命令队列的读指针前进。
9.如权利要求1所述的网络接口控制器，其中，所述主机接口是快速外围部件互连(PCIe)接口；并且
其中，所述命令管理逻辑块用于基于PCIe读取从所述命令队列中获得所述命令。
10.如权利要求1所述的网络接口控制器，其中，所述命令包括远程直接存储器存取(RDMA)命令。
11.一种用于促进命令管理系统的计算机系统，所述计算机系统包括：
处理器；
存储器设备，所述存储器设备存储命令队列；
主机接口，所述主机接口用于使网络接口控制器(NIC)耦接，所述网络接口控制器维持与所述命令队列相关联的内部缓冲区；以及
存储设备，所述存储设备存储指令，所述指令当由所述处理器执行时使所述处理器执行方法，所述方法包括：
将命令写入所述命令队列；
基于所述命令队列的状态来确定所述内部缓冲区是否能够接受所述命令；
响应于确定所述内部缓冲区能够接受所述命令，经由所述主机接口将所述命令写入所述内部缓冲区中；以及
响应于确定所述内部缓冲区不能接受所述命令，经由所述主机接口通知所述NIC所述命令已被写入所述命令队列中。
12.如权利要求11所述的计算机系统，其中，所述命令队列的状态指示所述命令队列是否为空。
13.如权利要求11所述的计算机系统，其中，所述方法进一步包括：
获得与所述内部缓冲区的性能相关联的统计数据；以及
基于所获得的统计数据来推测性地确定所述命令队列是否预期为空。
14.如权利要求11所述的计算机系统，其中，通知所述NIC进一步包括使所述命令队列的写指针前进。
15.如权利要求11所述的计算机系统，其中，所述存储器设备用于存储多个命令队列。
16.如权利要求11所述的计算机系统，其中，所述方法进一步包括：
基于允许写入所述命令队列的粒度将多个命令写入所述命令队列中；以及
根据所述粒度来使所述命令队列的写指针前进。
17.如权利要求11所述的计算机系统，其中，所述方法进一步包括：响应于确定所述内部缓冲区不能接受所述命令而选择所述命令队列中的所述命令作为备份命令。
18.如权利要求17所述的计算机系统，
其中，所述NIC响应于确定所述命令已经在所述内部缓冲区处被丢弃而经由所述主机接口从所述命令队列中获得所述命令。
19.如权利要求11所述的计算机系统，其中，所述主机接口是快速外围部件互连(PCIe)接口；并且
其中，所述命令基于PCIe写入被写入所述内部缓冲区中。
20.如权利要求11所述的计算机系统，其中，所述命令包括远程直接存储器存取(RDMA)命令。
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