CN113809003A - 包括相对低的电阻率的芯的互连导线 - Google Patents
包括相对低的电阻率的芯的互连导线 Download PDFInfo
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- CN113809003A CN113809003A CN202111073470.7A CN202111073470A CN113809003A CN 113809003 A CN113809003 A CN 113809003A CN 202111073470 A CN202111073470 A CN 202111073470A CN 113809003 A CN113809003 A CN 113809003A
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Abstract
本发明描述了一种电介质层和形成所述电介质层的方法。在电介质层中限定了开口,并且在所述开口内沉积了导线,其中,所述导线包括被护套材料包围的芯材料,其中,所述护套材料呈现出第一电阻率ρ1,并且所述芯材料呈现出第二电阻率ρ2,并且ρ2小于ρ1。
Description
本申请为分案申请,其原申请是于2016年2月25日(国际申请日为2014年9月25日)向中国专利局提交的专利申请,申请号为201480047060.7,发明名称为“包括相对低的电阻率的芯的互连导线”。
技术领域
本公开内容涉及诸如互连线之类的导线,该导线包括嵌入在护套内的芯,并且具体而言,涉及包括呈现出与护套相比相对较低的电阻率的芯的导线。
背景技术
随着集成电路特征按比例缩小并且密度增大,影响所观察到的电阻的诸如电阻率之类的材料性质会呈现出相对更显著的影响。例如,随着特征尺寸的减小,互连线延迟可以超过门延迟,并且形成总器件延迟的相对大的部分。互连线延迟被理解为至少部分地由电阻-电容延迟引起。电阻-电容延迟或RC延迟被理解为随电阻变化并随绝缘体电容变化的信号传播的延迟,所述电阻部分取决于金属导线成分的电阻率,所述绝缘体电容部分取决于层间电介质的电容率。用于减少RC延迟的现有解决方案包括导线几何形状的优化。
此外,集成电路的可靠性受随着特征尺寸降低和密度增大而增大的若干应力的影响。这些应力包括电应力、热应力、机械应力以及环境应力。电迁移是降低半导体可靠性、导致互连线故障、并且随着特征尺寸减小和功率密度增大而变得相对更显著的现象的示例。电迁移被理解为由于导体中离子的运动而引起的材料的传输。电迁移会导致在互连线中形成小丘(hillock)或孔隙,并且最终导致故障。
为了减少电迁移和其它应力引起的故障,难熔金属已经用于互连线制造中。然而,难熔金属呈现出增大的电阻率,并且因此导致电阻增大,从而增加了电阻-电容延迟。为了进一步减少电迁移和其它应力引起的故障,已经在包含互连线的层间电介质中的开口的侧壁和底壁上沉积了扩散屏障(barrier)。扩散屏障被理解为占据互连导线的横截面面积中的一小部分(通常为20%或更少)。利用诸如氮化硅之类的绝缘体来涂覆在给定电介质层的表面处所暴露的互连线的部分。然而,这种布置会对诸如电容之类的导线性质造成负面影响。
因此,随着特征尺寸持续减小,在一些实例中,在强调各种应力(诸如导致电迁移和热机械故障的那些应力)的互连线延迟和电阻的互连线设计中仍有提升的空间。
附图说明
通过结合附图参考对本文中所述实施例的以下描述,本公开内容的上述和其它特征以及实现它们的方式可以变得更加显而易见且更好理解,在附图中:
图1a示出了在层间电介质中的开口中形成的多条导线的实施例的图1b的横截面,其中,导线包括芯和护套;
图1b示出了在层间电介质中的开口中形成的多条导线的实施例的顶视图;
图2示出了在层间电介质中的开口中形成的导线的实施例的横截面,所述层间电介质具有应用于层间电介质与导线之间的开口中的扩散屏障;
图3示出了在包括芯和护套的基板中沉积导线的方法的实施例;
图4a示出了在将导线沉积在层间电介质中形成的开口中之前的层间电介质的实施例的横截面;
图4b示出了包括护套材料的第一层的共形涂层的层间电介质的实施例的横截面;
图4c示出了在对形成导线芯的材料进行沉积和回流之后的层间电介质的实施例的横截面;
图4d示出了在沉积护套材料的剩余部分之后的层间电介质的实施例的横截面;
图4e示出了在对护套材料进行平坦化从而使层间电介质的表面暴露之后的层间电介质的实施例的横截面;
图5示出了具有相同直径的铜芯和钴的导线电阻与导线长度相对比的示例;
图6示出了由A)钴护套和铜芯;B)钴;以及C)铜形成的具有不同直径的导线的最大电流密度的示例;
图7示出了在包括芯和护套的层间电介质中形成的导线的实施例的横截面的透射电子显微镜图像;以及
图8示出了在包括芯和护套的层间电介质中形成的导线的实施例的横截面的电子色散光谱图像。
具体实施方式
本公开内容涉及包括形成在护套内的芯的互连导线的形成。芯呈现出与护套相比相对较低的电阻率,这提供了扩散屏障和抗散射性质(即,芯表面处的电子散射)。如上所指出的,随着集成电路按比例缩小,某些材料性质(例如电阻率)呈现出相对更显著的效应。例如,互连线延迟可以超过门延迟并且形成总器件延迟的相对大的部分。互连线或互连导线(本文中也被称为导线)可以被理解为例如在集成电路上的部件之间的连接。部件包括例如:晶体管、二极管、电源、电阻器、电容器、电感器、传感器、收发器、接收器、天线等。互连线延迟被理解为至少部分地由电阻-电容延迟或RC延迟、由于互连线材料的电阻-电容效应而产生的信号延迟导致。可以通过使用较低电阻率互连线材料来减少电阻-电容延迟。另外,材料性质和电流密度影响电迁移,这被理解为是由于导体中离子的运动而引起的材料的传输。电迁移可能产生在互连线中形成的小丘(hillock)或孔隙,从而导致故障。本公开内容涉及使用本文所述的导线以及形成这种导线的方法来提供减少RC延迟和电迁移的导线。
图1a和图1b示出了包括形成在诸如层间电介质的金属化层104中的开口103中的诸如互连线之类的多条导线102的实施例。开口102具有长度、宽度、和高度并且表现为若干横截面几何形状,例如U形沟道、v形沟道等。金属化层包括电介质材料,该电介质材料被理解为是绝缘体但一旦施加电场就被极化的材料。在实施例中,电介质包括低k电介质,即,介电常数低于3.9(二氧化硅的介电常数)、包括从1.5到3.8的所有值和范围(例如1.7、1.9、2.1、2.8、2.7等)的材料。可以从中选择电介质材料的非限制性示例包括氟掺杂的二氧化硅、碳掺杂的二氧化硅、有机硅酸盐玻璃、碳氧化硅、氢化碳氧化硅、多孔二氧化硅、以及诸如聚酰亚胺、聚四氟乙烯、聚降冰片烯、苯并环丁烯、氢倍半硅氧烷和甲基倍半硅氧烷之类的有机聚合物电介质。金属化层可以具有在50nm到300nm的范围内的厚度,包括其中的所有值和范围,例如50nm到100nm、50nm到200nm等。
导线102包括包围在第二材料的护套108中的第一材料的芯106。在实施例中,金属化层104中的开口103的宽度W可以在5nm到100nm的范围内,包括其中的所有值和范围,例如10nm、20nm、25nm、30nm、35nm、40nm、45nm、50nm等,并且因此导线102的宽度也在该范围内。开口103的高度H可以在10nm到200nm的范围内,包括其中的所有值和范围,例如10nm、20nm、25nm、30nm、35nm、40nm、45nm、50nm等,并且因此导线102的高度也在该范围内。导线的长度L(见图1b)的范围可以从亚微米到几微米,包括从0.01μm到5.0μm的所有值和范围,例如0.05μm、0.1μm、1μm、2μm等。
尽管导线几何形状被示出为通常为正方形或矩形并且具有相对尖的角,但是导线的几何形状可以是圆形的、椭圆形的,或者呈现出半径变化的圆角。此外,芯的几何形状可以与护套的几何形状不同。例如,芯可以是矩形而护套可以是正方形的,或者芯可以是正方形的而护套是矩形的。如果护套和芯呈现出类似的几何形状,护套几何形状的长宽比(aspect ratio)可以与芯几何形状的长宽比相同或不同。另外,芯相对于导线的横截面可以是居中的或者有偏移的。
如图所示,护套108包围芯材料106的外部表面110,从而接触导线芯106的侧面。护套108存在于金属化层104与芯106之间,以及存在于导线102的上表面114处(其中,该特定金属化层的电介质材料不存在)。在实施例中,护套108通过护套和芯材料的内扩散或者由于护套与芯材料之间的化学键合来接合到芯106的外表面110。护套108占据导线102的体积的25%到75%,包括在其中的所有值和范围,例如导线102的体积的50%至75%。并且芯占据导线102的体积的25%至75%,包括其中的所有值和范围,例如导线102的体积的25%到50%。
在实施例中,护套108占据导线102的横截面面积的25%或更多,包括从25%到75%的所有值和范围,并且具体而言为50%到75%等。垂直于导线的长度L或者垂直于导线的呈现出如图1a和图1b中所示的最大尺寸的其它方面(长度、宽度或高度)来测量横截面面积。芯106占据导线102的横截面面积的75%或更小,包括从25%到75%的所有值和范围,并且具体而言为25%到50%。此外,如图所示,芯106设在金属化层104的台面或上表面112下方,其中,距离D存在于芯106的上表面114与金属化层104的上表面112之间。距离D可以高达导线102的整个高度H的40%,包括从1%到40%、5%到30%、10%到20%等的所有值和范围,其中,D=x*H,其中,x是从0.01到0.40。
在实施例中,芯材料呈现出4.0μΩ·cm或更小的电阻率ρ1,包括从1.0μΩ·cm到4.0μΩ·cm的所有值和范围,例如1.7、2.7等。护套材料呈现出5.0μΩ·cm或更大的电阻率ρ2,包括从5.0μΩ·cm到8.0μΩ·cm的所有值和范围。因此,形成导线芯的材料呈现出比形成导线护套的材料更低的电阻率,其中,ρ1<ρ2,ρ1是芯材料的电阻率,并且ρ2是护套材料的电阻率。芯材料还呈现出与护套材料相比相对较低的熔化温度,其中,T1<T2,T1是芯材料的熔化温度,并且T2是护套材料的熔化温度。在实施例中,T1可以比T2至少低300℃,其中,T2-X=T1,其中,x在300℃到2800℃的范围内。
例如,芯材料是金属并且包括铜、铝、金、银或包括这些元素中的一种或多种元素的合金。护套材料也是金属并且包括例如钨、钴、钌、钼或包括这些元素中的一种或多种元素的合金。在特定实施例中,芯材料包括铜或铜的合金,并且护套材料不包括铜,即,不含铜。
如图2的实施例中所示,可选的扩散屏障116设在导线102与金属化层104之间。因此,扩散屏障沉积在金属化层104中的开口103的壁120和底部122上。扩散屏障116可以被理解为是降低或防止导线材料扩散到层间电介质中的材料层。扩散屏障具有在5nm到10nm的范围内(包括其中的所有值和范围)的厚度。扩散屏障材料的示例包括下列各项中的一种或多种:钽、氮化钽、钴合金、以及氮化钨。在实施例中,该材料呈现出比护套材料更高的电阻率,例如从10μΩ·cm到更大,例如在10μΩ·cm到300μΩ·cm的范围内。如上文所指出的,护套108包围导线102横截面的整个外围,然而扩散屏障116设在与电介质接触的导线的侧面(包括开口103的壁120和底部122)上。此外,扩散屏障116占据开口103的横截面面积的10%或更少,包括其中的所有值和范围,例如1%到5%等。
图3示出了提供本文中所述的导线的方法的实施例,并且图4a到图4e示出了随着在图3中所示的方法而进行的导线生长。参考图3,方法300包括对诸如层间电介质的金属化层进行图案化并且在金属化层中形成开口302。
在实施例中,图案化包括在金属化层之上沉积光致抗蚀剂。光致抗蚀剂是正性抗蚀剂或负性抗蚀剂,并且可以包括例如聚甲基丙烯酸甲酯、聚甲基戊二酰亚胺、DNQ/酚醛树脂、或SU-8(基于环氧树脂的负性抗蚀剂)。通过诸如旋涂等铸造工艺来沉积光致抗蚀剂。可以以1到10,000rmp(包括其中的所有值和范围)来执行持续1秒到10秒的范围(包括其中的所有值和范围)内的时段的旋涂。
随后通过使用光刻(例如,光学光刻、浸没式光刻、深UV光刻、极UV光刻、或其它技术)将所需图案的图像投影到光致抗蚀剂上来对光致抗蚀剂进行图案化,其中,所投影的光的波长可以高达436nm,包括从157nm到436nm的所有值和范围,例如157nm、193nm、248nm等。例如通过旋涂将诸如处于0.1N到0.3N的范围内的浓度的四甲基氢氧化铵TMAH(具有或不具有表面活性剂)等显影剂涂覆到光致抗蚀剂上,该光致抗蚀剂的部分被去除从而暴露下面的电介质层的与所需图案相互关联的区域。
在实施例中,对电介质的烘烤可以在上述步骤中的任何一个之前或之后发生。例如,可以在200℃到400℃的范围内(包括其中的所有值和范围)的温度下对金属化层进行持续30到60分钟(包括其中的所有值和范围)的预烘烤,以去除表面的水。在涂覆光致抗蚀剂之后,可以发生涂覆后(post application)烘烤,其中,蒸馏掉了光致抗蚀剂中的溶剂的至少一部分。例如,在70℃到140℃的范围内(包括其中的所有值和范围)的温度下执行持续60秒到240秒的范围内(包括其中的所有值和范围)的时段的涂覆后烘烤。在图案化之后,可以在100℃到300℃的范围内(包括其中的所有值和范围)的温度下对抗蚀剂进行持续1分钟到10分钟(包括其中的所有值和范围)的时段的硬烘烤。
对金属化层的暴露部分进行化学蚀刻,其中,去除表面的暴露部分直至获得所需的深度,从而在金属化层中形成了开口。经由诸如灰化(其中,将光致抗蚀剂暴露于氧气或氟气,氧气或氟气与光致抗蚀剂结合以形成灰)等工艺来任选地去除剩余的光致抗蚀剂。图4a示出了经图案化的金属化层104的实施例,该金属化层104包括形成在表面112中的一个或多个开口103。
再次参照图3,在将金属化层图案化之后,将形成与侧壁的底部部分和下部部分接触的护套的部分的第一金属层沉积到开口中304。在实施例中,通过共形涂覆工艺来沉积护套材料的第一层,其中,在金属化层的任何暴露的表面上(包括在金属化层中形成的任何开口的侧壁和底部上)沉积第一金属。因此,共形涂层可以被理解为被施加到金属化层的暴露表面而不仅仅是例如水平表面的涂层。在实施例中,涂层呈现出小于35%的厚度变化,这包括从1%到35%的所有值和范围,例如10%或更少、15%或更少、20%或更少、25%或更少等。共形涂覆工艺是从诸如化学气相沉积或原子层沉积之类的工艺中选择的。在化学气相沉积中,例如,在包括电介质的腔中以1到50sccm(包括其中的所有值和范围)的流速提供一种或多种反应气体。反应气体可以选自以下各项中的一项或多项:六氟化钨(有或无氢)、五氯化钼(有氢)、六羰基钼、六羰基钨、双(乙基环戊二烯基)钌(II)、双(环戊二烯基)钌(II)、双(五甲基环戊二烯基)钌(II)、十二羰基三钌、八羰基二钴、双(环戊二烯基)钴(II)、双(乙基环戊二烯基)钴(II)、双(五甲基环戊二烯基)钴(II)。反应气体可以被提供有诸如惰性气体(其可以包括例如氩气)的运载气体。
腔维持在大气压、低压(亚大气压,即1x10-1托到1x10-6托)或超高真空(即,1x10-7托到1x10-8托)下。在实施例中,腔维持在10-1到10-3托的范围内(包括其中的所有值和范围)的气压和在20℃到500℃的范围内(包括其中的所有值和范围)的温度下。在实施例中,工艺可以是等离子体辅助的,其中,在处理腔内提供电极并且该电极用于使气体电离,或者在腔的外部形成等离子体并且随后向腔提供该等离子体。在腔中,由于气体的反应而导致金属层沉积在电介质的表面上。图4b示出了包括形成金属化层的层间电介质的表面112之上(包括沿着开口103的壁120和底部122)的护套108的一部分的第一金属层的共形涂层130的金属化层104的实施例。这继而形成了第二开口或特征132,所述第二开口或特征132在进一步的步骤中容纳芯材料。
再次参照图3,在沉积护套材料的第一层从而形成护套的一部分之后,芯材料则通过包括物理气相沉积或化学气相沉积的气相沉积工艺来进行沉积306。物理气相沉积包括例如:磁控溅射、蒸发沉积或电子束沉积。可以通过以上所概述的工艺来执行化学气相沉积。
物理气相沉积的示例包括以在5sccm到100sccm的范围内(包括其中的所有值和范围)的流速来向处理腔中供应惰性气体(诸如氩气),处理腔保持在1x10-1到10-7托的范围内(包括其中的所有值和范围)的气压下。处理腔包括工件(即,电介质)和由铜或铝形成的金属源(被称为靶)。金属源通过额定值在0.1到50kW的范围内(包括其中的所有值和范围)的DC源来偏置。工件或安置工件的工作台也可以通过额定值在0.1到1.5kW的范围内(包括其中的所有值和范围)的AC源来进行偏置。由于磁体邻近于靶安置或安置在靶后面,等离子体形成在并且位于靶周围。等离子体轰击靶从而如蒸汽一样溅射出金属原子,该金属原子随后沉积在工件上。工艺持续1秒到100秒的范围内的时段,这包括其中的所有值和范围,例如5秒、10秒、30秒等,从而允许电介质层表面上的芯材料层的生长。
施加足够的芯材料,以仅仅部分地填充由沉积在开口中的第一金属层形成的第二开口或特征132,其中,用芯材料来填充每个开口103的总体积的25%至75%,在工艺结束时用护套材料来填充剩余部分。一旦芯材料沉积在该第一金属层上,就对芯材料进行回流308以使得芯材料流到金属化层的开口中并且形成回流的芯材料。为了使芯材料回流,芯材料经受或暴露于在200℃到1100℃的范围内(包括其中的所有值和范围,例如从200℃到800℃、300℃、500℃、800℃)的升高的温度,通过辐射、熔炉、灯、微波、或热气体来施加该温度。可以对芯材料进行持续1分钟到100分钟的范围内(包括其中的所有值和范围,例如30分钟、45分钟等)的时段的回流。图4c示出了在发生回流之后的芯材料的实施例。如图所示,芯106部分地填充形成在第一金属层130中的第二开口132,以使得芯106材料的上表面114位于金属化层104的表面112下方。
再次参照图3,在将芯材料沉积到金属化层上之后,在308将附加的护套材料(即,第二层)沉积到如图4d中所示的特征132的未填充部分中。在金属化层104的表面112和开口103之上形成覆盖层134,以确保特征132的填充。覆盖层可以被理解为金属化层的电介质表面上的过量的材料并且随后将被去除。
在实施例中,使用气相沉积来沉积护套金属的第二层。例如,采用化学气相沉积,化学气相沉积使用以上针对在开口中形成护套金属的第一层的共形涂层而描述的工艺;或者可以采用物理气相沉积,物理气相沉积是例如通过以上所述的工艺来向金属化层涂覆芯材料从而用以上描述的护套材料来替代靶。在特定实施例中,在对护套材料的剩余部分进行填充之前,任选地对芯导线进行干法或湿法清洁以从芯材料表面去除氧化。这可以通过利用电离气体来溅射芯材料表面或通过化学蚀刻来去除任何氧化材料来执行。
随后使金属化层平坦化310以去除覆盖层。在实施例中,使用化学机械平坦化来执行平坦化,化学机械平坦化可以被理解为利用抛光表面、研磨料和研磨液来去除覆盖层并且使金属化层和导线的表面平坦化的工艺。从金属化层去除材料直到暴露电介质表面。图4e示出了在平坦化之后的金属化层104,其中,去除了覆盖层从而暴露了层间电介质表面112和护套108的一部分。
如上文所提到的,金属化层可以直接或间接沉积在诸如硅晶片的基板上,从而形成集成电路。集成电路是模拟电路或数字电路。集成电路可以用在许多应用中,例如微处理器、光电子产品、逻辑块、音频放大器等。集成电路可以用作用于在计算机中执行一个或多个相关功能的部分芯片组。
示例
示例1
如上文所指出的,可能影响可以在导线上运载的电流量的因素包括导线两端的最大电压降和电迁移。
导线两端的最大电压降部分地由导线电阻来决定,导线电阻受导线材料的电阻率的影响。图5示出了长度为25μm和100μm并且横截面面积为250nm2的钴和铜芯导线的电阻的示例。图表示出了铜芯具有较低的每单位长度电阻,这允许应用于较长的导线长度。
示例2
为了证实材料对最大电流密度的影响,图6示出了被各种导线尺寸(直径)的钴护套(A)包围的铜芯的被估计的最大电流密度与具有类似导线尺寸的钴(B)的最大电流密度和铜(C)的最大电流密度相比的示例。超过最大电流密度可能导致电迁移。如图所示,与单独使用铜导线相比,通过给铜芯装上钴护套,被估计的最大电流密度增大。
示例3
根据本文中的方法制备样本,其中,使用在层间电介质中形成若干开口的193nm光刻来将包括沉积在硅上的碳掺杂氧化物的层间电介质的金属化层图案化。经由以500rpm进行60秒的旋涂来沉积化学辅助光致抗蚀剂。在150℃的温度下预烘烤2分钟的时段之后,使用193nm的光将光致抗蚀剂图案化。随后再次在250℃的温度下对基板进行烘烤并且持续5分钟的时段。
经由旋涂来施加碱性显影剂,并且去除了光致抗蚀剂的所选择的部分。随后在250℃的温度下对光致抗蚀剂进行5分钟的时段的硬烘烤。在100℃的温度和几毫托与几百毫托之间的气压下使用氟碳化合物等离子体对层间电介质的暴露区域进行2分钟的时段的蚀刻。在蚀刻之后,通过暴露于氧等离子体来去除剩余的光致抗蚀剂,氧等离子体与光致抗蚀剂结合以形成灰。
在蚀刻之后,通过使用了钴前体双(环戊二烯基)钴(II)的化学气相沉积将钴(金属1)沉积到层间电介质中。在10托的气压和200℃的温度下执行该工艺。以25sccm的流速引入前体。在沉积期间将系统维持在10-100托的气压下。钴沿着金属化层开口的底部和侧壁以及跨过金属化层的上表面或台面形成共形涂层,从而形成凹槽。
随后通过物理气相沉积并且具体而言通过磁控溅射将铜沉积在钴上。随后通过在300到400℃的温度下将所沉积的铜加热50秒到500秒的时段而使得铜回流到凹槽中。所回流的铜部分填充凹槽,以使得在铜的上表面与金属化层的上表面之间存在高度差。随后经由用于形成共形涂层的化学气相沉积工艺使用钴来完全填充凹槽并且形成金属覆盖层。随后使用化学机械平坦化来去除覆盖层并且使导线与基板的上表面一样高。在必要的时候,在步骤之间,清洁基板以减少或去除氧化物和形成在表面上的其它反应产物。
在450kX的放大率下、在200kV的加速电压和-1.0mm的工作距离下对样本进行透射电子显微术(TEM)和电子色散光谱术(EDS)。图7示出了对样本所采集的TEM图像(左下角的刻度是10nm),并且图8示出了对样本所采集的EDS图像(右下角的刻度是20nm)。如在图像中看到的,在形成在金属化层中的开口内,钴(金属1)完全包围铜(金属2)。
如在以上示例中所看到的,与在相同几何形状的导线中单独使用难熔金属相比,本文中的布置和方法提供了减小的导线电阻。随着给定直径的导线的长度的增大,电阻的减小有所改进。另外,与单独使用芯材料的实例相比,该布置提供了相对有所改进的最大电流密度和电迁移性能。最大电流密度可以被理解为在不发生电迁移的情况下可以穿过导体的最大可允许电流。在实施例中,预计该改进将达到一个数量级或者更大。
本公开内容的一方面涉及在电介质层中形成导线的方法。该方法包括在电介质层中形成第一开口。在实施例中,电介质层呈现出低于3.9的介电常数,并且优选地,呈现出在1.5到3.8的范围内的介电常数。例如,电介质层包括从下列各项组成的组中选择的一种或多种材料:氟掺杂的二氧化硅、碳掺杂的二氧化硅、有机硅酸盐玻璃、碳氧化硅、氢化碳氧化硅、多孔二氧化硅、以及诸如聚酰亚胺、聚四氟乙烯、聚降冰片烯、苯并环丁烯、氢倍半硅氧烷和甲基倍半硅氧烷之类的有机聚合物电介质。在以上实施例中的任何一个中,通过光刻在电介质层中形成开口。
该方法还包括在电介质层上沉积护套材料的第一层的共形涂层并且在第一开口中形成第二开口。在以上实施例中的任何一个中,通过化学气相沉积形成共形涂层。替代地或另外地,使用原子层沉积形成共形涂层。
该方法还包括在共形涂层上沉积芯材料并且对芯材料进行回流,其中,芯材料部分地填充第二开口。在以上实施例中的任何一个中,使用物理气相沉积或化学气相沉积来沉积芯材料。
另外,该方法包括在芯材料和护套材料的第一层之上沉积护套材料的第二层,从而填充第二开口并且形成导线,其中,芯材料被护套材料包围。在以上实施例中的任何一个中,使用化学气相沉积或物理气相沉积来沉积护套材料的第二层。
护套材料呈现出第一电阻率ρ1,并且芯材料呈现出第二电阻率ρ2,并且ρ2小于ρ1。在以上实施例中的任何一个中,护套材料呈现出5.0μΩ·cm或更大的电阻率。在以上实施例中的任何一个中,芯材料呈现出4.0μΩ·cm或更小的电阻率。例如,芯材料包括铜,并且护套材料不包括铜。在以上实施例中的任何一个中,芯材料呈现出第一熔化温度,并且护套材料呈现出第二熔化温度,其中,第一熔化温度低于第二熔化温度。在示例中,芯材料包括从由铜、铝、金和银组成的组中选择的一种或多种金属。在示例中,护套材料包括从由钨、钴、钌和钼组成的组中选择的一种或多种金属。
在以上实施例中的任何一个中,第一开口限定了体积,并且护套材料存在于该体积的25%到75%的范围内。
在以上实施例中的任何一个中,该方法还包括在电介质层的表面之上形成护套材料的第二层的覆盖层。该方法还包括使护套材料的第二层平坦化直到暴露电介质层的表面。
在本公开内容的另一个方面中,提供了金属化层。开口限定在电介质层中并且导线安置在开口内。该导线包括被护套材料包围的芯材料,其中,护套材料呈现出第一电阻率ρ1,并且芯材料呈现出第二电阻率ρ2,并且ρ2小于ρ1。另外,在实施例中,护套材料存在于该开口的体积的25%到75%的范围内。
在实施例中,金属化层呈现出低于3.9的介电常数,并且优选地,呈现出在1.5到3.8的范围内的介电常数。例如,金属化层包括从下列各项组成的组中选择的一种或多种材料:氟掺杂的二氧化硅、碳掺杂的二氧化硅、有机硅酸盐玻璃、碳氧化硅、氢化碳氧化硅、多孔二氧化硅、以及诸如聚酰亚胺、聚四氟乙烯、聚降冰片烯、苯并环丁烯、氢倍半硅氧烷氢和甲基倍半硅氧烷之类的有机聚合物电介质。
在以上实施例中的任何一个中,护套材料呈现出5.0μΩ·cm或更大的电阻率,优选地呈现出在5.0μΩ·cm到8.0μΩ·cm的范围内的电阻率,并且芯材料呈现出4.0μΩ·cm或更小的电阻率,优选地呈现出在1.0μΩ·cm到4.0μΩ·cm的范围内的电阻率。在以上实施例中的任何一个中,芯材料呈现出第一熔化温度,并且护套材料呈现出第二熔化温度,其中,第一熔化温度低于第二熔化温度。例如,芯材料包括从由铜、铝、金和银组成的组中选择的一种或多种金属。例如,护套材料包括从由钨、钴、钌和钼组成的组中选择的一种或多种金属。在特定实施例中,芯材料包括铜,并且护套材料不包括铜。
在实施例中,根据上述方法的实施例中的任何一种来制备金属化层。
在又一个方面中,本公开内容涉及集成电路,该集成电路包括:一个或多个电介质层;限定在电介质层中的每个电介质层中的多个开口;以及连接到与集成电路相关联的一个或多个部件的多条导线。每条导线安置在开口中的一个开口内,并且导线包括被护套材料包围的芯材料,其中,护套材料呈现出第一电阻率ρ1,并且芯材料呈现出第二电阻率ρ2,并且ρ2小于ρ1。此外,护套材料存在于开口的体积的25%到75%的范围内。
在实施例中,集成电路的(多个)电介质层呈现出低于3.9的介电常数,并且优选地,呈现出在1.5到3.8的范围内的介电常数。(多个)电介质层包括例如从由下列各项组成的组中选择的一种或多种材料:氟掺杂的二氧化硅、碳掺杂的二氧化硅、有机硅酸盐玻璃、碳氧化硅、氢化碳氧化硅、多孔二氧化硅、以及诸如聚酰亚胺、聚四氟乙烯、聚降冰片烯、苯并环丁烯、氢倍半硅氧烷和甲基倍半硅氧烷之类的有机聚合物电介质。
在以上实施例中的任何一个中,护套材料呈现出5.0μΩ·cm或更大的电阻率,优选地呈现出在5.0μΩ·cm到8.0μΩ·cm的范围内的电阻率,并且芯材料呈现出4.0μΩ·cm或更小的电阻率,优选地呈现出在1.0μΩ·cm到4.0μΩ·cm的范围内的电阻率。在以上实施例中的任何一个中,芯材料呈现出第一熔化温度,并且护套材料呈现出第二熔化温度,其中,第一熔化温度低于第二熔化温度。例如,芯材料包括从由铜、铝、金和银组成的组中选择的一种或多种金属。例如,护套材料包括从由钨、钴、钌和钼组成的组中选择的一种或多种金属。在特定实施例中,芯材料包括铜,并且护套材料不包括铜。
在实施例中,根据上述方法中的任何一种来装备集成电路,并且集成电路包括根据上述实施例中的任何一个的金属化层。
出于例示的目的已经介绍了若干方法和实施例的前述描述。其并不旨在是详尽的或是将权利要求限制于所公开的任何精确步骤和/或形式,并且鉴于以上教导,许多修改和变型明显都是可能的。本发明的范围旨在由其所附权利要求书来限定。
Claims (11)
1.一种在电介质层中形成导线的方法,包括:
在电介质层中形成第一开口;
在所述电介质层上沉积护套材料的第一层的共形涂层,并且在所述第一开口中形成第二开口,其中,所述护套材料呈现出第一电阻率ρ1;
在所述共形涂层上沉积芯材料,其中,所述芯材料呈现出第二电阻率ρ2,并且ρ2小于ρ1,并且其中,所述芯材料部分填充所述第二开口;以及
在所述芯材料和所述护套材料的所述第一层之上沉积所述护套材料的第二层,填充所述第二开口并且形成导线,其中,所述芯材料处于被所述护套材料包围的体积中,所述芯材料完全填充被所述护套材料包围的所述体积。
2.根据权利要求1所述的方法,其中,所述第一开口限定了体积,并且所述护套材料存在于所述体积的25%到75%的范围内。
3.根据权利要求1所述的方法,其中,所述护套材料的所述第二层的覆盖层形成在所述电介质层的表面之上,并且所述方法还包括使护套材料的所述第二层平坦化直到暴露所述电介质层的所述表面。
4.根据权利要求1所述的方法,其中,通过光刻在所述电介质层中形成所述开口。
5.根据权利要求1所述的方法,其中,使用化学气相沉积来沉积所述共形涂层。
6.根据权利要求1所述的方法,其中,使用物理气相沉积来沉积所述芯材料。
7.根据权利要求1所述的方法,其中,所述芯材料包括选自由铜、铝、金和银组成的组中的一种或多种金属。
8.根据权利要求1所述的方法,其中,所述护套材料包括选自由钨、钴、钌和钼组成的组中的一种或多种金属。
9.根据权利要求1所述的方法,其中,所述芯材料包括铜并且所述护套材料不包括铜。
10.一种集成电路,包括:
电介质层;
限定在所述电介质层中的多个开口;以及
多条导线,其中,每条导线置于所述开口的其中之一内,并且每条导线包括芯材料,所述芯材料处于在垂直截面图中被护套材料完全包围的体积中,所述芯材料完全填充被所述护套材料包围的所述体积,其中,所述护套材料处于所述开口的所述其中之一内,并且其中,所述护套材料呈现出第一电阻率ρ1,并且所述芯材料呈现出第二电阻率ρ2,并且ρ2小于ρ1。
11.一种集成电路,包括:
具有最上表面的电介质层;
限定在所述电介质层中的多个开口;以及
多条导线,其中,每条导线置于所述开口的其中之一内,并且每条导线包括芯材料,所述芯材料处于在垂直截面图中被护套材料完全包围的体积中,所述芯材料完全填充被所述护套材料包围的所述体积,其中,所述护套材料具有与所述电介质层的所述最上表面共面的最上表面,并且其中,所述护套材料呈现出第一电阻率ρ1,并且所述芯材料呈现出第二电阻率ρ2,并且ρ2小于ρ1。
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US20230130273A1 (en) | 2023-04-27 |
US9691657B2 (en) | 2017-06-27 |
US20210020502A1 (en) | 2021-01-21 |
SG11201600829RA (en) | 2016-03-30 |
TW201532130A (zh) | 2015-08-16 |
US20170372950A1 (en) | 2017-12-28 |
US20160225665A1 (en) | 2016-08-04 |
SG10201803987PA (en) | 2018-06-28 |
CN105493243A (zh) | 2016-04-13 |
KR20220005643A (ko) | 2022-01-13 |
KR20160061962A (ko) | 2016-06-01 |
US9349636B2 (en) | 2016-05-24 |
EP3050081A4 (en) | 2017-05-10 |
US11881432B2 (en) | 2024-01-23 |
US11569126B2 (en) | 2023-01-31 |
US10832951B2 (en) | 2020-11-10 |
US20240112952A1 (en) | 2024-04-04 |
CN107731785A (zh) | 2018-02-23 |
KR102472898B1 (ko) | 2022-12-02 |
KR20230006599A (ko) | 2023-01-10 |
US20150084198A1 (en) | 2015-03-26 |
TWI556297B (zh) | 2016-11-01 |
EP3050081A1 (en) | 2016-08-03 |
CN107731785B (zh) | 2022-03-29 |
WO2015048221A1 (en) | 2015-04-02 |
EP3050081B1 (en) | 2021-07-07 |
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