WO2010097190A1 - Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices - Google Patents
Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices Download PDFInfo
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- WO2010097190A1 WO2010097190A1 PCT/EP2010/001091 EP2010001091W WO2010097190A1 WO 2010097190 A1 WO2010097190 A1 WO 2010097190A1 EP 2010001091 W EP2010001091 W EP 2010001091W WO 2010097190 A1 WO2010097190 A1 WO 2010097190A1
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- dielectric material
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- 239000003989 dielectric material Substances 0.000 title claims abstract description 87
- 238000001465 metallisation Methods 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 230000006866 deterioration Effects 0.000 title description 3
- 239000000463 material Substances 0.000 claims abstract description 76
- 238000011282 treatment Methods 0.000 claims abstract description 58
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910052802 copper Inorganic materials 0.000 claims abstract description 53
- 239000010949 copper Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 49
- 239000000126 substance Substances 0.000 claims abstract description 47
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 122
- 230000008569 process Effects 0.000 claims description 74
- 238000000151 deposition Methods 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 230000004888 barrier function Effects 0.000 claims description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 15
- 238000004140 cleaning Methods 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 10
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 claims description 10
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 5
- 230000004048 modification Effects 0.000 claims description 5
- 238000012986 modification Methods 0.000 claims description 5
- 229910000077 silane Inorganic materials 0.000 claims description 5
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 claims description 3
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 claims description 3
- 229940094989 trimethylsilane Drugs 0.000 claims description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 2
- 239000005751 Copper oxide Substances 0.000 claims description 2
- 229910000431 copper oxide Inorganic materials 0.000 claims description 2
- 238000010924 continuous production Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 84
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- 230000001965 increasing effect Effects 0.000 description 8
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- 238000000059 patterning Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
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- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 238000004070 electrodeposition Methods 0.000 description 5
- 230000002708 enhancing effect Effects 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000010348 incorporation Methods 0.000 description 3
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- 230000003071 parasitic effect Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000005749 Copper compound Substances 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000001722 carbon compounds Chemical class 0.000 description 2
- 238000001311 chemical methods and process Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 150000001880 copper compounds Chemical class 0.000 description 2
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- 238000005137 deposition process Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
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- 239000003054 catalyst Substances 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
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- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- -1 i.e. Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
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- 238000011160 research Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/906—Cleaning of wafer as interim step
Definitions
- the present disclosure relates to microstructures, such as advanced integrated circuits, and more particularly to metallization systems comprising sophisticated dielectric and conductive materials.
- interconnect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area as typically the number of interconnections required increases more rapidly than the number of circuit elements.
- a plurality of stacked "wiring" layers also referred to as metallization layers, is provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias.
- Advanced integrated circuits including transistor elements having a critical dimension of 0.05 ⁇ m and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm 2 in the individual interconnect structures despite the provision of a relatively large number of metallization layers owing to the increased number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, i.e., materials with significantly lower electrical resistivity and improved resistance to electromigration even at considerably higher current densities compared to aluminum.
- silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms
- selecting silicon nitride as an interlayer dielectric material is less than desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighbouring copper lines, which may result in non- tolerable signal propagation delays.
- a thin conductive barrier layer that also imparts the required mechanical stability to the copper is usually formed so as to separate the bulk copper from the surrounding dielectric material, thereby reducing copper diffusion into the dielectric materials and also reducing the diffusion of unwanted species, such as oxygen, fluorine, and the like, into the copper.
- the conductive barrier layers may also form strong interfaces with the copper, thereby reducing the probability for inducing significant material migration at the interface, which is typically a critical region in view of increased diffusion paths that may facilitate current induced material diffusion.
- tantalum, titanium, tungsten and their compounds with nitrogen and silicon and the like are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties.
- damascene Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not readily be deposited in larger amounts by chemical and physical vapor deposition techniques, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique.
- a dielectric layer is formed which is then patterned to include trenches and/or vias which are subsequently filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias.
- the deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 ⁇ m or even less in combination with trenches having a width ranging from 0.1 ⁇ m to several ⁇ m.
- Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, for the dimensions of the metal regions in semiconductor devices the void free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest.
- interconnect structures Since the geometry of interconnect structures is substantially determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and nonconductive barrier layers, the dielectric materials, and the like, and their mutual interaction, on the characteristics of the interconnect structure as a whole so as to insure both high yield and the required product reliability. In particular, it is important to identify, monitor and reduce degradation and failure mechanisms in metallization systems for various configurations so as to maintain device reliability for every new device generation or technology node.
- materials such as conductive and nonconductive barrier layers, the dielectric materials, and the like
- One failure mechanism which is believed to significantly contribute to a premature device failure, is the electromigration-induced material transport particularly along an interface formed between the copper and a dielectric cap layer, which may be provided after filling in the copper material in the trenches and via openings, the side walls of which are coated by the conductive barrier materials.
- the dielectric cap layer may usually act as an etch stop layer during the formation of the via openings in the interlayer dielectric.
- used materials are, for example, silicon nitride and nitrogen containing silicon carbide, which exhibit a moderately high etch selectivity to typically employed interlayer dielectrics, such as a plurality of low-k dielectric materials, and also suppress the diffusion of copper onto the interlayer dielectric.
- Recent research results seem to indicate, however, that the interface formed between the copper and dielectric cap layer is a major diffusion path for material transport during operation of the metal interconnect.
- the incorporation of certain species into the copper surface has been proven to be a viable technique for enhancing the overall electromigration behaviour, for instance, in combination with a corresponding cap or etch stop layer.
- the exposed surface of the copper lines may be exposed to a reactive ambient in order to incorporate silicon, nitrogen and the like for enhancing the surface characteristics of the metal lines prior to depositing the cap or etch stop material.
- a silicon and/or nitrogen containing species may be supplied into the reactive ambient of a plasma based cleaning process in order to initiate the inter-diffusion of silicon, nitrogen, and the like, thereby forming a corresponding copper compound that may significantly enhance the overall surface characteristics.
- silane may be used in a corresponding plasma treatment in order to form a silicon/copper compound, which may also be referred to as copper suicide and may provide for the superior electromigration behaviour.
- thermo chemical treatments have been used, for instance for cleaning the exposed copper surface and initiating a silicon diffusion into the copper surface in order to obtain the superior electromigration behaviour, while avoiding or at least reducing undue damage of the sensitive dielectric materials.
- the copper/silicon compound forming in and beyond the copper surface may have a negative effect on the overall conductivity of the metal line, in particular in metallization systems requiring high current densities due to the reduced cross-sectional area, which may result in significant signal propagation delays.
- the present disclosure relates to techniques for forming complex metallization layers with enhanced electromigration behaviour and improved electrical performance and high breakdown voltages of the dielectric materials, while avoiding or at least reducing the effects of one or more of the problems identified above.
- the present disclosure relates to process techniques in which a superior performance with respect to electromigration may be obtained while at the same time the overall electrical performance of the metallization system may be enhanced.
- the material characteristics of highly sensitive low-k and ULK materials may not unduly be deteriorated or may even be re-established after certain process steps on the basis of a thermo chemical treatment. It has recognized that for many sophisticated low-k dielectric materials the overall behaviour of these materials may critically depend on the carbon contents, which may significantly be reduced upon exposure to reactive plasma ambients, as may typically be applied during corresponding cleaning processes and frequently also during the incorporation of a silicon species into exposed surface areas.
- thermo chemical treatment may be applied which may result in a significantly reduced degree of carbon depletion upon interaction with sensitive low-k dielectric materials, while a copper-containing metal region may have formed thereon a conductive cap layer which may result in superior electromigration performance and may also act as an efficient mask during the thermo chemical treatment.
- thermo chemical treatment may result in superior characteristics of the low-k dielectric material, wherein in some illustrative embodiments disclosed herein a further thermo chemical treatment may be performed on the basis of an appropriate process ambient, such as a silicon-containing ambient, which may result in a corresponding improvement of surface characteristics of the dielectric material.
- a certain degree of etch-related damage of the sensitive low-k dielectric material may be "repaired" thereby enhancing the surface conditions for the further processing of the semiconductor device, for instance in view of depositing a further dielectric material, such as an etch stop material or any other transition material layer for forming thereon a further low-k dielectric material.
- a further dielectric material such as an etch stop material or any other transition material layer for forming thereon a further low-k dielectric material.
- One illustrative method disclosed herein relates to forming a metallization layer for a semiconductor device.
- the method comprises forming a conductive cap layer on a surface of a metal region that is laterally embedded in a first dielectric material of the metallization layer. Additionally, the method comprises performing a thermo chemical cleaning treatment on an exposed surface of the first dielectric material in the presence of the conductive cap layer. Furthermore, the method comprises forming a second dielectric material on the exposed surface of the first dielectric material and the conductive cap layer.
- a further illustrative method disclosed herein comprises forming a conductive cap material on a copper-containing surface of a metal region of a metallization layer of a semiconductor device, wherein the metal region is formed in a low-k dielectric material of the metallization layer.
- the method further comprises performing a first thermo chemical treatment on an exposed surface of the low-k dielectric material on the basis of a copper oxide reducing process gas.
- the method additionally comprises performing a second thermo chemical treatment on the exposed surface on the basis of a silicon-containing process ambient after performing the first thermo chemical treatment.
- the method comprises forming a dielectric material layer on the conductive cap layer and the exposed surface of the low-k dielectric material.
- a still further illustrative method disclosed herein relates to forming a metallization layer of a semiconductor device.
- the method comprises forming an opening in a low-k dielectric layer and filling the opening with a copper-containing material so as to form a metal region. Furthermore, a conductive cap layer is formed on the surface of the metal region and a cleaning process is performed on the basis of a copper-reducing gas ambient in the absence of a plasma. Additionally, the method comprises performing a surface modification process on the basis of a silicon-containing process ambient in the absence of a plasma in the silicon-containing process ambient.
- Figs 1 a, 1 b and 1 d schematically illustrate cross-sectional views of a semiconductor device during various manufacturing stages in forming metallization layers in which a thermo chemical treatment may be performed on the basis of a conductive cap layer according to illustrative embodiments;
- Fig 1 c schematically illustrates the semiconductor device according to a further illustrative embodiment in which an additional thermo chemical treatment may be performed so as to further enhance the characteristics of a sensitive low-k dielectric material according to still further illustrative embodiments.
- the present disclosure provides process techniques in which superior electromigration characteristics may be achieved for metal regions in sophisticated metallization systems on the basis of a conductive cap material, while additionally undue deterioration of sensitive low-k dielectric materials, such as carbon depletion, etch-related damage and the like, may be reduced so that overall performance of the metallization system may be enhanced due to superior electromigration with a desired high conductivity at more stable and uniform characteristics of the dielectric material, for instance in view of a higher breakdown voltage and the like.
- a cleaning process may be performed as a thermo chemical treatment, which may be understood as a treatment performed in a process ambient that is established without a plasma, ie.
- thermo chemical process ambient may be understood as an ambient in which the fraction of ionized particles substantially corresponds to a fraction that would be obtained by the thermal movement of molecules and atoms according to specified pressure and temperature conditions.
- a higher fraction of ionized particles caused by interaction with an electromagnetic field may not be considered as a thermo chemical process ambient.
- the thermo chemical cleaning process may be performed on the basis of oxide-reducing gases, such as an ammonia gas and/or a nitrogen gas, and may result in an efficient removal of contaminants generated during the preceding processes, such as copper deposition, chemical mechanical polishing of excess materials, the deposition of the conductive cap layer and the like, while also reducing the tendency of the sensitive low-k dielectric material for out diffusion of carbon species, which may significantly affect the overall characteristics of the low-k material.
- oxide-reducing gases such as an ammonia gas and/or a nitrogen gas
- a further thermo treatment may be performed on the basis of the silicon- containing process ambient in which a certain degree of surface modification may be accomplished, for instance by hardening or densifying exposed surface areas of the sensitive low-k dielectric material, thereby providing for further enhanced surface conditions during the further processing, or even reducing the degree of damage of previously performed etch and resist strip processes, thereby also contributing to superior reliability and thus dielectric strength.
- thermo chemical treatment may thus be performed as an in situ process sequence with a cleaning step and a subsequent "silicon diffusion" step, possibly in combination with a deposition process for forming a further dielectric material, such as a silicon nitride material, nitrogen-containing silicon carbide material and the like.
- a further dielectric material such as a silicon nitride material, nitrogen-containing silicon carbide material and the like.
- an efficient silicon diffusion into the exposed surface areas on the basis of a plasma-free treatment may thus re-establish to a certain degree the desired molecular structure or may provide for enhanced hardness or density of the surface area, which may also in part enhance mechanical stability to these materials, which may frequently be provided in the form of a porous material system.
- the degree of porosity at the exposed surface areas of these sensitive dielectric materials may be reduced by establishing a process ambient during the thermo chemical treatment on the basis of silicon-containing substances in the form of HMDS (hexamethyldisilazane) and the like.
- thermo chemical treatment may also be performed prior to actually forming the metal regions in the sensitive dielectric material, that is, after patterning the dielectric material and prior to forming a conductive barrier material and depositing a copper-containing metal. Also in this case a negative effect of plasma-based processes may be avoided while nevertheless obtaining superior surface conditions for the subsequent process steps.
- Fig 1 a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 in and above which may be formed circuit elements, such as transistors and the like, as required by the overall circuit configuration of the device 100.
- circuit elements such as transistors and the like
- the continuous shrinkage of the critical feature sizes in the transistor level of the device which may currently be at approximately 50 nm and less, also requires a corresponding adaptation of the feature sizes of metal lines and vias in a metallization system 130 of the device 100.
- the metallization system 130 may be represented by a first metallization layer 110 and a second metallization layer 120.
- the metallization system 130 may comprise any number of metallization layers as is necessary in view of the overall complexity of the device 100.
- any further metallization layers which may be formed above the layer 120 or which may be positioned below the metallization layer 1 10 are not shown.
- the metallization layer 1 10 may comprise a dielectric material 111 , such as a low-k dielectric material having a dielectric constant of 3.0 or less, while in more sophisticated applications the dielectric constant may be approximately 2.0 and less, in which case corresponding materials may also be referred to herein as ultra low-k (ULK) materials.
- ULK ultra low-k
- the 110 may comprise a metal region or metal line 1 12 wherein it should be appreciated that typically a large number of appropriate metal regions may be provided in the metallization layer 1 10.
- the metal line or metal region 112 may comprise a highly conductive core material 1 12a based on copper, silver and the like, while a conductive barrier material 1 12b may confine the core materials 112a, for instance with respect to diffusion into the surrounding dielectric material and with respect to the incorporation of reactive components, such as oxygen, fluorine and the like, which may be present in the dielectric material 111 .
- the conductive barrier material 1 12b may provide for the desired adhesion of the core material 112a to the surrounding dielectric material
- a conductive cap layer 1 12c may be formed on the core material 1 12a and may be comprised of any appropriate material, such as CoWP compounds and the like, as is for instance also previously explained. It should be appreciated, however, that in other illustrative embodiments (not shown) the conductive cap layer 112c may not be provided if considered appropriate for the metallization layer 110, while however in other metallization layers such as the layer 120 superior electromigration behaviour in combination with a high electric conductivity may be required.
- a dielectric etch stop or cap layer 113 which may be comprised of silicon carbide, nitrogen-containing silicon carbide, silicon nitride and the like, may be formed on the dielectric material 111 and on the metal region 112, for instance on the conductive cap layer 112c, while in other cases the dielectric layer 113 may provide for the required copper confinement and electromigration behaviour.
- the metallization layer 120 may comprise a dielectric material 121 , which may also represent a low-k dielectric material or a ULK material, which may have a more or less porous state, as previously explained.
- a metal region 122 may laterally be embedded in the dielectric material 121 and may comprise a core material 122a, such as a copper material, in combination with a conductive barrier material 122b.
- the metal region 122 may comprise a metal line 1221 and a via 122v connecting to the metal region 112 of the metallization layer 1 10.
- a conductive cap layer 122c formed of any appropriate metal or metal compound may be formed at least on the core material 122a so as to provide for superior electromigration behaviour while not unduly affecting the overall conductivity of the metal region 122.
- the semiconductor device 100 as illustrated in Fig 1 a may be formed on the basis of the following processes. After forming corresponding circuit elements, such as transistors, in a semiconductor material provided above the substrate 101 , a contact structure (not shown) may be formed on the basis of well-established process techniques in order to provide an interface between the circuit elements formed in and above the semiconductor material and the metallization system 130. Thereafter, one or more metallization layers may be formed, such as the layer 1 10. For this purpose, the dielectric material 1 11 may be deposited on the basis of any appropriate deposition technique, such as CVD, spin-on techniques and the like, depending on the type of material to be deposited. As previously explained, the material 11 1 may comprise a certain fraction of carbon species, which may significantly affect the overall material characteristics.
- the dielectric material 11 1 may be patterned on the basis of sophisticated lithography and etch strategies, as will also be explained with reference to the metallization layer 120. Finally, respective openings corresponding to the metal region 122 may be filled with a metal-containing material and any excess material thereof may be removed, for instance by CMP (chemical mechanical polishing) so as to provide electrically isolated metal regions in the dielectric material 111. Thereafter, the conductive cap layer 1 12c may be formed, if required, followed by the deposition of the dielectric layer 113.
- CMP chemical mechanical polishing
- the dielectric material 121 may be deposited as is previously explained with reference to the material 111 and a corresponding patterning sequence may be performed so as to obtain a trench and a via opening for the metal line 1221 and the via 122t, respectively.
- a corresponding patterning sequence may be performed so as to obtain a trench and a via opening for the metal line 1221 and the via 122t, respectively.
- an appropriate thermo chemical treatment may be performed, as will be explained later on with reference to Figs 1 b and 1 c.
- the conductive barrier material 122b may be deposited followed by the deposition of the core 122a and the removal of any excess material thereof.
- the device 100 may be exposed to a deposition ambient 102, which may represent an electrochemical deposition ambient or a gaseous ambient, for instance a CVD ambient, an ambient for physical vapour deposition, such as sputter deposition and the like.
- a deposition ambient 102 may represent an electrochemical deposition ambient or a gaseous ambient, for instance a CVD ambient, an ambient for physical vapour deposition, such as sputter deposition and the like.
- a plurality of metal materials may efficiently be deposited on the basis of electrochemical deposition techniques, for instance electroless plating, in which an exposed surface of the core material 122a may act as a catalyst material for initiating a deposition of the material from an appropriate electrolyte solution. Consequently, a very selective material deposition may be achieved without requiring any additional patterning strategies for restricting the conductive cap layer 122c to the metal line 1221.
- any other appropriate deposition regime may be used, for instance selective CVD-like deposition techniques, in which the core material 122a
- Fig 1 b schematically illustrates the semiconductor device 100 when exposed to a process ambient of a first thermo chemical treatment 103a.
- the process ambient of the treatment 103a may be established in any appropriate process tool, such as a deposition chamber and the like if, for instance, a deposition of a further dielectric material may be performed as an in situ process.
- the process ambient of the treatment 103a may be established on the basis of a copper-reducing gas, which may for instance be established on the basis of ammonia (NH 3 ) and nitrogen (N 2 ) at a pressure of approximately 1 - 6 Torr.
- the ratio of ammonia and nitrogen gas may range from approximately 1 :400 - 1 :1 while in other cases even substantially pure ammonia may be used as the reducing gas.
- the substrate 101 may be heated to approximately 250 - 500 0 C, for instance to approximately 350°C, in order to establish a desired process temperature for the treatment 103a. Consequently, a thermally induced chemical cleaning process may be initiated at the surface of the cap layer 122c and also on the surface 121 s of the dielectric material 121.
- the treatment 103a may result in the removal of metal residues, which may have been generated during the previous process sequences, for instance the deposition of the materials 122a, 122b and the corresponding removal of any excess material thereof.
- residues may have deposited in the exposed surface 121 s, which may efficiently be removed, while also reducing the degree of carbon depletion, which may typically be observed upon plasma-based cleaning processes.
- Fig 1 c schematically illustrates the semiconductor device 100 according to a further illustrative embodiment in which the device 100 may in addition to the thermo chemical treatment 103a be exposed to a further thermo chemical treatment 103b.
- the treatments 103a, 103b may be performed on the basis of an appropriate process ambient without exposing the device 100 to ambient atmosphere between the treatments 103a and 103b.
- a corresponding sequence of processes may also be referred to as an in situ process sequence, irrespective of whether the processes of the sequence may be performed in the same or different process chambers as long as an undue exposure to ambient atmosphere may be avoided.
- the thermo chemical treatment 103b may be performed on the basis of a gaseous ambient including, in one illustrative embodiment, a silicon-containing gas component, such as silane or any derivatives thereof, such as tri methyl silane (3MS), tetra methyl silane (4MS), HMDS and the like.
- a silicon-containing gas component such as silane or any derivatives thereof, such as tri methyl silane (3MS), tetra methyl silane (4MS), HMDS and the like.
- a corresponding silicon diffusion into the exposed surface 121s may be initiated, thereby providing for a certain degree of hardening or densification of the surface 121 s.
- HMDS may be used for enhancing the surface conditions of the material 121 , thereby even "re-establishing" a desired structure of the surface 121 s, which may have been damaged in the preceding process steps.
- a required degree of silicon diffusion into the surface 121s may readily be determined on the basis of corresponding test measurements in which different dielectric materials may be treated on the basis of different parameter settings for the treatment 103b and determining the surface conditions after the various treatments. Consequently, the exposed surface 121 s may be modified so as to provide enhanced surface conditions during the further processing, for instance during the deposition of a further dielectric material thereby reducing the probability of affecting the characteristics of the material 121 , which may thus result in enhanced reliability, as previously explained.
- the cap layer 121 c may act as a protection layer so as to avoid undue silicon diffusion into the core material 122a, which may otherwise result in a reduced overall conductivity, as also previously discussed.
- Fig 1 c schematically illustrates the semiconductor device 100 when exposed to a deposition ambient 104 after performing the treatment 103a (cf. Fig 1 b) and, in some illustrative embodiments, also the treatment 103b (cf. Fig 1 c).
- the deposition ambient 104 may be established on the basis of appropriate process parameters and precursor materials in order to obtain a desired composition of a dielectric layer 123, which may act as an etch stop material or any other appropriate transition layer for forming thereon a further dielectric material.
- the deposition process 104 represents one process of a process sequence comprising at least the treatment 103a (cf. Fig 1 b), wherein the process sequence may be performed as an in situ process in the above-defined sense.
- the treatment 103b (cf. Fig 1 c) may be performed and may also represent a part of the process sequence wherein the deposition ambient 104 may be established in the same process chamber as the process ambient of the treatment 103b.
- a plasma may be established so as to initiate the deposition of silicon, nitrogen and carbon in order to form the dielectric layer 123.
- the enhanced surface 121 s obtained by the previous one or more of the thermo chemical treatments may result in enhanced deposition uniformity and thus stable and reliable overall characteristics, such as enhanced dielectric strength and the like.
- any desired material composition may be deposited during the process 104, such as two or more different material layers in the form of silicon carbide, silicon nitride, nitrogen- containing silicon carbide and the like. Thereafter, the further processing may be continued by depositing a further dielectric material, such as a ULK material and the like, and forming therein appropriate metal lines and vias, as is also described with reference to the metallization layers 110 and 120.
- a further dielectric material such as a ULK material and the like
- thermo chemical treatments 103a, 103b, as described with reference to Figs 1 b and 1 c may be applied as a process sequence after the patterning of the dielectric material 121 , as discussed above.
- sophisticated etch strategies may have to be applied requiring formation of a resist mask, possibly in combination with hard mask material, so as to etch through the dielectric layer 121 and forming a corresponding trench for the metal line 1221 (cf. Fig 1 a).
- the repeated exposure to a reactive ambient such as anisotropic etch recipes, resist strip processes and the like, may result in a significant degree of damage of exposed surface portions of the dielectric material 121.
- a reactive ambient such as anisotropic etch recipes, resist strip processes and the like
- applying the sequence of treatments 103a, 103b of Figs 1 b and 1c may result in an efficient removal of contaminants and also in a corresponding "reinforcement" of exposed surface portions of the dielectric material 121. Consequently, carbon depletion during the further processing may be reduced and also enhanced surface conditions may be obtained, for instance by hardening or densifying the exposed surface areas.
- the conductive barrier material 122b upon depositing the conductive barrier material 122b, a more reliable degree of coverage may be obtained since the degree of porosity and etch damage at the surface areas of the material 121 may significantly be reduced. Furthermore, due to the avoidance of a plasma in the sequence 103a, 103b, additional damage may be avoided.
- the present disclosure provides techniques in which enhanced electromigration behaviour may be accomplished on the basis of a conductive cap layer while additionally enhanced material characteristics of sensitive dielectric materials may be obtained by using a plasma-free cleaning process, possibly in combination with a surface modification process on the basis of, for instance, a silicon-containing process ambient. Further modifications and variations of the present disclosure will be apparent to those skilled in the art in view of this description. Accordingly, the description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the principles disclosed herein. It is to be understood that the forms shown and described herein are to be taken as the presently preferred embodiments.
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JP2011551431A JP2012519373A (en) | 2009-02-27 | 2010-02-22 | Providing superior electromigration performance and reducing degradation of sensitive low-k dielectrics in semiconductor device metallization systems |
CN2010800121646A CN102388449A (en) | 2009-02-27 | 2010-02-22 | Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices |
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DE102008063417B4 (en) * | 2008-12-31 | 2016-08-11 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Local silicidation on contact hole bottoms in metallization systems of semiconductor devices |
US8710660B2 (en) | 2012-07-20 | 2014-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid interconnect scheme including aluminum metal line in low-k dielectric |
US9373579B2 (en) * | 2012-12-14 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protecting layer in a semiconductor structure |
CN103871959B (en) * | 2012-12-17 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and its manufacture method |
US20150206798A1 (en) * | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect Structure And Method of Forming |
US10020260B1 (en) * | 2016-12-22 | 2018-07-10 | Globalfoundries Inc. | Corrosion and/or etch protection layer for contacts and interconnect metallization integration |
US10515896B2 (en) | 2017-08-31 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor device and methods of fabrication thereof |
CN113471070B (en) | 2020-05-22 | 2022-04-12 | 北京屹唐半导体科技股份有限公司 | Workpiece processing using ozone gas and hydrogen radicals |
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