CN113690153B - 防止esd破坏tft的方法、tft的制备方法 - Google Patents
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Abstract
本发明提供了一种防止ESD破坏TFT(英文全称:Thin Film Transistor,中文:薄膜晶体管)的方法、TFT的制备方法、显示面板,通过对测试数据进行拟合,获取TFT的抗ESD能力与每一膜层的制备参数之间的关系,即在所述栅极层的爬坡角的角度范围为0°‑40°,且栅极层的爬坡角的角度越小,所述TFT的抗ESD能力越强;所述栅极绝缘层的厚度越大,所述TFT的抗ESD能力越强。根据上述关系,设置TFT的各膜层的制备参数,防止ESD破坏TFT。
Description
技术领域
本发明涉及一种显示技术领域,尤其涉及一种防止ESD破坏TFT的方法、TFT的制备方法、显示面板。
背景技术
ESD(Electro-Static Discharge)静电释放,即两物电位差不相等,经由接触或感应所产生的放电现象。它存在于环境之中,放电作用通过线路,电流脉冲无法被具保护的线路所疏通掉,瞬间通过的电流会将材料内部的温度提升至熔点,因此造成元件损伤。影响静电大小的因素主要有不纯物的混入,不纯物的导电度高带静电量低、表面状态接触面积与压力(即接触面积越大),带静电越高,压力越大;带静电越高,即分离速度越快;带静电越高,元件受到ESD冲击会产生剧变失效。元件在受到ESD冲击,遭受到彻底破坏,元件不再有功能,这种失效是永久性的,这种ESD可能使金属熔化,显示界面破坏,介电层破坏,这通常是因为在元件局部区域有高能量密度的放电所造成。元件受ESD影响会存在潜在缺陷。这类缺陷比较难侦测,元件受到部分的伤害,有某程度的劣化,虽还有正常的功能,但是其生命周期明显的变短,若系统中有这种元件,常常会提早报废。对于TFT LCD,ESD的破坏会造成AA(array area)区的线类不良,也会造成GOA(gate on array)的黑屏及线类不良。
发明内容
本发明提供了一种防止ESD破坏TFT的方法、TFT的制备方法、显示面板,以解决现有技术中存在的电子元件由于静电释放现象导致被损毁、缩短使用寿命的技术问题。
为了达到上述目的,本发明提供一种防止ESD破坏TFT的方法,其包括如下步骤:获取多个TFT的至少一膜层的测试数据,所述测试数据包括每一膜层的制备参数以及每一膜层所能承受的静电释放电压;将所述测试数据进行数据拟合,得到至少一拟合曲线;以及从所述拟合曲线中获取所述TFT的抗ESD能力与每一膜层的制备参数之间的关系。
进一步的,所述制备参数包括所述TFT的栅极层的爬坡角,所述栅极层的爬坡角的角度范围为0°-40°。
进一步的,所述栅极层的爬坡角的角度越小,所述TFT的抗ESD能力越强。
进一步的,所述制备参数包括所述TFT的栅极绝缘层的厚度,所述栅极绝缘层的厚度越大,所述TFT的抗ESD能力越强。
进一步的,所述栅极绝缘层的材质为无机材料。
进一步的,所述TFT包括:栅极层、栅极绝缘层以及有源层;所述栅极层的厚度为d0、所述栅极层的爬坡角的角度为A,所述栅极层的坡顶处的所述栅极绝缘层与所述有源层的厚度之和为d1,所述栅极层的爬坡处的所述栅极绝缘层与所述有源层的厚度之和为d2,所述栅极层的坡底处的所述栅极绝缘层与所述有源层的厚度之和为d3,其中,d2=0.773*d3+0.156*d3*cosA-0.061*d0。
进一步的,所述静电释放电压为多个TFT的同一膜层的所能承受的实际静电释放电压的平均值。
进一步的,所述测试数据还包括所述TFT的击伤比或良好比;所述击伤比为多个TFT中被静电释放电压击伤的TFT的数量相对于TFT总数的比值;所述良好比为多个TFT中未被静电释放电压击伤的TFT数量相对于TFT总数的比值。
为了达到上述目的,本发明还提供一种TFT的制备方法,其包括依据本发明所述的防止ESD破坏元件的方法中得出的所述TFT的抗ESD能力与每一膜层的制备参数之间的关系设置所述TFT的膜层的制备参数。
为了达到上述目的,本发明还提供一种显示面板,其包括TFT,所述TFT采用本发明所述的TFT的制备方法制备形成。
本发明的有益效果:本发明提供了一种防止ESD破坏TFT的方法、TFT的制备方法、显示面板,通过对测试数据进行拟合,获取TFT的抗ESD能力与每一膜层的制备参数之间的关系,即在所述栅极层的爬坡角的角度范围为0°-40°,且栅极层的爬坡角的角度越小,所述TFT的抗ESD能力越强;所述栅极绝缘层的厚度越大,所述TFT的抗ESD能力越强。根据上述关系,设置TFT的各膜层的制备参数,防止ESD破坏TFT造成AA区的线类不良,GOA区黑屏及线类不良等现象。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其它有益效果显而易见。
图1为本发明提供的TFT的结构示意图;
图2为本发明一实施例提供的栅极层的爬坡角与ESD数据拟合的示意图;
图3为本发明一实施例提供的栅极层的爬坡角与ESD击伤数据拟合的示意图;
图4为本发明一实施例提供的栅极绝缘层的厚度与ESD数据拟合的示意图;
图5为本发明一实施例提供的d0、d1、d2、d3以及A的示意图;
图6为本发明一实施例提供的d0、d1、d3以及A与d2数据拟合的示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
如图1所示,本发明提供一种防止ESD破坏元件的方法,包括如下步骤:
S1、获取多个TFT的至少一膜层的测试数据,所述测试数据包括每一膜层的制备参数以及每一膜层所能承受的静电释放电压。所述静电释放电压为多个TFT的同一膜层的所能承受的实际静电释放电压的平均值。在测试数据中,同一膜层对应多组制备参数及多个电压阈值,所述电压阈值为能承受的最大静电释放电压。
如图1所示,TFT包括依次层叠设置的基板11、栅极层12、栅极绝缘层13、有源层14、欧姆接触层15、源漏电极层16、绝缘保护层17以及像素电极18。
S2、将所述测试数据进行数据拟合,得到至少一拟合曲线。数据拟合又称曲线拟合,俗称拉曲线,是一种把现有数据透过数学方法来代入一条数式的表示方式。科学和工程问题可以通过诸如采样、实验等方法获得若干离散的数据,根据这些数据,我们往往希望得到一个连续的函数(也就是曲线)或者更加密集的离散方程与已知数据相吻合,这过程就叫做拟合(fitting)。本发明中为线性拟合,在其他实施例中还可为最小二乘拟合。
S3、从所述拟合曲线中获取所述TFT的抗ESD能力与每一膜层的制备参数之间的关系。
在一实施例中,如图2所示,圆圈无填充的为栅极层12的膜层厚度为7000埃,圆圈条纹填充的是栅极层12的膜层厚度为4000埃;当所述制备参数仅为栅极层12的爬坡角时,所述栅极层12的爬坡角的角度范围为0°-70°时,爬坡角的角度越大,所述TFT能承受的静电释放电压越小,即抗ESD能力越小。
参照图3所示,在纵坐标改为击伤比之后(所述测试数据还包括TFT的击伤比或良好比;所述击伤比为多个TFT中被静电释放电压击伤的TFT的数量相对于TFT总数的比值;所述良好比为多个TFT中未被静电释放电压击伤的TFT数量相对于TFT总数的比值)。由图3可知,所述栅极层的爬坡角的角度大于40°时,所述栅极层的爬坡角的角度越大,所述TFT的击伤比越大,因此所述所述栅极层的爬坡角的角度范围为0°-40°,且所述栅极层的爬坡角的角度越小,所述TFT的抗ESD能力越强。
如图4所示,在一实施例中,当所述制备参数仅为栅极绝缘层13的厚度时,所述栅极绝缘层13的厚度越大,所述TFT能承受的静电释放电压越大,即所述TFT的抗ESD能力越强。所述栅极绝缘层13的材质为无机材料。本实施例中,所述栅极绝缘层13包括:第一栅极绝缘层(图未示)以及第二栅极绝缘层(图未示),所述第二栅极绝缘层设于所述第一栅极绝缘层上。
如图5、图6所示,所述栅极层12的厚度为d0、所述栅极层12的爬坡角的角度为A,所述栅极层12的坡顶处的所述栅极绝缘层13与所述有源层14的厚度之和为d1,所述栅极层12的爬坡处的所述栅极绝缘层13与所述有源层14的厚度之和为d2,所述栅极层12的坡底处的所述栅极绝缘层13与所述有源层14的厚度之和为d3,其中,d2=0.773*d3+0.156*d3*cosA-0.061*d0。
本发明提供了一种防止ESD破坏TFT的方法,通过对测试数据进行拟合,获取TFT的抗ESD能力与每一膜层的制备参数之间的关系,即在所述栅极层12的爬坡角A的角度范围为0°-40°,且栅极层12的爬坡角A的角度越小,所述TFT的抗ESD能力越强;所述栅极绝缘层13的厚度越大,所述TFT的抗ESD能力越强。
本发明还提供一种TFT的制备方法,其包括依据本发明所述的防止ESD破坏元件的方法中得出的所述TFT的抗ESD能力与每一膜层的制备参数之间的关系设置所述TFT的膜层的制备参数。即根据ESD与TFT的膜层之间的关系设置TFT的膜层的制备参数,进而防止ESD破坏TFT。
本发明还提供一种显示面板,其包括TFT,所述TFT采用本发明所述的TFT的制备方法制备形成。
本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想;本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。
Claims (7)
1.一种防止ESD破坏TFT的方法,其特征在于,包括如下步骤:
获取多个TFT的至少一膜层的测试数据,所述测试数据包括每一膜层的制备参数以及每一膜层所能承受的静电释放电压;
将所述测试数据进行数据拟合,得到至少一拟合曲线;以及
从所述拟合曲线中获取所述TFT的抗ESD能力与每一膜层的制备参数之间的关系;
所述制备参数包括所述TFT的栅极层的爬坡角,所述栅极层的爬坡角的角度范围为0°-40°,所述栅极层的爬坡角的角度越小,所述TFT的抗ESD能力越强。
2.如权利要求1所述的防止ESD破坏TFT的方法,其特征在于,所述制备参数包括所述TFT的栅极绝缘层的厚度,所述栅极绝缘层的厚度越大,所述TFT的抗ESD能力越强。
3.如权利要求2所述的防止ESD破坏TFT的方法,其特征在于,所述栅极绝缘层的材质为无机材料。
4.如权利要求1所述的防止ESD破坏TFT的方法,其特征在于,所述TFT包括:栅极层、栅极绝缘层以及有源层;所述栅极层的厚度为d0、所述栅极层的爬坡角的角度为A,所述栅极层的坡顶处的所述栅极绝缘层与所述有源层的厚度之和为d1,所述栅极层的爬坡处的所述栅极绝缘层与所述有源层的厚度之和为d2,所述栅极层的坡底处的所述栅极绝缘层与所述有源层的厚度之和为d3,其中,d2=0.773*d3+0.156*d3*cosA-0.061*d0。
5.如权利要求1所述的防止ESD破坏TFT的方法,其特征在于,所述静电释放电压为多个TFT的同一膜层的所能承受的实际静电释放电压的平均值。
6.如权利要求1所述的防止ESD破坏TFT的方法,其特征在于,所述测试数据还包括所述TFT的击伤比或良好比;
所述击伤比为多个TFT中被静电释放电压击伤的TFT的数量相对于TFT总数的比值;
所述良好比为多个TFT中未被静电释放电压击伤的TFT数量相对于TFT总数的比值。
7.一种TFT的制备方法,其特征在于,包括:依据权利要求1-6中任一项所述的防止ESD破坏TFT的方法中得出的所述TFT的抗ESD能力与每一膜层的制备参数之间的关系设置所述TFT的膜层的制备参数。
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Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06221841A (ja) * | 1993-01-26 | 1994-08-12 | Hitachi Ltd | 積層体の膜評価法及びこれを用いた膜評価装置及び薄膜製造装置 |
JP2006349648A (ja) * | 2005-06-20 | 2006-12-28 | Toyota Industries Corp | 分光エリプソメータを用いた有機エレクトロルミネッセンス素子に用いられる有機物質の解析方法、複合膜の解析方法及び多層膜の解析方法 |
CN103308840A (zh) * | 2013-05-23 | 2013-09-18 | 上海华力微电子有限公司 | 晶圆可接受测试方法 |
CN105280633A (zh) * | 2015-11-30 | 2016-01-27 | 深圳市华星光电技术有限公司 | Tft阵列基板及其制作方法 |
CN107330200A (zh) * | 2017-07-03 | 2017-11-07 | 京东方科技集团股份有限公司 | 薄膜晶体管的耐受静电电压的确定方法及设备 |
CN107895942A (zh) * | 2017-12-05 | 2018-04-10 | 京东方科技集团股份有限公司 | Esd保护电路及方法、阵列基板、显示装置 |
CN108365013A (zh) * | 2018-02-27 | 2018-08-03 | 武汉华星光电技术有限公司 | 薄膜晶体管、阵列基板、显示面板及其制备方法、终端 |
CN109752612A (zh) * | 2018-12-29 | 2019-05-14 | 西安紫光国芯半导体有限公司 | 一种芯片esd保护电路的仿真电路和方法 |
CN109884490A (zh) * | 2019-01-09 | 2019-06-14 | 惠科股份有限公司 | 一种薄膜晶体管的检测方法和检测装置 |
CN110634843A (zh) * | 2019-08-27 | 2019-12-31 | 武汉华星光电半导体显示技术有限公司 | 薄膜晶体管及其制作方法、显示面板 |
CN112002764A (zh) * | 2020-08-11 | 2020-11-27 | Tcl华星光电技术有限公司 | Tft器件及其制备方法、tft阵列基板 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005093802A (ja) * | 2003-09-18 | 2005-04-07 | Oki Electric Ind Co Ltd | Esd保護素子のモデル化方法,esdシミュレーション方法 |
JP5140999B2 (ja) * | 2006-11-22 | 2013-02-13 | カシオ計算機株式会社 | 液晶表示装置 |
US9538169B2 (en) * | 2014-11-03 | 2017-01-03 | Denso International America, Inc. | Quality test device for inspecting vehicular display module having thin-film transistors |
WO2016139560A1 (en) * | 2015-03-03 | 2016-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Oxide semiconductor film, semiconductor device including the oxide semiconductor film, and display device including the semiconductor device |
WO2017115222A1 (en) * | 2015-12-29 | 2017-07-06 | Semiconductor Energy Laboratory Co., Ltd. | Metal oxide film and semiconductor device |
US10725098B2 (en) * | 2016-10-11 | 2020-07-28 | Esd It2 Llc. | System and method for efficient electrostatic discharge testing and analysis |
CN107978610B (zh) * | 2017-11-30 | 2020-04-24 | 上海天马微电子有限公司 | 一种阵列基板、显示面板、显示装置及阵列基板的制造方法 |
-
2021
- 2021-08-10 CN CN202110912249.XA patent/CN113690153B/zh active Active
- 2021-08-19 EP EP21801408.2A patent/EP4386817A1/en active Pending
- 2021-08-19 WO PCT/CN2021/113482 patent/WO2023015591A1/zh active Application Filing
- 2021-08-19 US US17/600,281 patent/US11942559B2/en active Active
- 2021-08-19 JP JP2021550202A patent/JP2023540409A/ja active Pending
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06221841A (ja) * | 1993-01-26 | 1994-08-12 | Hitachi Ltd | 積層体の膜評価法及びこれを用いた膜評価装置及び薄膜製造装置 |
JP2006349648A (ja) * | 2005-06-20 | 2006-12-28 | Toyota Industries Corp | 分光エリプソメータを用いた有機エレクトロルミネッセンス素子に用いられる有機物質の解析方法、複合膜の解析方法及び多層膜の解析方法 |
CN103308840A (zh) * | 2013-05-23 | 2013-09-18 | 上海华力微电子有限公司 | 晶圆可接受测试方法 |
CN105280633A (zh) * | 2015-11-30 | 2016-01-27 | 深圳市华星光电技术有限公司 | Tft阵列基板及其制作方法 |
CN107330200A (zh) * | 2017-07-03 | 2017-11-07 | 京东方科技集团股份有限公司 | 薄膜晶体管的耐受静电电压的确定方法及设备 |
CN107895942A (zh) * | 2017-12-05 | 2018-04-10 | 京东方科技集团股份有限公司 | Esd保护电路及方法、阵列基板、显示装置 |
CN108365013A (zh) * | 2018-02-27 | 2018-08-03 | 武汉华星光电技术有限公司 | 薄膜晶体管、阵列基板、显示面板及其制备方法、终端 |
CN109752612A (zh) * | 2018-12-29 | 2019-05-14 | 西安紫光国芯半导体有限公司 | 一种芯片esd保护电路的仿真电路和方法 |
CN109884490A (zh) * | 2019-01-09 | 2019-06-14 | 惠科股份有限公司 | 一种薄膜晶体管的检测方法和检测装置 |
CN110634843A (zh) * | 2019-08-27 | 2019-12-31 | 武汉华星光电半导体显示技术有限公司 | 薄膜晶体管及其制作方法、显示面板 |
CN112002764A (zh) * | 2020-08-11 | 2020-11-27 | Tcl华星光电技术有限公司 | Tft器件及其制备方法、tft阵列基板 |
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