CN113675157A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113675157A
CN113675157A CN202110503014.5A CN202110503014A CN113675157A CN 113675157 A CN113675157 A CN 113675157A CN 202110503014 A CN202110503014 A CN 202110503014A CN 113675157 A CN113675157 A CN 113675157A
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Prior art keywords
semiconductor device
circuit pattern
semiconductor element
bonded
wiring layer
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Granted
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CN202110503014.5A
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CN113675157B (zh
Inventor
北林拓也
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

对由金属导线的发热引起的半导体元件的温度上升进行抑制。半导体装置具有:印刷基板,其在上表面具有第一电路图案及第二电路图案;以及半导体元件,其配置于第一电路图案的上表面,半导体元件在上表面配置漏极电极,在下表面配置栅极电极及源极电极,栅极电极及源极电极经由第一接合材料与第一电路图案的上表面接合,漏极电极经由与半导体元件的上表面连接的金属部件与第二电路图案的上表面接合。

Description

半导体装置
技术领域
本申请说明书所公开的技术涉及半导体装置。
背景技术
就当前的半导体装置而言,例如,通过焊料等使半导体元件的漏极电极与绝缘基板的上表面处的电路图案接合,另外,经由由Al或Cu等构成的金属导线将半导体元件的源极电极及栅极电极与金属端子等连接。
另一方面,以降低制造成本为目的,正在进行半导体元件的外形尺寸的缩小化,栅极电极及源极电极的金属导线能够接合的面积有减小的倾向。
如果栅极电极及源极电极的金属导线能够接合的面积减少,则能够向源极电极进行配线的金属导线的根数减少,因此各个金属导线的发热量增加。其结果,由于金属导线的热量传播,有时半导体元件的温度会上升。
例如,专利文献1所公开的技术为用于应对这样的课题的技术,在GaN-高电子迁移率晶体管(high electron mobility transistor、即HEMT)等横向型半导体元件中提高散热效率。
专利文献1:日本特开2017-123358号公报
但是,专利文献1所示的技术涉及将源极电极和漏极电极配置于与基板平行的方向的横向型半导体元件,其存在如下问题,即,无法同样地应用于将源极电极和漏极电极配置于与基板垂直的方向的纵向型半导体元件等其它半导体元件。
发明内容
本申请说明书所公开的技术是鉴于以上所记载的问题而提出的,其是用于对由金属导线等的发热引起的半导体元件的温度上升进行抑制的技术。
本申请说明书所公开的与半导体装置相关的技术的第一方式具有:印刷基板,其在上表面具有第一电路图案及第二电路图案;以及半导体元件,其配置于所述第一电路图案的上表面,所述半导体元件在上表面配置漏极电极,在下表面配置栅极电极及源极电极,所述栅极电极及所述源极电极经由第一接合材料与所述第一电路图案的所述上表面接合,所述漏极电极经由与所述半导体元件的上表面连接的金属部件与所述第二电路图案的上表面接合。
发明的效果
本申请说明书所公开的技术的第一方式具有:印刷基板,其在上表面具有第一电路图案及第二电路图案;以及半导体元件,其配置于所述第一电路图案的上表面,所述半导体元件在上表面配置漏极电极,在下表面配置栅极电极及源极电极,所述栅极电极及所述源极电极经由第一接合材料与所述第一电路图案的所述上表面接合,所述漏极电极经由与所述半导体元件的上表面连接的金属部件与所述第二电路图案的上表面接合。根据这样的结构,能够对半导体元件的温度上升进行抑制。
另外,通过以下所示的详细的说明和附图,与本申请说明书所公开的技术关联的目的、特征、方案、优点会更清楚。
附图说明
图1是概略地表示实施方式涉及的半导体装置的结构的例子的剖视图。
图2是概略地表示实施方式涉及的半导体装置的结构的变形例的剖视图。
图3是概略地表示金属导线与栅极电极及源极电极各自连接的情况下的构造的例子的剖视图。
图4是概略地表示金属导线与栅极电极及源极电极各自连接的情况下的构造的例子的俯视图。
图5是概略地表示实施方式涉及的半导体装置的结构的例子的俯视图。
图6是概略地表示实施方式涉及的半导体装置的结构的例子的剖视图。
图7是概略地表示实施方式涉及的半导体装置的结构的例子的剖视图。
图8是概略地表示实施方式涉及的半导体装置的结构的例子的剖视图。
图9是概略地表示实施方式涉及的半导体装置的结构的例子的剖视图。
具体实施方式
以下,一边参照附图一边对实施方式进行说明。在下面的实施方式中,为了说明技术,还示出了详细的特征等,但它们是例示,是为了能够实施实施方式,并非全部都是必备的特征。
此外,附图是概略地示出的,为了方便说明,在附图中适当进行了结构的省略或结构的简化。另外,不同的附图各自所示的结构等的大小及位置的相互关系未必是准确地记载的,能够适当进行变更。另外,在并非剖视图的俯视图等附图中,为了容易理解实施方式的内容,有时添加了阴影。
另外,在以下所示的说明中,对同样的结构要素标注相同的标号而进行图示,它们的名称和功能也是同样的。因此,为了避免重复,有时会省略对它们的详细的说明。
另外,在下面所记载的说明中,在记载为“具备”、“包含”或“具有”某个结构要素等的情况下,只要没有特别说明,则不是排除其它结构要素的存在的排他性表述。
另外,在下面所记载的说明中,即使存在使用“第一”、或“第二”等序数的情况下,这些序数也只是为了容易对实施方式的内容进行理解,出于方便而使用的,并不限于通过这些序数能够产生的顺序等。
另外,在下面所记载的说明中,即使存在使用“上”、“下”、“左”、“右”、“侧”、“底”、“表”或“背”等表示特定的位置或方向的术语的情况,这些术语也只是为了容易对实施方式的内容进行理解,出于方便而使用的,与实际实施时的位置或方向无关。
另外,在下面所记载的说明中,在记载为“…的上表面”或“…的下表面”等的情况下,除了成为对象的结构要素的上表面本身或下表面本身之外,还包含在成为对象的结构要素的上表面或下表面形成有其它结构要素的状态。即,例如,在记载为“在甲的上表面设置的乙”的情况下,不妨碍其它结构要素“丙”介于甲和乙之间。
<第一实施方式>
下面,对本实施方式涉及的半导体装置进行说明。
另外,在下面的说明中,“将A和B电连接”这样的表述是指在结构A和结构B之间能够双向地流动电流。
<关于半导体装置的结构>
图1是概略地表示本实施方式涉及的半导体装置的结构的例子的剖视图。
如图1中所例示的那样,半导体装置至少具有印刷基板16、经由导电性的接合材料14B与印刷基板16的上表面接合的半导体元件18。
这里,印刷基板16具有:绝缘基板16A;电路图案16B及电路图案16E,其形成于绝缘基板16A的上表面;以及电路图案16C,其形成于绝缘基板16A的下表面。
另外,半导体元件18为金属-氧化膜-半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,即MOSFET)、结型场效应晶体管(JFET)、绝缘栅型双极晶体管(insulated gate bipolar transistor,即IGBT)、或高电子迁移率晶体管(high electron mobility transistor,即HEMT)等场效应晶体管,该半导体元件18具有:上表面的漏极电极18A;下表面的栅极电极18B,其经由接合材料14B与电路图案16B连接;以及下表面的源极电极18C,其经由接合材料14B与电路图案16B连接。另外,半导体元件18例如由Si构成。此外,在作为半导体元件18使用IGBT的情况下,将上述说明中的源极电极改称为IGBT的发射极电极,将上述说明中的漏极电极改称为IGBT的集电极(collector)电极(electrode)。
另外,半导体装置能够还具有:基座板12,其经由导电性的接合材料14A与印刷基板16的下表面接合;金属导线20,其将漏极电极18A和电路图案16E连接;金属端子24,其通过金属导线20进一步与电路图案16E连接;壳体26,其容纳这些构造;以及封装材料22,其为填充于壳体26内的凝胶或环氧树脂等。此外,基座板12的下表面在壳体26的下方露出到外部。
如果是这样的结构,则在半导体元件18处,在与金属导线20连接的上表面形成有漏极电极18A,与形成栅极电极18B及源极电极18C的面为上表面而连接金属导线20的情况相比,能够增大金属导线可接合的面积。
因此,在该面能够进行配线的金属导线20的根数变多,因此能够对各个金属导线20的发热量进行抑制。另外,金属导线20的配线位置的自由度也会提高。其结果,即使在将半导体元件18的外径尺寸缩小那样的情况下,也能够对由金属导线20的热量引起的半导体元件18的温度上升进行抑制。
另外,由于源极电极18C经由接合材料14B与电路图案16B连接,因此与通过金属导线20进行连接的情况相比,能够对半导体元件18的温度上升进行抑制。
图2是概略地表示本实施方式涉及的半导体装置的结构的变形例的剖视图。
如图2中所例示的那样,半导体装置至少具有印刷基板36、经由导电性的接合材料14B与印刷基板36的上表面接合的半导体元件18。
这里,印刷基板36具有:绝缘基板36A;配线层36B,其形成于绝缘基板36A的上表面;绝缘层36C,其局部地形成于配线层36B的上层;电路图案36D,其形成于绝缘层36C的上层;以及电路图案36E,其形成于绝缘基板36A的下层。此外,配线层36B和电路图案36D经由连接层36F电连接。
另外,半导体元件18具有:上表面的漏极电极18A;栅极电极18B,其经由接合材料14B与从绝缘层36C露出的配线层36B(即,印刷基板36的上表面处的电路图案)连接;以及源极电极18C,其经由接合材料14B与从绝缘层36C露出的配线层36B(即,印刷基板36的上表面处的电路图案)连接。
另外,半导体装置能够还具有:基座板12,其经由导电性的接合材料14A与印刷基板36的下表面接合;金属导线20,其将漏极电极18A和电路图案36D连接;金属端子24,其通过金属导线20进一步与电路图案36D连接;壳体26;以及封装材料22。此外,基座板12的下表面在壳体26的下方露出到外部。
这里,对金属导线与栅极电极18B及源极电极18C各自连接的情况下的构造、本实施方式涉及的半导体装置进行比较。
图3是概略地表示金属导线与栅极电极18B及源极电极18C各自连接的情况下的构造的例子的剖视图。
如图3中所例示的那样,半导体装置至少具有印刷基板46、经由导电性的接合材料14B与印刷基板46的上表面接合的半导体元件18。
这里,印刷基板46具有:绝缘基板16A;电路图案16D,其形成于绝缘基板16A的上表面;以及电路图案16C,其形成于绝缘基板16A的下表面。
另外,半导体元件18具有:漏极电极18A,其经由接合材料14B与电路图案16D连接;栅极电极18B;以及源极电极18C。
另外,半导体装置能够还具有:基座板12,其经由导电性的接合材料14A与印刷基板46的下表面接合;金属导线20B,其将栅极电极18B和电路图案16D连接;金属导线20A,其将源极电极18C和电路图案16D连接;金属端子24,其通过金属导线20A或金属导线20B进一步与电路图案16D连接;壳体26,其容纳这些构造;以及封装材料22,其为填充于壳体26内的凝胶或环氧树脂等。此外,基座板12的下表面在壳体26的下方露出到外部。
图4是概略地表示金属导线与栅极电极18B及源极电极18C各自连接的情况下的构造的例子的俯视图。
如图4中所例示的那样,与栅极电极18B连接的金属导线20B和与源极电极18C连接的金属导线20A作为用于对多个半导体元件18进行控制的配线而各自被绕引。伴随于此,对配线进行接合所需要的面积也会变大。另外,配线绕引的自由度也会降低。
图5是概略地表示本实施方式涉及的半导体装置的结构的例子的俯视图。
如图5中所例示的那样,与漏极电极18A连接的金属导线20作为用于对多个半导体元件18进行控制的配线而被绕引。另一方面,与栅极电极18B及源极电极18C连接的配线层36B作为用于在印刷基板36的层构造中对多个半导体元件18进行控制的配线起作用。
因此,在图5所例示的例子中,能够减少作为金属导线20而进行连接的配线的绕引。因此,在缩小半导体元件18的外径尺寸而并列配置多个的情况下,也能够不使半导体装置的外径尺寸变大地进行自由度高的恰当的配线。其结果,能够实现半导体装置的小型化。
<第二实施方式>
对本实施方式涉及的半导体装置进行说明。此外,在下面的说明中,对与以上记载的实施方式中说明过的结构要素同样的结构要素标注相同的标号而进行图示,适当省略其详细的说明。
<关于半导体装置的结构>
图6是概略地表示本实施方式涉及的半导体装置的结构的例子的剖视图。
如图6中所例示的那样,半导体装置至少具有印刷基板56、经由导电性的接合材料14B与印刷基板56的上表面接合的半导体元件18。
这里,印刷基板56具有:绝缘基板36A;配线层36G,其形成于绝缘基板36A的上层;绝缘层36C,其局部地形成于配线层36G的上层;电路图案36D,其形成于绝缘层36C的上层;以及电路图案36E,其形成于绝缘基板36A的下层。而且,配线层36G在与栅极电极18B及源极电极18C经由接合材料14B进行接合的位置处,具有在通路孔的内壁形成有镀敷层的通路孔镀敷层36H。此外,配线层36G和电路图案36D经由连接层36F电连接。另外,通路孔镀敷层36H配置于配线层36G的与栅极电极18B接合的位置、及配线层36G的与源极电极18C接合的位置中的哪一者都可以。
另外,半导体元件18具有:漏极电极18A;栅极电极18B,其经由接合材料14B与从绝缘层36C露出的通路孔镀敷层36H连接,进而与配线层36G连接;以及源极电极18C,其经由接合材料14B与从绝缘层36C露出的通路孔镀敷层36H连接,进而与配线层36G连接。
另外,半导体装置能够还具有:基座板12,其经由导电性的接合材料14A与印刷基板56的下表面接合;金属导线20,其将漏极电极18A和电路图案36D连接;金属端子24,其通过金属导线20进一步与电路图案36D连接;壳体26;以及封装材料22。此外,基座板12的下表面在壳体26的下方露出到外部。
在图6中,栅极电极18B及源极电极18C各自经由接合材料14B与通路孔镀敷层36H连接,进而与配线层36G连接。因此,在接合半导体元件18和印刷基板56时,接合材料14B进入到通路孔镀敷层36H的通路孔的内部。因此,接合材料14B和通路孔镀敷层36H的粘接面积增加,所以接合工艺稳定。另外,由于能够对半导体元件18的配线处的发热进行抑制,因此能够使半导体元件的可靠性提高。
<第三实施方式>
对本实施方式涉及的半导体装置进行说明。此外,在下面的说明中,对与以上记载的实施方式中说明过的结构要素同样的结构要素标注相同的标号而进行图示,适当省略其详细的说明。
<关于半导体装置的结构>
图7是概略地表示本实施方式涉及的半导体装置的结构的例子的剖视图。
如图7中所例示的那样,半导体装置至少具有印刷基板66、经由导电性的接合材料14B与印刷基板66的上表面接合的半导体元件18。
这里,印刷基板66具有:绝缘基板36A;配线层36G,其形成于绝缘基板36A的上层;绝缘层36C,其局部地形成于配线层36G的上层;以及电路图案36D,其形成于绝缘层36C的上层。而且,配线层36G在与栅极电极18B及源极电极18C经由接合材料14B进行接合的位置处,具有通路孔镀敷层36H。此外,配线层36G和电路图案36D经由连接层36F电连接。
另外,半导体元件18具有:漏极电极18A;栅极电极18B,其经由接合材料14B与从绝缘层36C露出的通路孔镀敷层36H连接,进而与配线层36G连接;以及源极电极18C,其经由接合材料14B与从绝缘层36C露出的通路孔镀敷层36H连接,进而与配线层36G连接。
另外,半导体装置能够还具有:基座板12,其经由散热片100粘接于印刷基板56的下表面;金属导线20,其将漏极电极18A和电路图案36D连接;金属端子24,其通过金属导线20进一步与电路图案36D连接;壳体26;以及封装材料22。此外,基座板12的下表面在壳体26的下方露出到外部。
散热片100具有:聚对苯二甲酸乙二醇酯(PET)膜102A,其经由粘接于绝缘基板36A下表面的丙烯酸粘接剂101A而被粘接;石墨片103,其配置于PET膜102A的下表面;PET膜102B,其配置于石墨片103的下表面;以及丙烯酸粘接剂101B,其粘接于PET膜102B的下表面。基座板12粘接于丙烯酸粘接剂101B的下表面。
根据图7所例示的构造,半导体元件18的散热性提高。因此,即使在半导体元件18的外径尺寸缩小的情况下,通过利用石墨片103使半导体元件18所产生的热量分散,也能够对半导体元件18的散热性的恶化进行抑制。
<第四实施方式>
对本实施方式涉及的半导体装置进行说明。此外,在下面的说明中,对与以上记载的实施方式中说明过的结构要素同样的结构要素标注相同的标号而进行图示,适当省略其详细的说明。
<关于半导体装置的结构>
图8是概略地表示本实施方式涉及的半导体装置的结构的例子的剖视图。
如图8中所例示的那样,半导体装置至少具有印刷基板66、半导体元件18。
另外,半导体装置能够还具有:基座板12,其经由散热片100粘接于印刷基板66的下表面;金属块110,其经由接合材料14C将漏极电极18A和电路图案36D连接;金属端子24,其通过金属导线20与电路图案36D连接;壳体26;以及封装材料22。此外,基座板12的下表面在壳体26的下方露出到外部。
散热片100具有丙烯酸粘接剂101A、PET膜102A、石墨片103、PET膜102B、丙烯酸粘接剂101B。基座板12粘接于丙烯酸粘接剂101B的下表面。
根据图8所例示的构造,由于与漏极电极18A及电路图案36D连接的金属块110具有比金属导线大的接合面积,因此能够使半导体元件18的散热性提高。其结果,能够实现提高半导体元件18的电流密度的设计。
<第五实施方式>
对本实施方式涉及的半导体装置进行说明。此外,在下面的说明中,对与以上记载的实施方式中说明过的结构要素同样的结构要素标注相同的标号而进行图示,适当省略其详细的说明。
<关于半导体装置的结构>
图9是概略地表示本实施方式涉及的半导体装置的结构的例子的剖视图。
如图9中所例示的那样,半导体装置至少具有印刷基板76、经由导电性的接合材料14B与印刷基板76的上表面接合的半导体元件18。
这里,印刷基板76具有:绝缘基板36A;配线层36J,其形成于绝缘基板36A的上层;绝缘层36C,其局部地形成于配线层36J的上层;以及电路图案36D,其形成于绝缘层36C的上层。而且,配线层36J在与栅极电极18B及源极电极18C经由接合材料14B进行接合的位置处,具有通路孔镀敷层36H。此外,配线层36J和电路图案36D经由连接层36F电连接。
另外,半导体元件18具有:漏极电极18A;栅极电极18B,其经由接合材料14B与从绝缘层36C露出的通路孔镀敷层36H连接,进而与配线层36J连接;以及源极电极18C,其经由接合材料14B与从绝缘层36C露出的通路孔镀敷层36H连接,进而与配线层36J连接。
另外,半导体装置能够还具有:基座板12,其经由散热片100粘接于印刷基板76的下表面;金属块110,其经由接合材料14C将漏极电极18A和电路图案36D连接;金属端子24A,其经由接合材料14D与在绝缘层36C的侧方露出的配线层36J连接;壳体26A;以及封装材料22。此外,基座板12的下表面在壳体26A的下方露出到外部。
散热片100具有丙烯酸粘接剂101A、PET膜102A、石墨片103、PET膜102B、丙烯酸粘接剂101B。基座板12粘接于丙烯酸粘接剂101B的下表面。
根据图9所例示的构造,由于金属端子24A和配线层36J经由接合材料14D连接,因此不需要形成用于连接金属导线的图案。因此,能够将用于搭载半导体元件18的面积确保得大,能够实现半导体装置的小型化。
<第六实施方式>
对本实施方式涉及的半导体装置进行说明。此外,在下面的说明中,对与以上记载的实施方式中说明过的结构要素同样的结构要素标注相同的标号而进行图示,适当省略其详细的说明。
<关于半导体装置的结构>
在以上所记载的实施方式中说明过的半导体装置能够具有在Tj=175℃以上时剥离强度大于或等于常温的70%的印刷基板。
通过配备具有上述那样的耐热性的树脂材料等的印刷基板,能够使高温环境下的半导体装置的可靠性提高。
<第七实施方式>
对本实施方式涉及的半导体装置进行说明。此外,在下面的说明中,对与以上记载的实施方式中说明过的结构要素同样的结构要素标注相同的标号而进行图示,适当省略其详细的说明。
<关于半导体装置的结构>
在以上所记载的实施方式中说明过的半导体装置能够具有由碳化硅(SiC)构成的半导体元件18。这里,碳化硅(SiC)为宽带隙半导体的一种。宽带隙半导体通常是指具有大约大于或等于2eV的禁带宽度的半导体,已知存在氮化镓(GaN)等3族氮化物、氧化锌(ZnO)等2族氧化物、硒化锌(ZnSe)等2族硫系化合物、金刚石及碳化硅等。
在半导体装置所具有的半导体元件由SiC构成的情况下,由于与Si等相比SiC能够进行高温动作,因此能够实现半导体元件的小型化及多个并列化。其结果,能够实现半导体装置的小型化。
<关于通过以上所记载的实施方式产生的效果>
下面,示出由以上所记载的实施方式产生的效果的例子。此外,在下面的说明中,基于在以上所记载的实施方式中所例示的具体的结构记载该效果,但在产生同样的效果的范围内,也可以与在本申请说明书中所例示的其它具体的结构进行替换。
另外,该替换也可以横跨多个实施方式而进行。即,也可以是对在不同的实施方式中所例示的各个结构进行组合而产生同样效果。
根据以上所记载的实施方式,半导体装置具有印刷基板、半导体元件18。这里,印刷基板例如与印刷基板16、印刷基板36、印刷基板56、印刷基板66及印刷基板76等中的任意1者对应(下面,为了方便,有时以对应它们中的任意1者的方式进行记载)。印刷基板16在上表面具有第一电路图案及第二电路图案。这里,第一电路图案例如与电路图案16B、配线层36B、通路孔镀敷层36H、配线层36G及配线层36J等中的任意1者对应(下面,为了方便,有时以对应它们中的任意1者的方式进行记载)。另外,第二电路图案例如与电路图案16E及电路图案36D等中的任意1者对应(下面,为了方便,有时以对应它们中的任意1者的方式进行记载)。半导体元件18配置于电路图案16B的上表面。半导体元件18在上表面配置漏极电极18A。另外,半导体元件18在下表面配置栅极电极18B及源极电极18C。栅极电极18B及源极电极18C经由第一接合材料与电路图案16B的上表面接合。这里,第一接合材料例如与接合材料14B等对应。漏极电极18A经由与半导体元件18的上表面连接的金属部件与第二电路图案的上表面接合。这里,金属部件例如与金属导线20及金属块110等中的任意1者对应(下面,为了方便,有时以对应它们中的任意1者的方式进行记载)。另外,第二电路图案例如与电路图案16E及电路图案36D等中的任意1者对应(下面,为了方便,有时以对应它们中的任意1者的方式进行记载)。
根据这样的结构,能够对半导体元件18的温度上升进行抑制。具体而言,在半导体元件18处在与金属导线20(或金属块110)连接的面形成有漏极电极18A,与金属导线20连接于形成栅极电极18B及源极电极18C的面的情况相比,能够增大金属导线可接合的面积。因此,在该面能够进行配线的金属导线20的根数多(或者,能够连接金属块110),所以能够对各个金属导线20(或者,金属块110)的发热量进行抑制。另外,金属导线20的配线位置的自由度也会提高。其结果,即使在以改善成品率为目的而将半导体元件18的外径尺寸缩小那样的情况下(即,将源极电极的面积缩小那样的情况下),也能够对由金属导线20的热量引起的半导体元件18的温度上升进行抑制。另外,由于源极电极18C经由接合材料14B与电路图案16B连接,因此与通过金属导线20进行连接的情况相比,能够对半导体元件18的温度上升进行抑制。因此,能够在半导体元件18的上下表面对配线的温度上升进行抑制,所以其结果,能够对半导体元件18的温度上升进行抑制。
此外,在向上述结构适当追加了本申请说明书中所例示的其它结构的情况下,即适当追加了没有作为上述结构提及的本申请说明书中的其它结构的情况下,也能够产生相同的效果。
另外,根据以上所记载的实施方式,印刷基板36具有:绝缘基板36A;配线层,其配置于绝缘基板36A的上表面;以及绝缘层36C,其局部地配置于配线层的上表面。这里,配线层例如与配线层36B、配线层36G及配线层36J等中的任意1者对应(下面,为了方便,有时以对应它们中的任意1者的方式进行记载)。第一电路图案是没有被绝缘层36C覆盖而在多个位置露出的配线层36B中的一部分。另外,第二电路图案是配置于绝缘层36C的上表面的电路图案36D。根据这样的结构,能够减少作为金属导线20而进行连接的配线的绕引。因此,在缩小半导体元件18的外径尺寸而并列配置多个的情况下,也能够不使半导体装置的外径尺寸变大地进行自由度高的恰当的配线。其结果,能够实现半导体装置的小型化。
另外,根据以上所记载的实施方式,配线层36G在与栅极电极18B及源极电极18C中的至少一者经由接合材料14B进行接合的位置处具有通路孔镀敷层36H。根据这样的结构,在接合半导体元件18和印刷基板56时,接合材料14B进入到通路孔镀敷层36H的通路孔的内部。因此,接合材料14B和通路孔镀敷层36H的粘接面积增加,所以接合工艺稳定。另外,由于能够对半导体元件18的配线处的发热进行抑制,因此能够使半导体元件的可靠性提高。
另外,根据以上所记载的实施方式,配线层36J从绝缘基板36A的侧面露出。而且,半导体装置具有经由第二接合材料与从绝缘基板36A的侧面露出的配线层36J接合的金属端子24A。这里,第二接合材料例如与接合材料14D对应。根据这样的结构,由于金属端子24A和配线层36J经由接合材料14D连接,因此不需要形成用于连接金属导线的图案。因此,能够将用于搭载半导体元件18的面积确保得大,能够实现半导体装置的小型化。
另外,根据以上所记载的实施方式,半导体装置具有:散热片100,其粘接于印刷基板66(或者,印刷基板76)的下表面;以及基座板12,其粘接于散热片100的下表面。散热片100具有第一PET膜、石墨片103、第二PET膜。这里,第一PET膜例如与PET膜102A对应。另外,第二PET膜例如与PET膜102B对应。PET膜102A经由第一粘接剂粘接于印刷基板66(或者,印刷基板76)的下表面。这里,第一粘接剂例如与丙烯酸粘接剂101A对应。石墨片103配置于PET膜102A的下表面。PET膜102B配置于石墨片103的下表面。另外,PET膜102B经由第二粘接剂粘接于基座板12的上表面。这里,第二粘接剂例如与丙烯酸粘接剂101B等对应。根据这样的结构,半导体元件18的散热性提高。因此,即使在半导体元件18的外径尺寸缩小的情况下,通过利用石墨片103使半导体元件18所产生的热量分散,也能够对半导体元件18的散热性的恶化进行抑制。
另外,根据以上所记载的实施方式,印刷基板16在大于或等于175℃时剥离强度大于或等于常温的70%。根据这样的结构,能够使高温环境下的半导体装置的可靠性提高。
另外,根据以上所记载的实施方式,半导体元件18由SiC构成。根据这样的结构,由于与Si等相比SiC能够进行高温动作,因此能够实现半导体元件的小型化及多个并列化。其结果,能够实现半导体装置的小型化。
另外,根据以上所记载的实施方式,金属部件为金属导线20。
根据这样的结构,在半导体元件18处在与金属导线20连接的面形成有漏极电极18A,与金属导线20连接于形成栅极电极18B及源极电极18C的面的情况相比,能够增大金属导线可接合的面积。因此,在该面能够进行配线的金属导线20的根数变多,所以能够对各个金属导线20的发热量进行抑制。
另外,根据以上所记载的实施方式,金属部件为金属块110。根据这样的结构,由于与漏极电极18A及电路图案36D连接的金属块110具有比金属导线大的接合面积,因此能够使半导体元件18的散热性提高。其结果,能够实现提高半导体元件18的电流密度的设计。
<关于以上所记载的实施方式的变形例>
在以上所记载的实施方式中,有时记载了各个结构要素的材质、材料、尺寸、形状、相对的配置关系或实施条件等,但这些在所有方面只是一个例子,并不是限定性的内容。
因此,在本申请说明书所公开的技术范围内可想象到没有示出例子的无数的变形例及均等物。例如,包含将至少1个结构要素变形的情况、追加的情况或省略的情况,以及,提取至少1个实施方式中的至少1个结构要素而与其它实施方式中的结构要素进行组合的情况。
另外,在以上所记载的实施方式中,在没有特别指定地记载了材料名等的情况下,只要不产生矛盾,则包括在该材料中包含其它添加物的例如合金等。
另外,只要不产生矛盾,在以上所记载的实施方式中记载为具备“1个”的结构要素,也可以具备“大于或等于1个”。
而且,以上所记载的实施方式中的各个结构要素是概念性的单位,在本申请说明书所公开的技术范围内,包含1个结构要素由多个构造物构成的情况、1个结构要素与某个构造物的一部分对应的情况以及1个构造物具有多个结构要素的情况。
另外,对于以上所记载的实施方式中的各个结构要素,只要发挥相同的功能,则包含具有其它构造或形状的构造物。
另外,本申请说明书中的说明是用于与本技术关联的全部目的而参照的,均没有承认是现有技术。
标号的说明
12基座板,14A、14B、14C、14D接合材料,16、36、46、56、66、76印刷基板,16A、36A绝缘基板,16B、16C、16D、16E、36D、36E电路图案,18半导体元件,18A漏极电极,18B栅极电极,18C源极电极,20、20A、20B金属导线,22封装材料,24、24A金属端子,26、26A壳体,36C绝缘层,36F连接层,36H通路孔镀敷层,36B、36G、36J配线层,100散热片,101A、101B丙烯酸粘接剂,102A、102B PET膜,103石墨片,110金属块。

Claims (9)

1.一种半导体装置,其具有:
印刷基板,其在上表面具有第一电路图案及第二电路图案;以及
半导体元件,其配置于所述第一电路图案的上表面,
所述半导体元件在上表面配置漏极电极,在下表面配置栅极电极及源极电极,
所述栅极电极及所述源极电极经由第一接合材料与所述第一电路图案的所述上表面接合,
所述漏极电极经由与所述半导体元件的上表面连接的金属部件与所述第二电路图案的上表面接合。
2.根据权利要求1所述的半导体装置,其中,
所述印刷基板具有:
绝缘基板;
配线层,其配置于所述绝缘基板的上表面;以及
绝缘层,其局部地配置于所述配线层的上表面,
所述第一电路图案是没有被所述绝缘层覆盖而在多个位置露出的所述配线层中的一部分,
所述第二电路图案配置于所述绝缘层的上表面。
3.根据权利要求2所述的半导体装置,其中,
所述配线层在与所述栅极电极及所述源极电极中的至少一者经由所述第一接合材料进行接合的位置处具有镀敷层。
4.根据权利要求2或3所述的半导体装置,其中,
所述配线层从所述绝缘基板的侧面露出,
所述半导体装置还具有金属端子,该金属端子经由第二接合材料与从所述绝缘基板的所述侧面露出的所述配线层接合。
5.根据权利要求1至4中任一项所述的半导体装置,其中,
所述半导体装置还具有:
散热片,其粘接于所述印刷基板的下表面;以及
基座板,其粘接于所述散热片的下表面,
所述散热片具有:
第一PET膜,其经由第一粘接剂粘接于所述印刷基板的所述下表面;
石墨片,其配置于所述第一PET膜的下表面;以及
第二PET膜,其配置于所述石墨片的下表面,并且经由第二粘接剂粘接于所述基座板的上表面。
6.根据权利要求1至5中任一项所述的半导体装置,其中,
所述印刷基板在大于或等于175℃时剥离强度大于或等于常温的70%。
7.根据权利要求1至6中任一项所述的半导体装置,其中,
所述半导体元件由SiC构成。
8.根据权利要求1至7中任一项所述的半导体装置,其中,
所述金属部件为金属导线。
9.根据权利要求1至7中任一项所述的半导体装置,其中,
所述金属部件为金属块。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220181310A1 (en) * 2019-05-24 2022-06-09 Rohm Co., Ltd. Semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007012913A (ja) * 2005-06-30 2007-01-18 Polymatech Co Ltd 放熱シート及び放熱構造
US20090227070A1 (en) * 2008-03-07 2009-09-10 Denso Corporation Semiconductor device and method of manufacturing the same
JP2013073945A (ja) * 2011-09-26 2013-04-22 Sumitomo Electric Ind Ltd 配線シート付き電極端子、配線構造体、半導体装置、およびその半導体装置の製造方法
JP2014170799A (ja) * 2013-03-01 2014-09-18 Sumitomo Electric Ind Ltd 半導体装置
US20160086876A1 (en) * 2014-09-23 2016-03-24 Infineon Technologies Ag Electronic Component
JP2019080016A (ja) * 2017-10-27 2019-05-23 三菱電機株式会社 回路基板収納筐体

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3759131B2 (ja) * 2003-07-31 2006-03-22 Necエレクトロニクス株式会社 リードレスパッケージ型半導体装置とその製造方法
JP4445351B2 (ja) * 2004-08-31 2010-04-07 株式会社東芝 半導体モジュール
US7598603B2 (en) * 2006-03-15 2009-10-06 Infineon Technologies Ag Electronic component having a power switch with an anode thereof mounted on a die attach region of a heat sink
DE102006060484B4 (de) * 2006-12-19 2012-03-08 Infineon Technologies Ag Halbleiterbauelement mit einem Halbleiterchip und Verfahren zur Herstellung desselben
US8441109B2 (en) * 2007-01-25 2013-05-14 Alpha And Omega Semiconductor Ltd. Structure and method for self protection of power device with expanded voltage ranges
JP6057926B2 (ja) * 2014-01-09 2017-01-11 三菱電機株式会社 半導体装置
US9373566B2 (en) * 2014-03-19 2016-06-21 Infineon Technologies Austria Ag High power electronic component with multiple leadframes
CN105981168B (zh) * 2014-08-28 2018-10-16 富士电机株式会社 功率半导体模块
DE102014115847B4 (de) * 2014-10-30 2018-03-08 Infineon Technologies Ag Verfahren zur Herstellung eines Leistungshalbleitermoduls
JP6488938B2 (ja) * 2015-08-04 2019-03-27 株式会社デンソー 電子装置の製造方法
JP6655992B2 (ja) 2016-01-04 2020-03-04 京セラ株式会社 パワーモジュール
JP2020013877A (ja) * 2018-07-18 2020-01-23 太陽誘電株式会社 半導体モジュール
JP7238330B2 (ja) * 2018-10-18 2023-03-14 富士電機株式会社 半導体装置及び半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007012913A (ja) * 2005-06-30 2007-01-18 Polymatech Co Ltd 放熱シート及び放熱構造
US20090227070A1 (en) * 2008-03-07 2009-09-10 Denso Corporation Semiconductor device and method of manufacturing the same
JP2013073945A (ja) * 2011-09-26 2013-04-22 Sumitomo Electric Ind Ltd 配線シート付き電極端子、配線構造体、半導体装置、およびその半導体装置の製造方法
JP2014170799A (ja) * 2013-03-01 2014-09-18 Sumitomo Electric Ind Ltd 半導体装置
US20160086876A1 (en) * 2014-09-23 2016-03-24 Infineon Technologies Ag Electronic Component
JP2019080016A (ja) * 2017-10-27 2019-05-23 三菱電機株式会社 回路基板収納筐体

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