CN113644116A - 栅极与源极并联可调电阻型超结功率器件及其制造方法 - Google Patents
栅极与源极并联可调电阻型超结功率器件及其制造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 108
- 239000002184 metal Substances 0.000 claims abstract description 108
- 238000002161 passivation Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 95
- 238000000034 method Methods 0.000 claims description 87
- 238000000151 deposition Methods 0.000 claims description 50
- 229920002120 photoresistant polymer Polymers 0.000 claims description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 238000001312 dry etching Methods 0.000 claims description 35
- 238000001259 photo etching Methods 0.000 claims description 30
- 229920005591 polysilicon Polymers 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 210000000746 body region Anatomy 0.000 claims description 27
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 27
- 229910052721 tungsten Inorganic materials 0.000 claims description 27
- 239000010937 tungsten Substances 0.000 claims description 27
- 239000012535 impurity Substances 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 16
- 239000012212 insulator Substances 0.000 claims description 15
- 238000001039 wet etching Methods 0.000 claims description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 14
- 229910052796 boron Inorganic materials 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 13
- 229910052698 phosphorus Inorganic materials 0.000 claims description 13
- 239000011574 phosphorus Substances 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 12
- 229910052785 arsenic Inorganic materials 0.000 claims description 11
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 11
- 230000003213 activating effect Effects 0.000 claims description 10
- 230000001413 cellular effect Effects 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 239000005749 Copper compound Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 239000012790 adhesive layer Substances 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 5
- 238000006731 degradation reaction Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000002131 composite material Substances 0.000 description 6
- 210000004027 cell Anatomy 0.000 description 4
- IWZSHWBGHQBIML-ZGGLMWTQSA-N (3S,8S,10R,13S,14S,17S)-17-isoquinolin-7-yl-N,N,10,13-tetramethyl-2,3,4,7,8,9,11,12,14,15,16,17-dodecahydro-1H-cyclopenta[a]phenanthren-3-amine Chemical compound CN(C)[C@H]1CC[C@]2(C)C3CC[C@@]4(C)[C@@H](CC[C@@H]4c4ccc5ccncc5c4)[C@@H]3CC=C2C1 IWZSHWBGHQBIML-ZGGLMWTQSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Abstract
本发明涉及功率器件半导体制造领域,公开了一种栅极与源极并联可调电阻型超结功率器件的制造方法,包括如下步骤:A、超结型功率器件元胞结构和栅极、源极之间并联可调电阻结构的制备;B、接触孔的制备;C、金属导线的制备;D、钝化层的制备;还公开了由上述制造方法制备得到的栅极与源极并联可调电阻型超结功率器件。本发明,将功率器件应用中需要通过外接的形式并联在栅极和源极间的电阻直接集成在功率器件中,提高了器件集成度和稳定性,简化了电路设计的复杂度节省了电路设计和制造成本,避免了因不同的栅极与源极之间并联电阻应用需求导致的栅极、接触通孔、金属导线层版图变更和重新制作掩模版,减少成本支出,提高器件的通用性。
Description
技术领域
本发明涉及功率器件半导体制造领域,具体是一种栅极与源极并联可调电阻型超结功率器件及其制造方法。
背景技术
超结型功率器件相较传统功率器件中引入超结结构在达到相同耐压前提下将导通电阻下降50%~65%,有效降低功耗提高了系统产品的效率,尤其在大功率的电源产品上,其优势表现得更为突出。
超结型功率器件在电路应用中需要在栅极和源极之间额外并联一颗电阻来避免电路中的漏电流引起的功率器件误开启,同时作为栅极的静电保护结构保护栅极免受外来静电的损伤,然而这种结构通过增加额外的并联电阻会导致电路设计和制造成本增加,同时会引入因电路制造过程异常引起的电阻失效风险,另外该并联电阻会按照电路性能需求而使用不同的阻值,采用固定阻值的电阻会降低电路的通用性,因此,需要进一步的改进。
发明内容
本发明的目的在于提供一种栅极与源极并联可调电阻型超结功率器件及其制造方法,以解决上述背景技术中提出的问题。
为实现上述目的,本发明提供如下技术方案:
一种栅极与源极并联可调电阻型超结功率器件的制造方法,包括如下步骤:
A、超结型功率器件元胞结构和栅极、源极之间并联可调电阻结构的制备;
B、接触孔的制备;
C、金属导线的制备;
D、钝化层的制备。
作为本发明进一步的方案:步骤A具体包括如下步骤:
步骤S1、在硅衬底上表面化学气相沉积一层本征外延层;通过离子注入在所述本征外延层掺杂五价元素;
步骤S2、在所述本征外延层的上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;
步骤S3、通过光刻工艺在掩膜上定义柱状掺杂区图形;通过离子注入在所述本征外延层掺杂三价元素;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
步骤S4、重复步骤S1-S3;
步骤S5、通过热氧化方法对生长栅极氧化层,然后通过低压化学气象淀积原位掺杂的栅极多晶硅;
步骤S6、在所述栅极多晶硅上面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义栅极图形,然后通过干法蚀刻形成栅极结构;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
栅极图形定义元胞区金属氧化物场效应晶体管的栅极图形和栅极与源极之间并联可调电阻结构的图形,所述栅极与源极之间并联可调电阻结构的可调范围介于5千欧姆与20千欧姆间,通过设计独立的1-10um线宽的栅极与源极之间并联可调电阻图形,平行并联2个到5个独立的栅极与源极之间并联可调电阻来实现;
步骤S7、在本征外延层上表面通过离子注入三价元素杂质得到体区,同时离子注入到多晶硅上,然后通过热工艺对体区的杂质进行激活;
步骤S8、在本征外延层上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义源区图形,通过离子注入五价元素杂质在体区上表面得到源极,同时用掩膜阻挡多晶硅电阻结构区域被离子注入五价元素杂质,然后通过干蚀刻搭配湿法蚀刻去除掩膜,再通过热工艺对源区的杂质进行激活;
步骤S9、在本征外延层上表面通过离子注入三价元素得到高掺杂的欧姆接触区,同时离子注入三价元素到多晶硅电阻结构区域,最终得到元胞结构和栅极与源极之间并联可调电阻结构。
作为本发明进一步的方案:步骤S1、S3、S7、S8和S9中所述三价元素包括硼元素,所述五价元素包括砷、磷。
作为本发明进一步的方案:步骤S4中每重复步骤S1-S3均按照器件设计需求单独定义三价元素和五价元素离子注入的工艺条件至本征外延层总的厚度为30um-70um。
作为本发明进一步的方案:步骤S5中所述栅极氧化层的厚度为50~200nm;所述步骤S5中所述栅极多晶硅的厚度为500~1000nm。
作为本发明进一步的方案:步骤B具体包括如下步骤:
步骤S10、通过化学气象淀积形成二氧化硅介质层;
步骤S11、通过光刻工艺使用光刻胶定义源区接触孔图形、栅极区域接触孔图形和栅极与源极之间并联可调电阻结构的栅极端接触孔图形和源极端接触孔图形;所述源区接触孔图形位于源极和体区的上方,用于将源极和体区一同引出;所述栅极区域接触孔图形位于栅极多晶硅的上方,同时在源区中定义没有源区接触孔的区域用于放置栅极金属导线;所述栅极与源极之间并联可调电阻结构的栅极端接触孔和源极端接触孔位于栅极与源极之间并联可调电阻结构的上方,用于栅极和源极与栅极与源极之间并联可调电阻结构并联;
步骤S12、通过干法蚀刻二氧化硅介质层,得到源区接触孔、栅极区域接触孔和栅极与源极之间并联可调电阻结构的栅极端接触孔和源极端接触孔;
步骤S13、通过物理气象淀积工艺淀积金属作为粘合层,淀积金属氮化物作为阻挡层,再利用快速热退化工艺形成硅化物,所述金属包括钛、钴、钽中的一种或多种;
步骤S14、通过钨栓工艺淀积金属钨,通过干法刻蚀方法去除掉接触孔以外的金属钨,在源区接触孔、栅极区域接触孔和栅极与源极之间并联可调电阻结构的接触孔中形成钨栓。
作为本发明进一步的方案:步骤C具体包括如下步骤:
步骤S15、在钨栓上方通过物理气象淀积铝铜化合物,通过光刻工艺使用光刻胶定义源极金属导线图形、栅极金属导线图形和栅极与源极之间并联可调电阻控制极图形;通过干法蚀刻得到源极、栅极、栅极与源极之间并联可调电阻控制极;
所述源极金属导线图形位于源区上方;
所述栅极金属导线图形通过围绕着元胞区边缘走线将栅极经由栅极区域接触孔互联至源区无源区接触孔的区域形成栅极金属块;
所述栅极与源极之间并联可调电阻控制极图形通过该可调电阻的栅极端接触孔与独立的栅极与源极之间并联可调电阻结构连接,同时在每个独立的栅极与源极之间并联可调电阻与栅极金属导线之间引出独立的栅极与源极之间并联可调电阻控制极,该控制极数量与设计的独立的栅极与源极之间并联可调电阻数量一一对应,钨栓会填充到体区/源区接触孔、栅极互联区域接触孔、并联可调电阻栅极端接触孔和并联可调电阻源极端接触孔中。
作为本发明进一步的方案:步骤S15中所述栅极与源极之间并联可调电阻控制极图形会将在可调电阻栅极端接触孔连接金属导线与独立的栅极与源极之间并联可调电阻控制极金属导线交汇点之后的用于与栅极金属导线互联的金属导线局部线宽设计为1~2um。
作为本发明进一步的方案:步骤D具体包括如下步骤:
步骤S16、淀积钝化层,通过光刻工艺使用光刻胶定义源极金属接触区、栅极金属接触区和栅极与源极之间并联可调电阻控制极接触区;
通过干法蚀刻得到源极金属接触区、栅极金属接触区、栅极与源极之间并联可调电阻控制极接触区;栅极与源极之间并联可调电阻控制极接触区数量与独立栅极与源极之间并联可调电阻数量一一对应;
所述钝化层包括氮化硅或二氧化硅;
第一型掺杂和第二型掺杂为相反掺杂类型,第一型为N型则第二型为P型,第一型为P型则第二型为N型。
一种栅极与源极并联可调电阻的超结型功率器件,由上述所述的栅极与源极并联可调电阻型超结功率器件的制造方法制备得到。
与现有技术相比,本发明的有益效果是:
(1)、通过将功率器件应用中需要通过外接的形式并联在栅极和源极间的电阻直接集成在功率器件中,提高了器件集成度和稳定性,简化了电路设计的复杂度节省了电路设计和制造成本;
(2)、通过栅极与源极之间并联可调电阻控制极分别对每个独立的栅极与源极之间并联可调电阻进行开路控制以实现对栅极与源极之间并联可调电阻阻值的调整,进一步提高器件的应用范围;
(3)、通过栅极与源极之间引入电阻控制极分别对每个独立的栅极与源极之间并联电阻进行开路控制以实现对栅极与源极之间并联电阻的阻值调整,避免了因不同的栅极与源极之间并联电阻应用需求导致的栅极、接触通孔、金属导线层版图变更和重新制作掩模版,减少成本支出,提高器件的通用性。
附图说明
图1为栅极与源极并联可调电阻型超结功率器件的结构示意图。
图2为栅极与源极并联可调电阻型超结功率器件中栅极金属导线的剖面结构示意图。
图中:1、硅衬底;2、本征外延层;3、柱状掺杂区;4、可调电阻控制极;5、源极;6、栅极;7、栅极氧化层;8、栅极多晶硅;9、体区;10、源区;11、并联可调电阻;12、二氧化硅介质层;13、欧姆接触区;14、体区/源区接触孔;15、栅极区域接触孔;16、栅极端接触孔;17、源极端接触孔;18、钨栓;19、铝铜化合物;20、钝化层;21、栅极金属导线。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
实施例1
请参阅图1和图2,本发明实施例中,一种栅极与源极并联可调电阻型超结功率器件的制造方法,包括如下步骤:
步骤S1、在硅衬底1上表面化学气相沉积一层本征外延层2;通过离子注入在所述本征外延层2掺杂五价元素;所述五价元素包括砷、磷,本实施例具体为砷元素。
步骤S2、在所述本征外延层2的上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构。
步骤S3、通过光刻工艺在掩膜上定义柱状掺杂区3图形;通过离子注入在所述本征外延层2掺杂三价元素硼元素;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
步骤S4、重复步骤S1-S3至本征外延层2总的厚度为50um;步骤S4中每重复步骤S1-S3均按照器件设计需求单独定义三价元素和五价元素离子注入的工艺条件。
步骤S5、通过热氧化方法对生长栅极氧化层7,然后通过低压化学气象淀积原位掺杂的栅极多晶硅8;所述栅极氧化层7的厚度为80nm;所述栅极多晶硅8的厚度为700nm。
步骤S6、在所述栅极多晶硅8上面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义栅极6图形,然后通过干法蚀刻形成栅极6结构;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
定义元胞区金属氧化物场效应晶体管的栅极6图形和栅极6与源极5之间并联可调电阻11结构的图形,所述栅极6与源极5之间并联可调电阻11结构的可调范围介于7千欧姆与20千欧姆间,通过设计独立的5um线宽的栅极6与源极5之间并联可调电阻11图形,平行并联3个独立的栅极6与源极5之间并联可调电阻11来实现。
步骤S7、在本征外延层2上表面通过离子注入三价元素杂质得到体区9,所述三价元素包括硼,同时离子注入到多晶硅上,然后通过热工艺对体区9的杂质进行激活;
步骤S8、在本征外延层2上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义源区10图形,通过离子注入五价元素杂质在体区9上表面得到源极5,所述五价元素包括砷、磷,本实施例具体为砷元素,同时用掩膜阻挡多晶硅电阻结构区域被离子注入五价元素杂质,然后通过干蚀刻搭配湿法蚀刻去除掩膜,再通过热工艺对源区10的杂质进行激活;
步骤S9、在本征外延层2上表面通过离子注入三价元素硼元素得到高掺杂的欧姆接触区13,同时离子注入三价元素到多晶硅电阻结构区域,最终得到元胞结构和栅极6与源极5之间并联可调电阻11结构。
步骤S10、通过化学气象淀积形成二氧化硅介质层12;
步骤S11、通过光刻工艺使用光刻胶定义源区接触孔14图形、栅极区域接触孔15图形和栅极6与源极5之间并联可调电阻11结构的栅极端接触孔16图形和源极端接触孔17图形;所述源区接触孔14图形位于源极5和体区9的上方,用于将源极5和体区9一同引出;所述栅极区域接触孔15图形位于栅极多晶硅8的上方,同时在源区10中定义没有源区接触孔14的区域用于放置栅极金属导线21;所述栅极6与源极5之间并联可调电阻11结构的栅极端接触孔16和源极端接触孔17位于栅极6与源极5之间并联可调电阻11结构的上方,用于栅极6和源极5与栅极6与源极5之间并联可调电阻11结构并联;
步骤S12、通过干法蚀刻二氧化硅介质层12,得到源区接触孔14、栅极区域接触孔15和栅极6与源极5之间并联可调电阻11结构的栅极端接触孔16和源极端接触孔17;
步骤S13、通过物理气象淀积工艺淀积金属作为粘合层,淀积金属氮化物作为阻挡层,再利用快速热退化工艺形成硅化物,所述金属包括钛、钴、钽中的一种或多种;本实施例具体为金属钛。
步骤S14、通过钨栓18工艺淀积金属钨,通过干法刻蚀方法去除掉接触孔以外的金属钨,在源区接触孔14、栅极区域接触孔15和栅极6与源极5之间并联可调电阻11结构的接触孔中形成钨栓18。
步骤S15、在钨栓18上方通过物理气象淀积铝铜化合物19,通过光刻工艺使用光刻胶定义源极5金属导线图形、栅极金属导线21图形和栅极6与源极5之间并联可调电阻11结构控制极图形;通过干法蚀刻得到源极5、栅极6、栅极6与源极5之间并联可调电阻控制极4;
所述源极5金属导线图形位于源区10上方;
所述栅极金属导线21图形通过围绕着元胞区边缘走线将栅极6经由栅极区域接触孔15互联至源区10无源区10接触孔的区域形成栅极金属导线21;
所述栅极6与源极5之间并联可调电阻控制极4图形通过该可调电阻的栅极端接触孔16与独立的栅极6与源极5之间并联可调电阻11结构连接,同时在每个独立的栅极6与源极5之间并联可调电阻11与栅极金属导线21之间引出独立的栅极6与源极5之间并联可调电阻控制极4,该控制极数量与设计的独立的栅极6与源极5之间并联可调电阻11数量一一对应。
步骤S15中所述栅极6与源极5之间并联可调电阻控制极4图形会将在可调电阻栅极端接触孔16的金属导线与独立的栅极6与源极5之间并联可调电阻控制极4金属导线交汇点之后的用于与栅极金属导线21互联的金属导线局部线宽设计为1.5um。
步骤S16、淀积钝化层20,通过光刻工艺使用光刻胶定义源极5金属接触区、栅极6金属接触区和栅极6与源极5之间并联可调电阻控制极4接触区;
通过干法蚀刻得到源极5金属接触区、栅极6金属接触区、栅极6与源极5之间并联可调电阻控制极4接触区;栅极6与源极5之间并联可调电阻控制极4接触区数量与独立栅极6与源极5之间并联可调电阻11数量一一对应;所述钝化层20为氮化硅。
最终得到一种栅极与源极并联可调电阻型超结型功率器件。
实施例2
请参阅图1和图2,本发明实施例中,一种栅极与源极并联可调电阻型超结功率器件的制造方法,包括如下步骤:
步骤S1、在硅衬底1上表面化学气相沉积一层本征外延层2;通过离子注入在所述本征外延层2掺杂五价元素;所述五价元素包括砷、磷,本实施例具体为磷元素。
步骤S2、在所述本征外延层2的上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构。
步骤S3、通过光刻工艺在掩膜上定义柱状掺杂区3图形;通过离子注入在所述本征外延层2掺杂三价元素硼元素;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
步骤S4、重复步骤S1-S3至本征外延层2总的厚度为60um;步骤S4中每重复步骤S1-S3均按照器件设计需求单独定义三价元素和五价元素离子注入的工艺条件。
步骤S5、通过热氧化方法对生长栅极氧化层7,然后通过低压化学气象淀积原位掺杂的栅极多晶硅8;所述栅极氧化层7的厚度为100nm;所述栅极多晶硅8的厚度为600nm。
步骤S6、在所述栅极多晶硅8上面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义栅极6图形,然后通过干法蚀刻形成栅极6结构;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
定义元胞区金属氧化物场效应晶体管的栅极6图形和栅极6与源极5之间并联可调电阻11结构的图形,所述栅极6与源极5之间并联可调电阻11结构的可调范围介于7千欧姆与10千欧姆间,通过设计独立的3um线宽的栅极6与源极5之间并联可调电阻11图形,平行并联3个独立的栅极6与源极5之间并联可调电阻11来实现。
步骤S7、在本征外延层2上表面通过离子注入三价元素杂质得到体区9,所述三价元素包括硼,同时离子注入到多晶硅上,然后通过热工艺对体区9的杂质进行激活;
步骤S8、在本征外延层2上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义源区10图形,通过离子注入五价元素杂质在体区9上表面得到源极5,所述五价元素包括砷、磷,本实施例具体为磷元素,同时用掩膜阻挡多晶硅电阻结构区域被离子注入五价元素杂质,然后通过干蚀刻搭配湿法蚀刻去除掩膜,再通过热工艺对源区10的杂质进行激活;
步骤S9、在本征外延层2上表面通过离子注入三价元素硼元素得到高掺杂的欧姆接触区13,同时离子注入三价元素到多晶硅电阻结构区域,最终得到元胞结构和栅极6与源极5之间并联可调电阻11结构。
步骤S10、通过化学气象淀积形成二氧化硅介质层12;
步骤S11、通过光刻工艺使用光刻胶定义源区接触孔14图形、栅极区域接触孔15图形和栅极6与源极5之间并联可调电阻11结构的栅极端接触孔16图形和源极端接触孔17图形;所述源区接触孔14图形位于源极5和体区9的上方,用于将源极5和体区9一同引出;所述栅极区域接触孔15图形位于栅极多晶硅8的上方,同时在源区10中定义没有源区接触孔14的区域用于放置栅极金属导线21;所述栅极6与源极5之间并联可调电阻11结构的栅极端接触孔16和源极端接触孔17位于栅极6与源极5之间并联可调电阻11结构的上方,用于栅极6和源极5与栅极6与源极5之间并联可调电阻11结构并联;
步骤S12、通过干法蚀刻二氧化硅介质层12,得到源区接触孔14、栅极区域接触孔15和栅极6与源极5之间并联可调电阻11结构的栅极端接触孔16和源极端接触孔17;
步骤S13、通过物理气象淀积工艺淀积金属作为粘合层,淀积金属氮化物作为阻挡层,再利用快速热退化工艺形成硅化物,所述金属包括钛、钴、钽中的一种或多种;本实施例具体为金属钴。
步骤S14、通过钨栓18工艺淀积金属钨,通过干法刻蚀方法去除掉接触孔以外的金属钨,在源区接触孔14、栅极区域接触孔15和栅极6与源极5之间并联可调电阻11结构的接触孔中形成钨栓18。
步骤S15、在钨栓18上方通过物理气象淀积铝铜化合物19,通过光刻工艺使用光刻胶定义源极5金属导线图形、栅极金属导线21图形和栅极6与源极5之间并联可调电阻11结构控制极图形;通过干法蚀刻得到源极5、栅极6、栅极6与源极5之间并联可调电阻控制极4;
所述源极5金属导线图形位于源区10上方;
所述栅极金属导线21图形通过围绕着元胞区边缘走线将栅极6经由栅极区域接触孔15互联至源区10无源区10接触孔的区域形成栅极金属导线21;
所述栅极6与源极5之间并联可调电阻控制极4图形通过该可调电阻的栅极端接触孔16与独立的栅极6与源极5之间并联可调电阻11结构连接,同时在每个独立的栅极6与源极5之间并联可调电阻11与栅极金属导线21之间引出独立的栅极6与源极5之间并联可调电阻控制极4,该控制极数量与设计的独立的栅极6与源极5之间并联可调电阻11数量一一对应。
步骤S15中所述栅极6与源极5之间并联可调电阻控制极4图形会将在可调电阻栅极端接触孔16的金属导线与独立的栅极6与源极5之间并联可调电阻控制极4金属导线交汇点之后的用于与栅极金属导线21互联的金属导线局部线宽设计为1um。
步骤S16、淀积钝化层20,通过光刻工艺使用光刻胶定义源极5金属接触区、栅极6金属接触区和栅极6与源极5之间并联可调电阻控制极4接触区;
通过干法蚀刻得到源极5金属接触区、栅极6金属接触区、栅极6与源极5之间并联可调电阻控制极4接触区;栅极6与源极5之间并联可调电阻控制极4接触区数量与独立栅极6与源极5之间并联可调电阻11数量一一对应;所述钝化层20为氮化硅。
最终得到一种栅极与源极并联可调电阻型超结型功率器件。
实施例3
请参阅图1和图2,本发明实施例中,一种栅极与源极并联可调电阻型超结功率器件的制造方法,包括如下步骤:
步骤S1、在硅衬底1上表面化学气相沉积一层本征外延层2;通过离子注入在所述本征外延层2掺杂三价元素;所述三价元素包括硼,本实施例具体为硼元素。
步骤S2、在所述本征外延层2的上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构。
步骤S3、通过光刻工艺在掩膜上定义柱状掺杂区3图形;通过离子注入在所述本征外延层2掺杂五价元素,所述五价元素包括砷、磷,本实施例具体为磷元素;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
步骤S4、重复步骤S1-S3至本征外延层2总的厚度为55um;步骤S4中每重复步骤S1-S3均按照器件设计需求单独定义三价元素和五价元素离子注入的工艺条件。
步骤S5、通过热氧化方法对生长栅极氧化层7,然后通过低压化学气象淀积原位掺杂的栅极多晶硅8;所述栅极氧化层7的厚度为90nm;所述栅极多晶硅8的厚度为650nm。
步骤S6、在所述栅极多晶硅8上面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义栅极6图形,然后通过干法蚀刻形成栅极6结构;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
定义元胞区金属氧化物场效应晶体管的栅极6图形和栅极6与源极5之间并联可调电阻11结构的图形,所述栅极6与源极5之间并联可调电阻11结构的可调范围介于7千欧姆与10千欧姆间,通过设计独立的7um线宽的栅极6与源极5之间并联可调电阻11图形,平行并联2个独立的栅极6与源极5之间并联可调电阻11来实现。
步骤S7、在本征外延层2上表面通过离子注入五价元素杂质得到体区9,所述五价元素包括砷、磷,本实施例具体为磷元素,同时离子注入到多晶硅上,然后通过热工艺对体区9的杂质进行激活;
步骤S8、在本征外延层2上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义源区10图形,通过离子注入三价元素杂质在体区9上表面得到源极5,所述三价元素包括硼,本实施例具体为硼元素,同时用掩膜阻挡多晶硅电阻结构区域被离子注入三价元素杂质,然后通过干蚀刻搭配湿法蚀刻去除掩膜,再通过热工艺对源区10的杂质进行激活;
步骤S9、在本征外延层2上表面通过离子注入五价元素得到高掺杂的欧姆接触区13,所述五价元素包括砷、磷,同时离子注入三价元素到多晶硅电阻结构区域,最终得到元胞结构和栅极6与源极5之间并联可调电阻11结构。
步骤S10、通过化学气象淀积形成二氧化硅介质层12;
步骤S11、通过光刻工艺使用光刻胶定义源区接触孔14图形、栅极区域接触孔15图形和栅极6与源极5之间并联可调电阻11结构的栅极端接触孔16图形和源极端接触孔17图形;所述源区接触孔14图形位于源极5和体区9的上方,用于将源极5和体区9一同引出;所述栅极区域接触孔15图形位于栅极多晶硅8的上方,同时在源区10中定义没有源区接触孔14的区域用于放置栅极金属导线21;所述栅极6与源极5之间并联可调电阻11结构的栅极端接触孔16和源极端接触孔17位于栅极6与源极5之间并联可调电阻11结构的上方,用于栅极6和源极5与栅极6与源极5之间并联可调电阻11结构并联;
步骤S12、通过干法蚀刻二氧化硅介质层12,得到源区接触孔14、栅极区域接触孔15和栅极6与源极5之间并联可调电阻11结构的栅极端接触孔16和源极端接触孔17;
步骤S13、通过物理气象淀积工艺淀积金属作为粘合层,淀积金属氮化物作为阻挡层,再利用快速热退化工艺形成硅化物,所述金属包括钛、钴、钽中的一种或多种;本实施例具体为金属钛。
步骤S14、通过钨栓18工艺淀积金属钨,通过干法刻蚀方法去除掉接触孔以外的金属钨,在源区接触孔14、栅极区域接触孔15和栅极6与源极5之间并联可调电阻11结构的接触孔中形成钨栓18。
步骤S15、在钨栓18上方通过物理气象淀积铝铜化合物19,通过光刻工艺使用光刻胶定义源极5金属导线图形、栅极金属导线21图形和栅极6与源极5之间并联可调电阻11结构控制极图形;通过干法蚀刻得到源极5、栅极6、栅极6与源极5之间并联可调电阻控制极4;
所述源极5金属导线图形位于源区10上方;
所述栅极金属导线21图形通过围绕着元胞区边缘走线将栅极6经由栅极区域接触孔15互联至源区10无源区10接触孔的区域形成栅极金属导线21;
所述栅极6与源极5之间并联可调电阻控制极4图形通过该可调电阻的栅极端接触孔16与独立的栅极6与源极5之间并联可调电阻11结构连接,同时在每个独立的栅极6与源极5之间并联可调电阻11与栅极金属导线21之间引出独立的栅极6与源极5之间并联可调电阻控制极4,该控制极数量与设计的独立的栅极6与源极5之间并联可调电阻11数量一一对应。
步骤S15中所述栅极6与源极5之间并联可调电阻控制极4图形会将在可调电阻栅极端接触孔16的金属导线与独立的栅极6与源极5之间并联可调电阻控制极4金属导线交汇点之后的用于与栅极金属导线21互联的金属导线局部线宽设计为2um。
步骤S16、淀积钝化层20,通过光刻工艺使用光刻胶定义源极5金属接触区、栅极6金属接触区和栅极6与源极5之间并联可调电阻控制极4接触区;
通过干法蚀刻得到源极5金属接触区、栅极6金属接触区、栅极6与源极5之间并联可调电阻控制极4接触区;栅极6与源极5之间并联可调电阻控制极4接触区数量与独立栅极6与源极5之间并联可调电阻11数量一一对应;所述钝化层20为二氧化硅。
最终得到一种栅极与源极并联可调电阻型超结型功率器件。
本发明无需在电路应用中额外增加并联在栅极和源极之间的电阻,减少成本支出提高器件集成度和稳定性;同时无需就不同的栅极与源极之间并联电阻需求而变更栅极、接触通孔、金属导线层的版图和重新制作掩模版并流片,减少成本支出;通过栅极与源极之间并联电阻控制极分别对每个独立的栅极与源极之间并联电阻进行开路控制以实现对栅极与源极之间并联电阻的调整;还能够提高器件在应用时的通用性。
对于本领域技术人员而言,显然本发明不限于上述示范性实施例的细节,而且在不背离本发明的精神或基本特征的情况下,能够以其他的具体形式实现本发明。因此,无论从哪一点来看,均应将实施例看作是示范性的,而且是非限制性的,本发明的范围由所附权利要求而不是上述说明限定,因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外,应当理解,虽然本说明书按照实施方式加以描述,但并非每个实施方式仅包含一个独立的技术方案,说明书的这种叙述方式仅仅是为清楚起见,本领域技术人员应当将说明书作为一个整体,各实施例中的技术方案也可以经适当组合,形成本领域技术人员可以理解的其他实施方式。
Claims (10)
1.一种栅极与源极并联可调电阻型超结功率器件的制造方法,其特征在于,包括如下步骤:
A、超结型功率器件元胞结构和栅极、源极之间并联可调电阻结构的制备;
B、接触孔的制备;
C、金属导线的制备;
D、钝化层的制备。
2.根据权利要求1所述的栅极与源极并联可调电阻型超结功率器件的制造方法,其特征在于,步骤A具体包括如下步骤:
步骤S1、在硅衬底上表面化学气相沉积一层本征外延层;通过离子注入在所述本征外延层掺杂五价元素;
步骤S2、在所述本征外延层的上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;
步骤S3、通过光刻工艺在掩膜上定义柱状掺杂区图形;通过离子注入在所述本征外延层掺杂三价元素;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
步骤S4、重复步骤S1-S3至本征外延层总的厚度为30um-70um;
步骤S5、通过热氧化方法对生长栅极氧化层,然后通过低压化学气象淀积原位掺杂的栅极多晶硅;
步骤S6、在所述栅极多晶硅上面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义栅极图形,然后通过干法蚀刻形成栅极结构;然后通过干蚀刻搭配湿法蚀刻去除掩膜;
定义元胞区金属氧化物场效应晶体管的栅极图形和栅极与源极之间并联可调电阻结构的图形,所述栅极与源极之间并联可调电阻结构的可调范围介于5千欧姆与20千欧姆间,通过设计独立的1-10um线宽的栅极与源极之间并联可调电阻图形,平行并联2个到5个独立的栅极与源极之间并联可调电阻来实现;
步骤S7、在本征外延层上表面通过离子注入三价元素杂质得到体区,同时离子注入到多晶硅上,然后通过热工艺对体区的杂质进行激活;
步骤S8、在本征外延层上表面沉积掩膜,所述掩膜的成分为光刻胶或光刻胶与其它绝缘体掩模组成的多层组合结构;通过光刻工艺在掩膜上定义源区图形,通过离子注入五价元素杂质在体区上表面得到源极,同时用掩膜阻挡多晶硅电阻结构区域被离子注入五价元素杂质,然后通过干蚀刻搭配湿法蚀刻去除掩膜,再通过热工艺对源区的杂质进行激活;
步骤S9、在本征外延层上表面通过离子注入三价元素得到高掺杂的欧姆接触区,同时离子注入三价元素到多晶硅电阻结构区域,最终得到元胞结构和栅极与源极之间并联可调电阻结构。
3.根据权利要求2所述的栅极与源极并联可调电阻型超结功率器件的制造方法,其特征在于,步骤S1、S3、S7、S8和S9中所述三价元素包括硼元素,所述五价元素包括砷、磷。
4.根据权利要求2所述的栅极与源极并联可调电阻型超结功率器件的制造方法,其特征在于,步骤S4中每重复步骤S1-S3均按照器件设计需求单独定义三价元素和五价元素离子注入的工艺条件至本征外延层总的厚度为30um-70um。
5.根据权利要求1所述的栅极与源极并联可调电阻型超结功率器件的制造方法,其特征在于,步骤S5中所述栅极氧化层的厚度为50~200nm;步骤S5中所述栅极多晶硅的厚度为500~1000nm。
6.根据权利要求1所述的栅极与源极并联可调电阻型超结功率器件的制造方法,其特征在于,步骤B具体包括如下步骤:
步骤S10、通过化学气象淀积形成二氧化硅介质层;
步骤S11、通过光刻工艺使用光刻胶定义源区接触孔图形、栅极区域接触孔图形和栅极与源极之间并联可调电阻结构的栅极端接触孔图形和源极端接触孔图形;所述源区接触孔图形位于源极和体区的上方,用于将源极和体区一同引出;所述栅极区域接触孔图形位于栅极多晶硅的上方,同时在源区中定义没有源区接触孔的区域用于放置栅极金属导线;所述栅极与源极之间并联可调电阻结构的栅极端接触孔和源极端接触孔位于栅极与源极之间并联可调电阻结构的上方,用于栅极和源极与栅极与源极之间并联可调电阻结构并联;
步骤S12、通过干法蚀刻二氧化硅介质层,得到源区接触孔、栅极区域接触孔和栅极与源极之间并联可调电阻结构的栅极端接触孔和源极端接触孔;
步骤S13、通过物理气象淀积工艺淀积金属作为粘合层,淀积金属氮化物作为阻挡层,再利用快速热退化工艺形成硅化物,所述金属包括钛、钴、钽中的一种或多种;
步骤S14、通过钨栓工艺淀积金属钨,通过干法刻蚀方法去除掉接触孔以外的金属钨,在源区接触孔、栅极区域接触孔和栅极与源极之间并联可调电阻结构的接触孔中形成钨栓。
7.根据权利要求1所述的栅极与源极并联可调电阻型超结功率器件的制造方法,其特征在于,步骤C具体包括如下步骤:
步骤S15、在钨栓上方通过物理气象淀积铝铜化合物,通过光刻工艺使用光刻胶定义源极金属导线图形、栅极金属导线图形和栅极与源极之间并联可调电阻控制极图形;通过干法蚀刻得到源极、栅极、栅极与源极之间并联可调电阻控制极;
所述源极金属导线图形位于源区上方;
所述栅极金属导线图形通过围绕着元胞区边缘走线将栅极经由栅极区域接触孔互联至源区无源区接触孔的区域形成栅极金属导线;
所述栅极与源极之间并联可调电阻控制极图形通过该可调电阻的栅极端接触孔与独立的栅极与源极之间并联可调电阻结构连接,同时在每个独立的栅极与源极之间并联可调电阻与栅极金属导线之间引出独立的栅极与源极之间并联可调电阻控制极,该控制极数量与设计的独立的栅极与源极之间并联可调电阻数量一一对应。
8.根据权利要求7所述的栅极与源极并联可调电阻型超结功率器件的制造方法,其特征在于,步骤S15中所述栅极与源极之间并联可调电阻控制极图形会将在可调电阻栅极端接触孔的金属导线与独立的栅极与源极之间并联可调电阻控制极金属导线交汇点之后的用于与栅极金属导线互联的金属导线局部线宽设计为1~2um。
9.根据权利要求1所述的栅极与源极并联可调电阻型超结功率器件的制造方法,其特征在于,步骤D具体包括如下步骤:
步骤S16、淀积钝化层,通过光刻工艺使用光刻胶定义源极金属接触区、栅极金属接触区和栅极与源极之间并联可调电阻控制极接触区;
通过干法蚀刻得到源极金属接触区、栅极金属接触区、栅极与源极之间并联可调电阻控制极接触区;栅极与源极之间并联可调电阻控制极接触区数量与独立栅极与源极之间并联可调电阻数量一一对应;
所述钝化层包括氮化硅或二氧化硅。
10.一种栅极与源极并联可调电阻的超结型功率器件,其特征在于,由权利要求1-9任一项所述的栅极与源极并联可调电阻型超结功率器件的制造方法制备得到。
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