CN113437029A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN113437029A
CN113437029A CN202110002095.0A CN202110002095A CN113437029A CN 113437029 A CN113437029 A CN 113437029A CN 202110002095 A CN202110002095 A CN 202110002095A CN 113437029 A CN113437029 A CN 113437029A
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semiconductor
insulating film
semiconductor device
support
semiconductor chip
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CN113437029B (zh
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加藤贤
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Kioxia Corp
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Kioxia Corp
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
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    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract

本发明涉及一种半导体装置及其制造方法。实施方式的半导体装置具有：支撑体，形成着第1电极；半导体芯片，设置在支撑体上，且形成着第2电极；第1绝缘膜，与半导体芯片的支撑体侧一面即第1面及作为半导体芯片的至少一个侧面的第1侧面连续相接；以及配线层，将第1电极与第2电极连接，且和半导体芯片的与第1面为相反侧的一面即第2面、第1绝缘膜的与第1侧面侧为相反侧的一面及支撑体相接。

Description

半导体装置及其制造方法
相关申请案的引用
本申请案基于2020年03月23日提出申请的在先日本专利申请案第2020-050831号的优先权而主张优先权利益，通过引用将其全部内容并入本文中。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
已知有以下方法：在晶片等支撑体上安装逻辑系半导体芯片，形成与晶片连接的配线层时，为了防止露出在芯片侧壁的Si与配线层电连接，而在形成配线层之前设置覆盖芯片上及芯片侧面的绝缘膜。然而，如果在将芯片载置在晶片之后设置绝缘膜，那么会有半导体封装的厚度增加相当于绝缘膜厚度的量的情况。
发明内容
本发明的实施方式提供一种有利于封装小型化的半导体装置。
实施方式的半导体装置具有：支撑体，形成着第1电极；半导体芯片，设置在支撑体上，且形成着第2电极；第1绝缘膜，与半导体芯片的支撑体侧一面即第1面及作为半导体芯片的至少一个侧面的第1侧面连续相接；以及配线层，将第1电极与第2电极连接，且和半导体芯片的与第1面为相反侧的一面即第2面、第1绝缘膜的与第1侧面侧为相反侧的一面及支撑体相接。
根据所述构成，能够提供一种有利于封装小型化的半导体装置。
附图说明
图1是实施方式的半导体装置的剖视概念图。
图2是实施方式的半导体装置的步骤概念图。
图3是实施方式的半导体装置的步骤概念图。
图4是实施方式的半导体装置的步骤概念图。
图5是实施方式的半导体装置的步骤概念图。
图6是实施方式的半导体装置的步骤概念图。
图7是实施方式的半导体装置的步骤概念图。
图8是实施方式的半导体装置的步骤概念图。
图9是实施方式的半导体装置的步骤概念图。
图10是实施方式的半导体装置的步骤概念图。
图11是实施方式的半导体装置的俯视概念图。
图12是实施方式的半导体装置的俯视概念图
图13是实施方式的半导体封装的剖视概念图。
图14是实施方式的半导体装置的剖视概念图。
图15是实施方式的半导体装置的步骤概念图。
图16是实施方式的半导体装置的步骤概念图。
图17是实施方式的半导体装置的步骤概念图。
图18是实施方式的半导体装置的步骤概念图。
图19是实施方式的半导体装置的步骤概念图。
图20是实施方式的半导体封装的剖视概念图。
图21是实施方式的半导体装置的剖视概念图。
具体实施方式
以下，参照附图对实施方式进行说明。
在本说明书中，对几个要素附加多个表达例。此外，这些表达示例只不过为例示，并不否定所述要素用其它表达方式来表达。另外，关于未附加多个表达的要素，也可以用其它表达方式来表达。
另外，附图是示意性图，厚度与平面尺寸的关系或各层的厚度的比率等有时与实物不同。另外，也会在附图相互间包含相互的尺寸关系或比率不同的部分。另外，在附图中，省略了一部分符号。
(第1实施方式)第1实施方式涉及一种半导体装置。图1表示半导体装置100的剖视概念图。更具体来说，实施方式的半导体装置100是形成着一部分配线的半导体芯片、搭载着半导体芯片的半导体封装的一部分或半导体封装。此外，X方向、Y方向及Z方向优选为相互交叉、相互正交。
图1的概念图表示半导体装置100的主要部分。图1的半导体装置100具有半导体芯片1、第1绝缘膜20、配线层30及支撑体40。支撑体40具有作为“第1电极”的电极41。半导体芯片具有半导体层10、半导体元件13、第2绝缘膜11及作为“第2电极”的电极12。半导体元件13例如为CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)电路等。
半导体芯片1例如为逻辑芯片。更具体来说，半导体芯片1为非易失性存储器芯片的控制器芯片。
在半导体芯片1的朝向支撑体40侧的一面即“第1面”及半导体芯片1的侧面设置着第1绝缘膜20。设置在半导体芯片1的朝向支撑体40侧一面的第1绝缘膜20与设置在半导体芯片1侧面的第1绝缘膜20为不间断的连续膜。在半导体芯片的侧面，露出作为半导体衬底的一部分的半导体层10，如果半导体层的例如Si与配线层30相接，那么半导体层10与配线层30在侧面电连接。因此，从使半导体芯片的侧面绝缘的观点来看，优选为半导体芯片1的朝向支撑体40侧的一面及半导体芯片1的侧面直接与第1绝缘膜20相接，更优选为半导体芯片1的朝向支撑体40侧的整个面及半导体芯片1的整个侧面直接与第1绝缘膜20相接。
在半导体芯片1的与朝向支撑体40的一面为相反侧的面即“第2面”，设置着第2绝缘膜11及电极12。第2绝缘膜11在半导体芯片1的半导体层10的与朝向支撑体40的一面为相反侧，覆盖不希望与配线层30电连接的部位。第2绝缘膜11的一部分与配线层30直接相接。第2绝缘膜11例如为无机氧化膜、无机氮化膜或无机氮氧化膜等无机系膜。无机系的第2绝缘膜11可以通过使Si氧化或氮化等而形成，也可以通过CVD(chemical vapor deposition，化学气相沉积)或溅镀等成膜而形成。第2绝缘膜11也可以为聚酰亚胺等有机系膜。有机系膜通过旋转涂布等涂布法而形成，膜厚可以为1μm至几μm。在形成无机系膜的情况下，可使其厚度例如为10nm以上100nm以下。第2绝缘膜11也可以使用将所述有机系膜与无机系膜积层而成的膜或混合而成的膜。
电极12是半导体芯片1的电极，虽然图1中未示出，但电极12在芯片1上设置着多个。电极12由Al、Cu或Ni合金等金属构成。电极12与配线层30电连接。电极12经由内部配线而与半导体元件13电连接。
例如，如图1所示，半导体元件13在半导体层1中包含多个，半导体元件13彼此电连接。半导体元件13与电极12电连接。
第1绝缘膜20是将半导体芯片1绝缘的部件。第1绝缘膜20是包含树脂的绝缘膜。可以在第1绝缘膜20与支撑层40之间设置芯片粘结膜(DAF)等，而使第1绝缘膜20与支撑层40粘接，也可以在第1绝缘膜20具备粘接性的情况下，使第1绝缘膜20与支撑体40粘接。从减小封装厚度的观点来看，优选为位于半导体芯片1与支撑体40之间的第1绝缘膜20与支撑体40直接相接。第1绝缘膜20例如优选包含粘接性树脂，还包含任意填料。
由于第1绝缘膜20是不间断的连续膜，所以第1绝缘膜20的第1部分与第2部分由相同的绝缘物构成，第1部分是以与半导体芯片1的朝向支撑体40的一面相接的方式设置的部分，第2部分是以与芯片1的侧面相接的方式设置的部分。更具体来说，第1绝缘膜20中的与半导体芯片1的第1面相接的部分及与半导体芯片1的侧面相接的部分由相同树脂构成，或由相同树脂及相同填料构成。
配线层30至少与半导体芯片1电连接，且设置在支撑体40上。配线层30可以与支撑体40电连接，也可以不与支撑体40电连接。在图1的概念图中，半导体芯片1与支撑体40利用配线层30而电连接。优选为配线层30与半导体芯片1、第1绝缘膜及支撑体40直接相接。配线层30有时还设置在X方向。
配线层30由Cu层、包含Ti等的基底层与Cu层的积层体等构成。在利用镀覆形成配线层30的情况下，配线层30也可以包含镀覆基底层。配线层30也可以组合溅镀法等成膜与光刻法而形成。
配线层30和半导体芯片1的与支撑体40侧为相反侧的一面、设置在作为半导体芯片1的一个侧面的“第1侧面”的第1绝缘膜20的与第1侧面侧为相反侧的一面以及支撑体40相接。更优选为，配线层30和半导体芯片1的与支撑体40侧为相反侧的一部分或整个面、与半导体芯片1的一个侧面相接的第1绝缘膜20的与半导体芯片侧为相反侧的整个面以及支撑体40相接。如果在配线层30与第1绝缘膜20之间设置着其它绝缘膜，那么导致封装变厚，所以优选为不在配线层30与第1绝缘膜20之间设置其它绝缘膜。另外，在图1中，配线层30与无机的第2绝缘膜11相接。
在将从支撑体40到半导体芯片1为止的最大距离设为T1，将从支撑体40到配线层30为止的最大距离设为T2时，T2－T1优选为1μm以上10μm以下，优选为1μm以上5μm以下。通过在半导体芯片1上直接设置配线层30能够减小T2－T1的长度，有助于封装尺寸的小型化。
支撑体40是形成着再配线层的半导体元件或配线衬底等。作为半导体元件，例如可列举非易失性或易失性存储器芯片。非易失性存储器芯片是进行数据读写的半导体芯片。作为非易失性存储器芯片，可使用NAND(Not AND，与非)存储器芯片、相变存储器芯片、阻变存储器芯片、强介电体存储器芯片、磁性存储器芯片等。作为易失性存储器芯片，可使用DRAM(Dynamic Random Access Memory，动态随机存取存储器)等。此外，半导体元件并不限定为存储器芯片。优选为，支撑体40具有与半导体元件或内部配线电连接的电极41，且经由配线层30而将半导体芯片1与支撑体40经由电极41电连接。
接下来，参照图2至图10的半导体装置100的步骤概念图，对图1的半导体装置100的制造方法进行说明。半导体装置100的制造方法包含以下步骤：在设置着多个半导体芯片1的支承衬底50上，以覆盖多个半导体芯片1的与支承衬底50侧为相反侧的一面及多个半导体芯片的侧面的方式形成绝缘体21；将绝缘体21在多个半导体芯片1之间切断，获得形成着第1绝缘膜20的半导体芯片1，所述第1绝缘膜20和半导体芯片1的与支承衬底50侧的面为相反侧的一面及半导体芯片1的侧面连续相接；将形成着第1绝缘膜20的半导体芯片1从支承衬底50拆除，以半导体芯片1的与支承衬底50侧的面为相反侧一面的第1绝缘膜20朝向支撑体40侧的方式载置在支撑体40上；以及形成配线层30，所述配线层30和半导体芯片1的与支撑体40侧为相反侧的一面、第1绝缘膜20的半导体芯片1的侧面侧及支撑体40相接。
首先，如图2的步骤概念图所示，以半导体芯片1的第2绝缘膜11及电极12侧朝向硅晶片等支承衬底50侧的方式，在支承衬底50上设置多个半导体芯片1。在多个半导体芯片1之间设置空隙。支承衬底可以为玻璃衬底或树脂衬底等。支承衬底50也可以为具有粘附性的树脂衬底。在该情况下，只要在具有粘附性的树脂贴附半导体芯片1即可。在支承衬底50不具有粘附性的情况下，在半导体芯片1与支承衬底50之间形成未图示的粘附剂。
接下来，如图3的步骤概念图所示，在半导体芯片1的与支承衬底50侧为相反侧的一面形成层状绝缘体21。层状绝缘体21例如为膜状树脂膜。
接下来，对层状绝缘体21进行加压，如图4的步骤概念图所示，以由绝缘体21覆盖半导体芯片1的侧面的方式在半导体芯片1之间也压入绝缘体21而获得绝缘体22。被压入的绝缘体22也与半导体芯片1的侧面相接。优选为，一边在减压(真空)下放置一边对绝缘体21进行加压、或一边进行加热一边对绝缘体21进行加压、或一边进行加热一边在减压下对绝缘体21进行加压等，从而由绝缘体22覆盖半导体芯片1的整个侧面。
接下来，将半导体芯片1之间的绝缘体22切断，如图5的步骤概念图所示，获得形成有第1绝缘膜20的半导体芯片1，所述第1绝缘膜20和半导体芯片1的与支承衬底50侧的面为相反侧的一面以及半导体芯片1的侧面连续相接。切断例如利用激光或刀片切割等来进行。此时也可以切入到支承衬底50。
接下来，将形成着第1绝缘膜20的半导体芯片1从支承衬底50拆除。图6表示从已拆除的半导体芯片1的上表面观察的概念图。如图6所示，半导体层10的整个侧面由第1绝缘膜20包围。如图7的步骤概念图所示，以半导体芯片1的与支承衬底50侧的面为相反侧一面的第1绝缘膜20朝向支撑体40侧的方式将半导体芯片1载置在支撑体40上。在支撑体40中设置着之后会与半导体芯片1电连接的电极41。在图7至图10中，省略半导体元件13的图示。
接下来，如图8的步骤概念图所示，在设置着半导体芯片1的支撑体40上利用CVD、溅镀等成膜镀覆基底层31。
接下来，如图9的步骤概念图所示，在未形成配线层30的位置形成将成为镀覆掩模的抗蚀剂32、33。然后，进行Cu的电镀，如图10的步骤概念图所示在露出的基底层31上形成Cu层34。然后，将抗蚀剂32、33与抗蚀剂32、33之下的基底膜31去除，可获得图1的半导体装置100。也就是说，配线层30是基底膜31与Cu层34的积层膜。如果在第1绝缘膜20与配线层30之间设置其它绝缘膜，那么需要形成其它绝缘膜的工艺，但在制成实施方式的构造的半导体装置100的步骤中可完全省略形成其它绝缘膜的工艺，所以从简化工艺的观点来看也适宜。
对在晶片上形成半导体装置100的情况进行说明。例如，如图11的俯视概念图所示，在晶片200形成着半导体元件100a。半导体元件100a例如可以为非易失性或易失性存储器元件，也可以为CMOS电路等。以将多个半导体元件100a排列在晶片200上的方式形成。在半导体元件100a的表面形成着多个电极41与电极42。电极42与电极41是经由形成在半导体元件100a上的未图示的再配线层或半导体元件100a的内部配线等而连接。电极41用于与半导体芯片1连接，电极42用于与其它半导体芯片连接。图12表示在各半导体元件100a之上配置图6所示的半导体芯片1，如图7至图10中所说明将半导体芯片1与电极41利用配线层30连接的状态的概念图。此时，配线层30沿着半导体芯片1的4个侧面中的3个侧面形成。此处，配线层30可以沿着半导体芯片1的4个侧面的全部而形成，也可以沿着2个侧面形成，还可以只沿着一个侧面形成。配线层30的图案布局可自由选择。另外，即便半导体1芯片1并非方形而为多边形的情况下，也能够以沿着至少一个侧面或多个侧面的方式形成配线层30。将晶片200沿着半导体元件100a的轮廓切断，形成半导体装置100。
图13表示使用由图12中所说明的方法制成的半导体装置100的半导体封装300。半导体封装300包含半导体装置100、多个NAND闪速存储器芯片60(A～C)、接合线61(A～D)、配线衬底62、焊球63及密封材64。支撑体40使用NAND闪速存储器芯片。在半导体封装300中，在配线衬底62上积层着多个NAND闪速存储器芯片60，并在多个NAND闪速存储器芯片60之上设置着半导体装置100。电极12与电极41经由配线层30连接。作为NAND闪速存储器芯片的支撑体40的电极42与作为NAND闪速存储器芯片60A的焊垫电极(未图示)利用接合线61A连接。各NAND闪速存储器芯片60利用接合线61(B～C)连接。最下段的NAND闪速存储器芯片60C与配线衬底62利用接合线61D连接。通过将实施方式的半导体装置100用于半导体封装300，能够抑制半导体封装300的厚度。
(第2实施方式)第2实施方式涉及一种半导体装置。第2实施方式的半导体装置101是第1实施方式的半导体装置100的变化例。关于第2实施方式中与第1实施方式共通的内容省略说明。图14表示第2实施方式的半导体装置101的剖视概念图。
第2实施方式的半导体装置101与第1实施方式的半导体装置100的不同点在于，在半导体芯片1的与支撑体40侧为相反侧一面的一部分也设置着第1绝缘膜20的一部分20a。由此，在半导体芯片1的表面露出金属时等，能够更加提高半导体芯片1与配线层30之间的绝缘性。
接下来，参照图15至图19的半导体装置100的步骤概念图，对图14的半导体装置101的制造方法进行说明。
首先，如图15的步骤概念图所示，以半导体芯片1的第2绝缘膜11及电极12侧朝向晶片等支承衬底50侧的方式，在支承衬底50上设置多个半导体芯片1。在多个半导体芯片1之间设置空隙。朝向支承衬底50侧的半导体层10的一部分露出。
接下来，如图16的步骤概念图所示，在半导体芯片1的与支承衬底50侧为相反侧的一面涂布液状或凝胶状的树脂组合物23。此时，优选为以不产生空隙的方式减压。树脂组合物23例如为利用干燥、加热或UV(ultraviolet，紫外线)照射等硬化的材料。
接下来，如图17的步骤概念图所示获得将树脂组合物利用干燥、加热或UV照射等硬化成的绝缘体22。
接下来，如图17的步骤概念图所示，将半导体芯片1之间的绝缘体21切断。获得形成为第1绝缘膜20及第1绝缘膜20的一部分20a与半导体层10直接接触的半导体芯片1，所述第1绝缘膜20以和半导体芯片1的与支承衬底50侧的面为相反侧的一面以及半导体芯片1的侧面连续相接的方式设置。图18表示从已拆除的半导体芯片1的上表面观察的步骤概念图。如图18所示，由虚线表示的半导体层10的侧面被第1绝缘膜20包围。进而，从半导体层10的外形轮廓稍微向内侧进入的部位形成着第1绝缘膜20的一部分20a。在半导体元件13的上表面的一部分也形成着第1绝缘膜20。以下，可利用与第1实施方式相同的步骤获得半导体装置100。
可以将第2实施方式的制造方法用于第1实施方式的制造方法，也可以将第1实施方式的制造方法用于第2实施方式的制造方法。
图20表示使用半导体装置101的半导体封装400。半导体封装400包含半导体装置101、支撑体40、多个NAND闪速存储器芯片60(A～D)、接合线65(A～D)、接着层66、焊球63及密封材64。支撑体40为配线衬底。在半导体封装400中，利用接着层66覆盖半导体装置101的半导体芯片1，在接着层66之上积层着多个NAND闪速存储器芯片60。最下段NAND闪速存储器芯片60A与支撑体40利用接合线65A连接，各NAND闪速存储器芯片60利用接合线65(B～D)连接。电极41与连接着焊球63及接合线65A的支撑体40的焊垫电极经由支撑体40的内部配线等电连接。通过将实施方式的半导体装置101用于半导体封装400，能够降低接着层66的厚度而抑制半导体封装400的厚度。
(第3实施方式)第3实施方式涉及一种半导体装置。第3实施方式的半导体装置是第1实施方式及第2实施方式的半导体装置100的变化例。关于第3实施方式与第1实施方式或第2实施方式共通的内容省略说明。图21表示第3实施方式的半导体装置500的概念图。
第3实施方式的半导体装置500与第1实施方式及第2实施方式的不同点在于，支撑体40上设置着2个半导体芯片1，2个半导体芯片1由配线层30连接。
第1实施方式及第2实施方式是将半导体装置100(101)的半导体芯片1与不同半导体芯片连接的形态，但也可以将实施方式的配线构造用于在支撑体40上连接相同种类的半导体芯片1，能够采用。例如，通过将多个逻辑芯片像半导体装置500那样连接，能够获得高速且大规模的逻辑IC(integrated circuit，集成电路)。
其它实施方式(a)在所述实施方式中，配线层30由金属层形成，但也可以进而在金属层之上形成树脂膜或无机膜等绝缘膜。此时配线层30由绝缘膜保护，可靠性提高。(b)也可以在所述实施方式(a)中，在设置在配线层30的绝缘膜之上进而设置金属层，使金属层为两层。另外，也可以进而积层，利用光刻与蚀刻等对金属层及绝缘膜加工，使配线层30积层多层。此时可形成具有复杂配线图案的配线层30。
以上，对本发明的几个实施方式进行了说明，但这些实施方式是作为示例而提出的，并不旨在限定发明的范围。这些新颖的实施方式能够以其它各种方式加以实施，能够在不脱离发明的主旨的范围内进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书中所记载的发明及其均等的范围内。

Claims (16)

1.一种半导体装置，具备：
支撑体，支撑着第1电极；
半导体芯片，设置在所述支撑体上，具有与所述支撑体对向的第1面及与所述第1面为相反侧的第2面，且在所述第2面侧形成着第2电极；
第1绝缘膜，具有设置在所述第1面侧的第1部分、及设置在作为所述半导体芯片的至少1个侧面的第1侧面的第2部分；以及
配线层，将所述第1电极与所述第2电极连接，且设置在所述第2面、所述第2部分及所述支撑体。
2.根据权利要求1所述的半导体装置，其中所述支撑体为配线衬底。
3.根据权利要求1所述的半导体装置，其还具备设置在所述第2面的第2绝缘膜，
所述第2绝缘膜处于所述第2面与所述第1绝缘膜之间。
4.根据权利要求1所述的半导体装置，其中所述第1绝缘膜从所述第1部分连续至所述第2部分为止。
5.根据权利要求1所述的半导体装置，其中所述第1绝缘膜还设置在所述第2面侧。
6.根据权利要求1所述的半导体装置，其中所述第1绝缘膜设置在所述半导体芯片的所有侧面。
7.根据权利要求1所述的半导体装置，其中所述支撑体包含半导体元件。
8.根据权利要求1所述的半导体装置，其中所述第1绝缘膜与所述第1面及所述第1侧面直接接触。
9.根据权利要求8所述的半导体装置，其中所述第1绝缘膜与支撑体直接接触。
10.根据权利要求1所述的半导体装置，其中所述第1绝缘膜包含粘接性树脂。
11.根据权利要求1所述的半导体装置，其中所述配线层与所述第1绝缘膜及所述支撑体直接接触。
12.一种半导体装置的制造方法，其以多个半导体芯片的第1面朝向与衬底相反侧的方式，将所述多个半导体芯片配置在所述衬底，
以覆盖所述第1面与所述多个半导体芯片的侧面的方式形成绝缘体，
将所述绝缘体在所述多个半导体芯片之间切断，形成具有第1绝缘膜的所述多个半导体芯片，所述第1绝缘膜包含设置在所述第1面的第1部分及设置在所述侧面的第2部分，
将所述多个半导体芯片分别从所述衬底拆除，
将作为所述多个半导体芯片之一的第1半导体芯片以所述第1部分朝向支撑体的方式配置在所述支撑体上，
形成配线层，所述配线层设置在所述第1半导体芯片的与所述第1面为相反侧的一面即第2面、所述第2部分及所述支撑体。
13.根据权利要求12所述的半导体装置的制造方法，其中所述配线层将所述支撑体的电极与所述半导体芯片的电极连接。
14.根据权利要求12所述的半导体装置的制造方法，其中所述支撑体为配线衬底。
15.根据权利要求12所述的半导体装置的制造方法，其中所述第1绝缘膜还设置在所述第2面。
16.根据权利要求12所述的半导体装置的制造方法，其中所述多个半导体芯片为逻辑芯片。
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