CN113287192A - 具有改进的电场抑制的高压半导体器件 - Google Patents

具有改进的电场抑制的高压半导体器件 Download PDF

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Publication number
CN113287192A
CN113287192A CN201980088826.9A CN201980088826A CN113287192A CN 113287192 A CN113287192 A CN 113287192A CN 201980088826 A CN201980088826 A CN 201980088826A CN 113287192 A CN113287192 A CN 113287192A
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Prior art keywords
semiconductor device
suppression layer
field
layer
field suppression
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CN201980088826.9A
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Inventor
史蒂芬·戴利·亚瑟
于梁纯
南希·塞西莉亚·斯托费尔
大卫·理查德·埃斯勒
克里斯托弗·詹姆斯·卡普斯塔
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General Electric Co
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General Electric Co
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Publication of CN113287192A publication Critical patent/CN113287192A/zh
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Abstract

提供了一种半导体器件(16)。该半导体器件(16)包括形成在端接区域上的电场(E场)抑制层(36)。E场抑制层(36)图案化为在金属接触区域(66)上形成有开口。E场抑制层(36)的厚度使得当半导体器件(16)在最大电压或低于最大电压下操作时，E场抑制层(36)上方的电场强度低于相邻材料的介电强度。

Description

具有改进的电场抑制的高压半导体器件
技术领域
本文公开的主题涉及半导体器件，更具体地，涉及具有改进的电场抑制的半导体器件。
背景技术
电力电子系统，例如电力转换系统，在现代电气系统中广泛使用以将电力从一种形式转换为另一种形式以供负载消耗。在此功率转换过程中，许多电力电子系统使用各种半导体器件和部件，例如晶闸管、二极管和各种类型的晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、结栅场效应晶体管(JFET)、绝缘栅双极晶体管(IGBT)和其他合适的晶体管。各种半导体器件可以包含在电力电子系统中以控制电路中的电流流动。特别地，可以利用半导体器件，例如晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)或绝缘栅双极晶体管(IGBT))。然而，虽然特定类型的晶体管或其他半导体器件由于选择此类晶体管所提供的某些好处而可用于高功率应用中，但每种类型的晶体管可能存在许多设计考虑和挑战以确保可靠操作。
电力电子系统中一种经常使用的半导体器件是碳化硅金属氧化物半导体场效应晶体管(SiC MOSFET)。SiC MOSFET在高功率、高频功率开关应用中的潜在性能优势已经得到公认。例如，SiC允许高临界电场强度(2-3MV/cm)，该强度比使用在硅(Si)衬底上制造的半导体器件(例如，晶体管)可达到的强度高约10倍。因此，SiC衬底的使用提供了具有高电压、高频和高效性能的器件，因为SiC单极器件(JFET、MOSFET)在电压等级中提供低损耗，而Si单极器件不能。然而，在阻塞(blocking)条件下与SiC材料相关联的高电场(以及电场与SiC表面上方的介电系统的相互作用)使SiC MOSFET器件的设计、制造和测试变得复杂。
特别地，使用SiC作为高压功率器件的材料在功率模块中的晶圆(wafer)形式和晶片(die)形式的制造和高压测试期间提出了挑战。在晶圆形式和晶片形式中，高压端接区域(termination region)通常覆盖有低介电强度的材料，例如当器件为晶圆形式时的空气，以及当器件为模块形式时的硅胶。当在某些条件(例如高压反向偏置条件)下测试器件时，电场会延伸到半导体衬底之外并穿过绝缘层，绝缘层被制造为端接区域上的钝化层。电场强度可能超过钝化层上材料的能力，造成可靠性风险或介电故障(电弧)。
本文描述的实施例可以解决上述挑战中的一个或多个。
发明内容
在一个实施例中，提供了一种半导体器件。该半导体器件包括形成在端接区域上的电场(E场)抑制层。E场抑制层被图案化为在金属接触区域上具有开口。E场抑制层的厚度使得当半导体器件在最大电压或低于最大电压下操作时，E场抑制层上方的电场强度低于相邻材料的介电强度。
在另一个实施例中，提供了包括金属氧化物半导体场效应晶体管(MOSFET)元件的半导体器件。半导体器件还包括形成在MOSFET元件的表面上的一个或多个隔离层。进一步地，半导体器件包括形成在一个或多个隔离层上的图案化的电场(E场)抑制层，其中该E场抑制层被构造为抑制由MOSFET元件产生的电场强度，使得当半导体器件在最大电压或低于最大电压下操作时，E场抑制层上方的电场强度低于相邻材料的介电强度。
在进一步的实施例中，提供了一种半导体器件。该半导体器件包括碳化硅(SiC)衬底、形成在SiC衬底上的端接区域和形成在SiC衬底上的金属接触区域。该半导体器件还包括形成在端接区域上的电场(E场)抑制层，其中该E场抑制层被图案化为在金属接触区域上具有开口，并且其中该E场抑制层包括的厚度使得当半导体器件在最大电压或低于最大电压下操作时，E场抑制层上方的电场强度低于相邻材料的介电强度。
附图说明
当参考附图阅读以下详细描述时，将更好地理解本发明的这些和其他特征、方面和优点，其中贯穿附图，相同的字符代表相同的部分，其中：
图1是根据本公开的实施例的包括半导体器件的电力电子系统的框图；
图2是可用于电力电子系统中的碳化硅(SiC)半导体器件的端接区域的截面图；
图3是根据本公开的实施例的可用于电力电子系统中的碳化硅(SiC)半导体器件的端接区域的截面图；
图4示出了通过各种材料和温度对图3的SiC半导体器件的表面上方的电场强度的建模结果；
图5示出了根据本发明的实施例的制造有E场抑制层的晶圆；
图6A和6B分别示出了根据本发明的实施例制造的SiC半导体器件的一部分的俯视图和侧视图；
图7A和7B分别示出了根据本发明的另一个实施例制造的SiC半导体器件的一部分的俯视图和侧视图；和
图8A和8B分别示出了根据本发明的另一个实施例制造的SiC半导体器件的一部分的顶视图和侧视图。
具体实施方式
下面将描述一个或多个具体实施例。为了提供这些实施例的简明描述，在说明书中并未描述实际实施方式的所有特征。应该理解，在任何此类实际实施方式的开发中，就像在任何工程或设计项目中一样，必须做出许多特定于实施方式的决策来实现开发人员的特定目标，例如遵守与系统相关和与业务相关的约束，这可能因实施方式而异。此外，应当理解，这样的开发工作可能是复杂和耗时的，但是对于受益于本公开的普通技术人员而言，它仍然是设计、制造和制备的例行工作。
除非另外定义，否则本文使用的技术和科学术语具有与本公开所属领域的普通技术人员通常理解的相同的含义。这里使用的术语“第一”、“第二”等不表示任何顺序、数量或重要性，而是用于将一个元件与另一个元件区分开来。此外，当介绍本公开的各种实施例的元件时，冠词“一”、“一种”和“该”旨在表示存在一个或多个元件。术语“包括”、“包含”和“具有”旨在是包括性的，并且意味着除了所列元件之外可能还有其他元件。如果公开了范围，则针对相同部件或性质的所有范围的端点是包括在内的并且可以独立组合。与数量相关的修饰语“大约”包括所述值，并具有上下文规定的含义(例如，包括与特定数量的测量相关联的过程变化或误差的程度)。
如本文所用，术语“层”是指以连续或不连续方式布置在下表面的至少一部分上的材料。此外，除非另有说明，术语“层”并不一定意味着所布置材料的均匀厚度，并且所布置材料可以具有均匀或可变的厚度。此外，除非上下文另有明确规定，否则本文所用的术语“层”是指单层或多层。此外，如本文所用，除非另外具体指明，否则短语“布置在”、“溅射在”或“沉积在”是指层彼此直接接触地布置或通过在其间具有中间层来间接地布置。如本文所用，术语“相邻”是指两层连续布置且彼此直接接触。此外，术语“在…上”描述了层/区域彼此的相对位置并且不一定意味着“在…顶部”，因为上方或下方的相对位置取决于设备对观察者的取向。此外，使用“顶部”、“底部”、“上方”、“下方”、“上”以及这些术语的变体是为了方便起见，除非另有说明，否则不需要部件的任何特定取向。考虑到这一点，如本文所用，术语“下”、“中间”或“底部”指的是特征相对更靠近衬底层的，而术语“顶部”或“上”指的是特定特征离衬底层相对最远。
各种半导体器件可以包括在功率转换系统中。特别地，可以利用半导体器件，例如晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、结型场效应晶体管(JFET)或绝缘栅双极晶体管(IGBT))和功率二极管。应当理解，虽然本文在金属氧化物半导体场效应晶体管(MOSFET)的上下文中描述了本实施例，但是本技术中的一些可以适用于其他类型的半导体器件结构，例如其他类型的晶体管或用于高压系统的其他半导体器件。此外，虽然目前描述的实施例已经被测试以向基于碳化硅的半导体器件(例如，SiC MOSFET)提供特别的益处，但是例如，本实施例还可以向采用其他衬底材料的半导体器件提供益处，其他衬底材料诸如硅(Si)，碳化硅(SiC)、锗(Ge)、氮化铝(AlN)、氮化镓(GaN)、砷化镓(GaAs)、金刚石(C)。
本发明的实施例的技术效果提供了耐用的半导体器件，其可用于高电压系统并且可以晶圆形式在全电压和额定温度下测试而无需用于电弧抑制的特殊探测技术(例如，使用可移除液体介电层进行探测或使用高压探测室)并且可以晶片形式在全电压和额定温度下测试。本实施例提供半导体器件，例如SiC MOSFET器件，其具有某些区域，例如端接区域，覆盖有坚固、柔顺、厚实的介电电场(E场)抑制层，该层与商业制造兼容并且足以将边缘场强度降低到可靠模块使用(其中器件封装在硅胶中)所需的强度以下或空气的介电强度以下，以避免在以晶圆形式或晶片形式探测时产生电弧，即使在额定温度下也是如此。
更具体地，E场抑制层可以被图案化并且布置在器件端接区域上以避免在高压测试下的任何电弧，高压测试例如在全电压和额定高温下的反向偏压。在一个实施例中，E场抑制层是可以以卷或片形式提供和图案化的介电聚酰亚胺。SiC MOSFET上表面上的金属接触区域通过图案化的厚E场抑制层保持暴露，用于引线接合或其他接触方案。E场抑制层可以在晶圆锯切过程中与晶片分离，并保留为未封装晶片的一部分，用于分立封装或用于功率模块，其中E场抑制层可防止与高电场相关联的可靠性故障。E场抑制层的厚度足以抑制或包含在高压测试期间可能出现在SiC MOSFET表面上方的电场电弧。
本实施例的技术效果允许在不使用特殊测试设备并且降低损坏半导体器件或测试设备的风险的情况下在全额定电压和温度下测试半导体器件。提高了对晶圆探测“已知的良好晶片”产量的信心，并降低了可靠性风险。在将晶片组装成高价值组件之前，可以在晶圆级确定介电强度不足(即由于填充问题或气泡导致的端接处(termination)的气隙)导致的质量问题，从而降低与组装后报废设备相关的成本。
此外，所公开的实施例减轻了可能与缺陷相关联的故障，这些缺陷可能只能通过目视检查来检测，但是在器件制造期间目视检查是困难的或不可能的。例如，在半导体器件制造过程中的某些点，可能无法在用于制造器件的透明凝胶或组件中或通过透明凝胶或组件目视检查质量缺陷。这种目视检查通常需要定位由于与半导体器件(例如，SiC MOSFET)的制造相关联的焊合或焊接操作而产生的碎片，或者识别可能影响器件操作或可靠性的其他不希望有的颗粒。无法在某些点进行目视检查可能是由于缺乏视觉能力(没有视线)看到组装中的晶片，或者因为可能没有通过周围材料(例如，凝胶)检查的无损测试方法。有利地，当前描述的在端接区域上具有厚E场抑制层的半导体器件将减轻可能与先前设计中的气泡或颗粒相关联的故障，从而消除在先前设计中可能有益的目视检查的需要，以防止设备故障。因此，本实施例提供提供更高质量和更可靠零件的晶片级全电压额定值。此外，在模块构造中，凝胶中的E场可以保持低于材料额定介电强度额定值，从而避免可能与颗粒和气泡相关联的可靠性问题。
更进一步，根据本文提供的实施例，可以有利地采用功率覆(POL)结构来接合到SiC MOSFET。随着器件电流密度的增加，器件的总电流可能会受到到源极接合的导线连接的载流量(例如，有限的横截面积)的限制。对于具有用于端接处的晶片的相对较大面积的较小晶片尤其如此。如本文所提供的，形成在端接区域上的E场抑制层可以用作POL介电层，其与POL金属化层结合以形成将接合区域重新分布为大于原始焊盘尺寸的POL结构。所公开的POL结构，包括设置在端接区域上的E场抑制层，还可以提供重新金属化以与各种金属类型和各种接合技术兼容。
作为根据当前描述的实施例的进一步技术效果，因为半导体器件的晶片端接区域通常在设计中产生最高场，所以在端接区域处实施E场抑制层可以减少后续器件封装中的电气要求，拓宽了允许的材料特性。这可以允许将较高电压的晶片与较低电压的模块设计特征集成。此外，E场抑制层提供应力缓冲(如果不提供这样的层，则该应力缓冲可能会损坏器件)，这可以允许使用刚性封装材料，从而提供更大体积的器件尺寸或更复杂的3D模块形状。
考虑到前述内容，图1图示了电力电子系统10(例如，电力转换系统、开关系统等)的实施例的框图。电力电子系统10可包括电源12、电气负载14、至少一个半导体器件16(例如，开关器件)和控制器18(例如，电子控制单元)。电源12可以包括交流(AC)电源或直流(DC)电源。在一些实施例中，电源12可以包括电网、发电机、电池等。电源12可以电连接到半导体器件16并且可以向半导体器件16提供电流(例如，AC电流或DC电流)。此外，至少一个半导体器件16可以电连接到电气负载14并且可以向电气负载14供应电流(例如，AC电流或DC电流)。电气负载14可以包括DC负载或AC负载。在某些实施例中，电气负载14可以被配置为存储电力和/或使用电力来执行操作。例如，电气负载14可以包括电池、计算机、电动机等。
半导体器件16可以经由一个或多个有线和/或无线连接通信地联接到控制器18。在一些实施例中，控制器18可包括一个或多个处理器和存储可由该一个或多个处理器执行的指令的一个或多个存储器设备(例如，有形、非暂时性、计算机可读介质)。在某些实施例中，控制器18可以包括逻辑阵列和/或控制电路。控制器18可以被配置为在导通状态(例如，接通状态)和非导通状态(例如，关断状态)之间切换半导体器件16。此外，半导体器件16可以被配置为控制电流从电源12流向电气负载14。特别地，当半导体器件16处于导通状态时，半导体器件16可以允许电流或使电流能够从电源12流到电气负载14。此外，当半导体器件16处于非导通状态时，半导体器件16可以阻止电流从电源流向电气负载14。根据一个实施例，半导体器件16包括碳化硅金属氧化物半导体场效应晶体管(SiC MOSFET)，该晶体管被制造成包括在端接区域上图案化的厚介电层，如上文所概括和下文进一步详细描述的。在一些实施例中，控制器18可以被配置为控制半导体器件16将来自电源12的AC电流转换为DC电流。
图2是可以在图1的电力电子系统10中使用的半导体器件16的一部分的实施例的截面图。特别地，图2所示的半导体器件16是平面n沟道碳化硅金属氧化物半导体场效应晶体管(SiC MOSFET)的一部分，以下称为SiC MOSFET器件20。如前所述，在器件的操作和测试期间，SiC MOSFET器件20的端接区域可能表现出高电场，特别是在某些操作条件下，下面将详细讨论。因此，结合所提供的实验数据和模拟结果来描述图示的SiC MOSFET器件20，以演示某些可靠性问题，该可靠性问题已被识别并且可能与测试晶圆形式和晶片形式的SiCMOSFET器件相关。特别地，仅图示了SiC MOSFET器件20的端接区域以更清楚地描述实验/建模数据以及可能与在全电压和温度额定值下测试SiC MOSFET器件(和其他高压器件)相关联的挑战。
图2所示的SiC MOSFET器件20包括半导体衬底层22、半导体漂移层24、阻塞结26和结端接区域28。在上述实施例中，半导体衬底层22和半导体漂移层24可以包括碳化硅(SiC)。半导体漂移层24可以是第一导电类型的(例如，n型漂移层)并且可以与下面的SiC衬底层22直接交界(即，布置为直接接触)。在一些实施例中，半导体衬底层22可以具有第一导电类型并且可以比半导体漂移层24(例如，n+衬底层)更重地掺杂。阻塞结26可以形成在半导体漂移层24的上部之中或之上，并且可以重掺杂有第二导电类型(例如，p+阻塞结)以在与半导体漂移层24的n型部分的交界处提供PN结。结端接(JTE)区域28被提供作为阻塞结26和半导体漂移层24之间的PN结的端接处。JTE区域28是相对于与阻塞结26的接近度具有渐变掺杂分布的区域。即，JTE区域28可以在与阻塞结26的交界处以第二导电类型(例如，p+)最重地掺杂。随着JTE区域28从与阻塞结26的交界横向延伸更远，JTE区域28逐渐变得较轻掺杂。这种跨JTE区域28从重到轻的渐变掺杂产生电荷的梯度分布并将电场扩展到整个区域。
本文所述的JTE区域28提供了结端接处的说明性示例，更具体地，本文所述的JTE区域28描绘了梯度区JTE的说明性示例。然而，在一些实施例中，具有第二导电类型(例如，p型)的注入区域，例如浮动区域，可以额外地或替代地被实施为具有对应于另一端接处和/或结端接结构的一个或多个特性。例如，注入区域可以实现为单区JTE，其可以包括与中间阱区域接触的单个注入区域，和/或实现为多区JTE，其可以包括两个或更多个连接的注入区域。在一些实施例中，两个或更多个连接的注入区域可以具有相同或不同的特性，并且两个或更多个连接的注入区域中的至少一个可以接触中间阱区域。此外，在一些实施例中，可以实施注入区域以形成多浮区JTE。在这样的实施例中，第一注入区域可以接触中间阱区域，而具有不同间距和/或宽度的一组附加注入区域，例如浮动区域，可以与第一注入区域断开连接并且彼此断开连接地注入。此外，在一些实施例中，可以实施注入区域(例如，浮动区域)以形成浮动场环(FFR)端接处。在这样的实施例中，浮动区域可以彼此断开连接并且与中间阱区域断开连接地注入。此外或替代地，注入区域可以被实施以形成空间调制JTE，其可以包括与中间阱区域接触并且与一组附加注入区域断开连接的第一注入区域，该第一注入区域被注入以形成FFR。因此，可以理解，这里描述的技术可以应用于任何合适的结端接处，例如单区JTE、多区JTE、梯度JTE、多浮动区JTE、FFR、空间调制JTE，以及/或类似的，并且在此描述的实施例旨在是说明性的而非限制性的。
如本文所用，术语“半导体元件”、“晶体管元件”、“有源元件”、“有源器件元件”、“MOSFET元件”等是指构成器件的形成在半导体材料之上、之中、上方或周围的部分的层和材料。这些术语不包括设置在器件表面上的任何介电材料。例如，在所示示例中，SiCMOSFET器件20的半导体元件(晶体管元件、有源元件、有源器件元件)包括半导体衬底层22、半导体漂移层24、阻塞结26和结端接区域28。然而，该术语不包括下面进一步描述的上覆介电或绝缘隔离材料。
如将理解的，SiC MOSFET器件20也可以涂覆有多个介电膜和绝缘层以提供下面的器件的物理和电隔离。例如，SiC MOSFET器件20可以包括钝化层30和介电层32。如下文进一步描述的，当SiC MOSFET器件20在器件完全封装之前处于晶圆形式或晶片形式时，可以在制造后材料或环境34中测试SiC MOSFET器件20。即，当SiC MOSFET 20仍处于晶圆或晶片形式时，本文中使用元件34来指定测试环境。
钝化层30可以包括绝缘材料(例如氧化物和氮化物)的一个或多个薄层，用于在典型的晶圆加工期间形成钝化层。例如，可以通过标准沉积技术沉积形成钝化层30的一个或多个薄层以形成厚度在大约1-10微米(μm)范围内的钝化层30。在下面关于模拟测试详细描述的MOSFET器件20的一个实施例中，钝化层30具有大约1.8μm的厚度。举例来说，表1提供了在标准处理下具有各种膜类型、介电特性和可能厚度的玻璃膜的列表，其可单独使用或彼此组合使用(或与类似材料组合使用)以形成钝化层30。
Figure BDA0003159612410000081
表1
如表1所示，虽然氧化物和氮化物材料的介电强度优异(例如，在3.0E6-10.0E6V/cm的范围内)，但钝化层30中的材料的厚度为通常使用标准沉积技术限制为小于10μm。因此，钝化层30为SiC MOSFET器件20的端接区域提供了一些电隔离。然而，如下所述，这种电隔离可能不足以在高压操作期间完全隔离活性材料。
为了进一步提供SiC MOSFET器件20的下面的端接区域的电隔离，可以在钝化层30上形成介电层32。根据晶圆处理中采用的标准沉积技术，聚酰亚胺(或类似材料)可以单独沉积或彼此组合沉积以形成介电层32。举例来说，表2提供了各种聚酰亚胺的列表，这些聚酰亚胺可以被考虑用于晶圆上端接区域覆盖并且可以通过晶圆处理中使用的标准技术来沉积。
Figure BDA0003159612410000091
表2
从表2可以明显看出，虽然聚酰亚胺材料的介电强度良好(例如，在2.75E6–4.70E6V/cm的范围内)，但介电层32中材料的厚度通常使用标准沉积技术被限制为小于15μm。虽然介电层32可以进一步隔离SiC MOSFET器件20的端接区域，但是该层与钝化层30结合可能不足以在高压操作期间完全隔离器件。
当SiC MOSFET器件20已被制造但仍处于晶圆形式时，可以在端接区域处对器件进行电探测以进行可靠性和功能测试。即，在晶片被分离和封装之前测试晶圆形式的SiCMOSFET器件20以识别已知良好芯片是有益的。越早识别缺陷，最终将报废的进一步处理设备浪费的时间和材料就越少。通过测试晶圆形式(并且再次晶片形式，在进一步封装之前)的SiC MOSFET器件20，可以及早识别已知的良好晶片。因此，当SiC MOSFET器件20为晶圆形式时，通常在制造后材料(环境)34(例如空气或凝胶)中进行探测。值得注意的是，为了使电气测试具有最佳意义，应该在SiC MOSFET器件20被额定进行的所有可能的操作温度和电气限制范围内对SiC MOSFET器件20进行测试。然而，基于在高压下在端接区域产生的高E场，晶圆形式的SiC MOSFET器件20的电气探测在全额定功率和温度下可能存在问题。例如，考虑到制造后材料34可以包括表3中提供的材料之一。
Figure BDA0003159612410000092
表3
值得注意的是，在标准温度和压力(STP)下，干燥空气的介电强度是制造后材料或测试环境34中最低的。因此，在测试晶圆形式的SiC MOSFET器件20时，SiC MOSFET器件20应该能够在干燥空气中测试到其最高额定电压操作，同时保持在SiC MOSFET器件20的表面可测量的E场强度至等于或低于3.0E4 V/cm的水平。具有厚度小于10μm的玻璃膜钝化层30和厚度小于15μm的聚酰亚胺介电层32的上述SiC MOSFET器件20的各种实施例的测试结果表明，在没有附加材料的情况下，图2所示的设计不足以在典型的制造后材料34中提供完全的电隔离。具体而言，在空气中的反向偏置条件(1700V)下测试SiC MOSFET器件20的模拟结果表明，电场强度的可测量幅度约为2.7E5 V/cm，远高于空气中表面处的为3.0E4 V/cm的目标最大E场强度。即，所描述的钝化层30与介电层32的组合不提供必要的保护以避免在没有专用测试设备的情况下，以晶圆或晶片形式在MOSFET器件20的高温额定极限(例如，175℃–200℃)和MOSFET器件20在凝胶或空气中的高电压额定极限(例如，在完全反向偏置条件下为1700V)下进行测试期间产生电弧。
为了在晶圆测试和晶片测试期间，但在SiC MOSFET器件20的完成封装之前，减轻在SiC MOSFET器件20的端接区域上形成的材料上方产生电弧的可能性，根据本发明的实施例，E场抑制层(图示和以下关于图3-7B进一步描述的)在此公开。E场抑制层提供了SiCMOSFET器件20的端接区域的进一步电隔离，使得可以在所有额定温度和电压下以晶圆和晶片形式可靠地测试器件。
在选择用于可以沉积、布置或通常形成在所示介电层32顶部的E场抑制层的材料时，进行了某些设计考虑。由于介电层32的材料具有良好的特性，包括高介电强度，因此研究了类似的介电材料用于E场抑制层。因此运行模拟以模拟在钝化层30和介电层32上具有附加介电材料的SiC MOSFET器件20的结果，以确定具有在2.0E6–5.0E6 V/cm的范围内的E场强度和在2.9-3.6的范围内的介电常数的介电材料的适当厚度，以形成E场抑制层，从而可靠地测试SiC MOSFET器件20。
图3示出了具有形成在介电层32上的E场抑制层36的SiC MOSFET器件20。根据本文所述的实施例，E场抑制层36在全温度和额定电压下提供在晶圆形式或晶片形式的SiCMOSFET器件20的端接区域上产生的电场的充分隔离。如将关于图4中所示的模拟测试结果所描述的，取决于为下面的钝化层30和介电层32选择的厚度和材料，当使用具有在2.0E6–5.0E6 V/cm范围内的E场强度和在2.9-3.6的范围内的介电常数的材料时，E场抑制层36的足够厚度T被发现在大约80μm–100μm的范围内。E场抑制层36的厚度T的该范围还在空气的“最坏情况”测试环境中提供足够的电隔离。如将理解的，如果钝化层30或介电层32的介电强度和/或厚度增加，则E场抑制层36的厚度T可以减小到低于大约80μm-100μm的范围。在某些实施例中，厚度T可以更大。例如，在其他实施例中，厚度T可以在大约50μm–200μm的范围内。然而，这些材料和典型制造设施中通常可用的沉积技术的选择可能会将材料选择和厚度能力限制到与关于表1和2中描述的那些材料和厚度类似的材料和厚度。此外，如果已知测试环境(即，制造后材料34)是除空气之外的其他物质(例如，硅胶)，则也可以减小E场抑制层36的厚度，如下文关于图4进一步描述地。
如还将描述的，基于模拟测试结果，许多传统技术无法将材料(例如上述表2中描述的那些)沉积到适当的厚度范围，该模拟测试结果表明，对于具有在2.0E6–5.0E6 V/cm范围内的E场强度和在2.9–3.6范围内的介电常数的材料，E场抑制层36的厚度T在大约80μm-100μm的范围内。因此，本文公开了其他形式的材料，作为用于E场抑制层36的可选材料。例如，聚酰亚胺、聚苯并恶唑(PBO)或两者的混合物可用作E场抑制层36。这些材料可以作为液体电介质施加到芯片表面，该液体电介质被分配固化和图案化。该材料可以是纺铸的、浸涂的、喷涂的或丝网印刷的。还可以使用可包括丝网印刷、气溶胶喷射印刷、凹版印刷或注射器分配的添加剂技术来附加地施加液体树脂材料。在一个实施例中，用于E场抑制层36的厚电介质可以作为聚酰亚胺(例如Kapton牌)的片状或卷状干膜提供。虽然片状形式的聚酰亚胺大体在下面被描述为该E场抑制层36的材料候选物并且已经被证明用于其实验验证，但是其他高温介电材料可以片状形式获得。例如，聚醚酰亚胺(Ultem)、聚酰亚胺、聚醚酰亚胺、液晶聚合物(LCP)聚砜、聚醚醚酮(PEEK)、聚亚芳基醚酮、环氧树脂、以及聚苯并恶唑和含氟聚合物或环氧树脂也可提供100至500微米厚的片材和也可以考虑。
参考图4，示出了模型结果40。具体地，SiC MOSFET器件20被建模，具有钝化层30和介电层32，钝化层30和介电层32具有与上文关于表1和2所述的那些相似的特性并且具有形成在其上的E场抑制层(例如，聚酰亚胺材料)36。通过模拟聚酰亚胺的E场强度的模拟测量(沿y轴42)被绘制为离半导体SiC MOSFET器件20表面的距离(沿x轴44)的函数，以确定聚酰亚胺E场抑制层36的厚度，从而充分抑制凝胶或空气中在最极端操作条件(例如，在完全反向偏压条件下为1700V)下产生的电场。也就是说，可以确定聚酰亚胺E场抑制层36的厚度的选择，使得E场抑制层36的电场强度大于或等于测试环境(即，制造后材料34)的介电强度。如果制造后材料34的介电强度随温度变化(例如硅胶)，则可以提供进一步的考虑。
再次参考表3，如果硅胶是制造后材料34，则硅胶在室温(25℃)下的介电强度约为1.75E5 V/cm，在175℃时约为1.0E5 V/cm。在SiC MOSFET器件20的标准操作范围内，空气的介电强度约为3.0E4。因此，应该选择E场抑制层36的厚度以可靠地抑制可能在SiC MOSFET器件20的端接区域上方产生的任何E场。再次返回到图4，这三种条件下的模拟测试结果表明了E场抑制层36的最小厚度，以确保在SiC MOSFET器件20的整个电压和温度范围内进行可靠测试。
具体而言，曲线46通过聚酰亚胺的厚度对电场强度进行模拟，并因此为E场抑制层36提供阈值厚度以在1700V下提供对电场的充分抑制。如果要测试器件的制造后材料34是硅胶并且SiC MOSFET器件20在室温下操作，则E场抑制层的大约25μm的阈值厚度将降低电场强度至小于1.75E5 V/cm，这足以抑制可能在端接区域上方产生的最大E场，如曲线46上的点48所示。如果制造后材料34是硅胶并且MOSFET器件20在175℃的温度下操作，则E场抑制层36的大约44μm的阈值厚度将减小电场强度至小于1.0E5 V/cm，这足以抑制可能在端接区域上方产生的最大E场，如曲线46上的点50所示。如果制造后材料34是空气并且MOSFET器件20在任何温度下操作，则E场抑制层36的大约94μm的阈值厚度将把该层上方的电场强度降低到小于3.0E4V/cm，这足以抑制可能在端接区域上方产生的最大E场，如曲线46的点52所示。因此，为了允许“最坏情况”的测试场景，其中测试环境(即，制造后材料34)是空气，应选择大约94μm的总介电厚度以在MOSFET器件20的额定电压和温度下进行测试期间减轻可靠性风险和/或介电故障(即，电弧)。即，钝化层30、介电层32和E场抑制层36的组合厚度应为大约94μm(或更大)，以确保可靠的测试。因此，在钝化层30的厚度约为1.8μm，介电层32的厚度约为12μm的实施例中，E场抑制层36的厚度应大于或等于约82.2μm。
图5示出了包括多个SiC MOSFET器件20的测试晶圆60，多个SiC MOSFET器件20根据本实施例制造并测试以提供实验验证。提供晶圆60的一部分62的放大视图以更好地说明SiC MOSFET晶片20。根据本实施例，每个晶片包括E场抑制层36。为了晶圆形式的测试和验证目的，钝化层30(不可见)被沉积到大约1.8μm的厚度。以卷状提供的聚酰亚胺Kapton膜粘附到晶圆上并提供E场抑制层36。E场抑制层36和下面的介电层32的组合厚度约为87μm。在膜(E-场抑制层36)对准并粘附到晶圆之前，E场抑制层36经由激光烧蚀图案化以暴露栅极金属64和源极焊盘66用于探测。SiC MOSFET器件20是额定1200伏的SiC器件，其在室温至200℃的测试温度下以全击穿电压进行探测，没有观察到电弧。事实上，使用这些材料和厚度，发现E场抑制层36在一直操作到大约1800伏时可靠地包含电弧。值得注意的是，E场抑制层36可以是可以被图案化(在沉积或放置到晶圆上之前或之后)以暴露下面的接触结构并且提供对可能由SiC MOSFET器件20的半导体元件在正常额定操作条件(例如，电压和温度)期间产生的任何电场的充分抑制的任何材料。
现在参考图6A和6B，描述了本发明的实施例的其他特征和益处。具体地，图6A图示了单个SiC MOSFET 20的顶视图，并且图6B图示了SiC MOSFET器件20的侧视图。如图所示，SiC MOSFET 20包括E场抑制层36，其被图案化以暴露源极金属焊盘66。如前所述，E场抑制层36的厚度T(例如，80μm-100μm)足以包含当SiC MOSFET器件20操作在其最高额定电压(例如1700V)时可能在端接区域产生的任何电场70。除了前面描述的厚E场抑制层36的好处之外，因为电场70被降低到E场抑制层36内所关注的水平以下，所以可能存在于E场抑制层36的顶表面上的任何颗粒、碎片或气泡将不会影响器件的操作。因此，当稍后封装SiC MOSFET器件20时，从而消除了目视检查器件20的表面是否存在此类碎屑的能力，任何颗粒、碎屑或气泡(在封装材料中)的有害影响将被减轻，因为在E场抑制层36内，由于电场70的减少，任何颗粒将不会与残余电场发生反应。此外，图6A和6B中示出了电联接到源极金属焊盘66以提供到SiC MOSFET器件20的电连接的接合元件72。在一个实施例中，接合元件72是铝楔接合元件，其可以将SiC MOSFET器件20电联接到外部元件、器件或系统。应当理解，在某些实施例中可以使用其他类型的接合元件(例如，焊线、带等)和其他导电金属(例如，铜、金等)。
图7A和7B分别示出了SiC MOSFET器件20的替代实施例的顶视图和侧视图，其具有改进的接合结构，利用了电场抑制层36。为了增加接合元件72的数量并为SiC MOSFET器件20提供更好的电流密度，在整个SiC MOSFET器件20上提供了额外的金属化层74。有利地，除了上述优点之外，E场抑制层36还可以提供介电层作为金属化层74和SiC MOSFET器件20的下方有源区域之间的绝缘势垒。在该实施例中，E场抑制层36和金属化层74结合以提供功率覆盖(POL)结构。POL结构可以有利地用于接合到SiC MOSFET器件20。随着器件电流密度的增加，器件的总电流可能受到连接到源极接合处的导线的载流量(例如，有限的横截面积)的限制。对于具有用于端接处的晶片的相对较大面积的较小晶片尤其如此。如本文所提供，形成于端接区域上的E场抑制层36可用作POL介电层，其与POL金属化层74结合以形成将接合面积重新分布为大于原始焊盘尺寸(即，源极金属焊盘66)的POL结构，同时保持与SiCMOSFET器件20的下面的有源区的电隔离。所公开的POL结构，结合设置在端接区域上的E场抑制层36，还可以提供重新金属化以与各种金属类型和各种接合技术兼容。例如，金属化层74可以是铜(Cu)和镍金(NiAu)以更好地结合。因为金属化层74的尺寸大于下面的源极金属焊盘66，所以可以增加接合元件72的数量。在一实施例中，接合元件72是铝楔形接合元件。在另一个实施例中，接合元件72是铜楔形接合元件。应当理解，在某些实施例中可以使用其他类型的接合元件(例如，焊线、带等)和其他导电金属。
图8A和8B分别示出了SiC MOSFET器件20的替代实施例的顶视图和侧视图，其具有改进的接合结构，利用E场抑制层36和可以降低操作期间封装的导通电阻的接合元件72。与图7A和7B所示的实施例一样，当前所示的实施例包括用于在更大面积上重新分布接合区域的POL结构。POL结构包括E场抑制层36(POL电介质)和金属化层74。金属化层74可以是铜(Cu)和镍金(NiAu)以更好地接合。在所示的实施例中，接合元件72可以是铜带或铜夹接合元件，其可以使用例如焊料76电和物理联接到下面的金属化层74。应当理解，可以使用其他导电粘合剂代替焊料76。有利地，铜夹接合的使用可以降低操作期间封装的导通电阻。
该书面描述使用示例来公开本发明，包括最佳模式，并且还使本领域技术人员能够实践本发明，包括制造和使用任何设备或系统以及执行任何合并的方法。本发明的可专利范围由权利要求限定，并且可以包括本领域技术人员想到的其他示例。如果这些其他示例具有与权利要求的字面语言没有区别的结构要素，或者如果它们包括与权利要求的字面语言没有实质性差异的等效结构要素，则这些其他示例旨在在权利要求的范围内。

Claims (27)

1.一种半导体器件，其特征在于，包括：
电场(E场)抑制层，所述电场(E场)抑制层形成在端接区域上，其中所述E场抑制层被图案化为在金属接触区域上具有开口，并且其中所述E场抑制层包括厚度，使得当所述半导体器件在最大电压或低于最大电压下操作时，所述E场抑制层上方的电场强度低于相邻材料的介电强度。
2.根据权利要求1所述的半导体器件，其特征在于，其中所述器件包括晶体管、二极管、MOSFET、JFET、IGBT或晶闸管。
3.根据权利要求1所述的半导体器件，其特征在于，进一步包括：
衬底；
半导体漂移层，所述半导体漂移层形成于所述衬底上；
阻塞结，所述阻塞结形成于所述漂移层中；和
结端接区域，所述结端接区域形成在所述半导体漂移层中并且与所述阻塞结横向相邻。
4.根据权利要求3所述的半导体器件，其特征在于，其中所述衬底或所述漂移层中的至少一个包括碳化硅(SiC)。
5.根据权利要求1所述的半导体器件，其特征在于，其中所述最大电压为900伏至10KV。
6.根据权利要求1所述的半导体器件，其特征在于，进一步包括形成在所述E场抑制层下方的钝化层。
7.根据权利要求6所述的半导体器件，其特征在于，包括形成在所述钝化层上且在所述E场抑制层下方的介电层。
8.根据权利要求1所述的半导体器件，其特征在于，其中所述E场抑制层包括在大约50μm–200μm的范围内的厚度。
9.根据权利要求1所述的半导体器件，其特征在于，其中所述E场抑制层包括聚酰亚胺、聚苯并恶唑(PBO)、环氧树脂、双苯并环丁烯(BCB)、聚醚酰亚胺(Ultem)、聚醚酰亚胺、液晶聚合物(LCP)、聚砜、聚醚醚酮(PEEK)、聚亚芳基醚酮、含氟聚合物或它们的组合。
10.根据权利要求1所述的半导体器件，其特征在于，包括功率覆盖(POL)结构，所述功率覆盖(POL)结构被构造为扩大下方接合区域，其中所述POL结构包括：
所述E场抑制层；和
金属化层，所述金属化层至少部分地形成在所述E场抑制层上方。
11.根据权利要求10所述的半导体器件，其特征在于，其中所述金属化层是重新金属化层。
12.根据权利要求10所述的半导体器件，其特征在于，其中所述金属化层延伸到所述开口中，并且其中所述金属化层通过所述开口电联接到所述金属接触区域。
13.根据权利要求1所述的半导体器件，其特征在于，其中所述E场抑制层包括适用于干膜形式的材料。
14.一种半导体器件，其特征在于，包括：
金属氧化物半导体场效应晶体管(MOSFET)元件；
一个或多个隔离层，所述一个或多个隔离层形成在所述MOSFET元件的表面上；和
图案化的电场(E场)抑制层，所述电场(E场)抑制层形成在所述一个或多个隔离层上，其中所述E场抑制层被构造为抑制由所述MOSFET元件产生的电场强度，使得当所述半导体器件在最大电压或低于最大电压下操作时，所述E场抑制层上方的电场强度低于相邻材料的介电强度。
15.根据权利要求14所述的半导体器件，其特征在于，其中所述一个或多个隔离层包括钝化层和介电层。
16.根据权利要求14所述的半导体器件，其特征在于，其中所述E场抑制层包括聚酰亚胺、聚苯并恶唑(PBO)、环氧树脂、双苯并环丁烯(BCB)、聚醚酰亚胺(Ultem)、聚醚酰亚胺、液晶聚合物(LCP)、聚砜、聚醚醚酮(PEEK)、聚亚芳基醚酮、含氟聚合物或它们的组合。
17.根据权利要求14所述的半导体器件，其特征在于，其中所述E场抑制层包括在大约50μm–200μm的范围内的厚度。
18.根据权利要求14所述的半导体器件，其特征在于，其中所述E场抑制层覆盖所述MOSFET元件的端接区域，并且其中所述E场抑制层被图案化以暴露所述SiC MOSFET元件的下方栅极焊盘、源极焊盘或两者。
19.根据权利要求18所述的半导体器件，其特征在于，进一步包括金属化层，所述金属化层至少部分地设置在所述E场抑制层上方并延伸到所述图案化的E场抑制层的开口中，使得所述金属化层电联接到所述SiC MOSFET元件的所述下方栅极焊盘、所述源极焊盘或两者。
20.根据权利要求19所述的半导体器件，其特征在于，其中所述金属化层包括大于所述SiC MOSFET元件的所述下方栅极焊盘、所述源极焊盘或两者的面积的面积。
21.如权利要求14所述的半导体器件，其特征在于，其中所述MOSFET元件包括碳化硅(SiC)。
22.一种半导体器件，其特征在于，包括：
碳化硅(SiC)衬底；
端接区域，所述端接区域形成在所述SiC衬底上；
金属接触区域，所述金属接触区域形成在所述SiC衬底上；和
电场(E场)抑制层，所述电场(E场)抑制层形成在所述端接区域上，其中所述E场抑制层被图案化为在金属接触区域上具有开口，并且其中所述E场抑制层包括厚度，使得当所述半导体器件在最大电压或低于最大电压下操作时，所述E场抑制层上方的电场强度低于相邻材料的介电强度。
23.根据权利要求22所述的半导体器件，其特征在于，其中所述E场抑制层包括在大约50μm–200μm的范围内的厚度。
24.根据权利要求22所述的半导体器件，其特征在于，其中所述E场抑制层包括在大约80μm–100μm的范围内的厚度。
25.根据权利要求22所述的半导体器件，其特征在于，包括金属化层，所述金属化层至少部分地形成在所述E场抑制层上方。
26.根据权利要求25所述的半导体器件，其特征在于，其中所述金属化层延伸到所述开口中，并且其中所述金属化层通过所述开口电联接到所述金属接触区域。
27.如权利要求22所述的半导体器件，其特征在于，其中所述E场抑制层包括聚酰亚胺、聚苯并恶唑(PBO)、环氧树脂、双苯并环丁烯(BCB)、聚醚酰亚胺(Ultem)、聚醚酰亚胺、液晶聚合物(LCP)、聚砜、聚醚醚酮(PEEK)、聚亚芳基醚酮、含氟聚合物或它们的组合。
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