WO2016103434A1 - 半導体装置およびその製造方法、並びに半導体モジュール - Google Patents
半導体装置およびその製造方法、並びに半導体モジュール Download PDFInfo
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- WO2016103434A1 WO2016103434A1 PCT/JP2014/084456 JP2014084456W WO2016103434A1 WO 2016103434 A1 WO2016103434 A1 WO 2016103434A1 JP 2014084456 W JP2014084456 W JP 2014084456W WO 2016103434 A1 WO2016103434 A1 WO 2016103434A1
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Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a power semiconductor device using silicon and silicon carbide as raw materials and a manufacturing method thereof.
- SiC silicon carbide
- SiC has an electric field strength that is an order of magnitude higher than that of silicon and is suitable for high-voltage applications. Its thermal conductivity is three times that of silicon, and its semiconductor properties are unlikely to be lost even at high temperatures. It is strong and suitable as a power semiconductor material because it can lower the resistance of the element.
- SiC Schottky barrier diode S chottky B arrier D iode
- Switching elements in addition to the rectifier element also has a full SiC module silicon IGBT (hereinafter Si-IGBT) was replaced by MOS (M etal O xide S emiconductor ) of SiC, loss reduction effect is further increased. This is because the switching loss can be reduced by replacing the Si-IGBT of the bipolar element with the SiC-MOS of the unipolar element by the same principle as when the silicon PN diode is replaced with the SBD of SiC.
- the full SiC module there is also a method in which the SBD is omitted and the rectification function is handled on the MOS side.
- SBD and MOS can be manufactured with silicon, but if the thickness of the body layer is increased in order to increase the withstand voltage, the resistance increases, which is not practical.
- SiC low-resistance SiC, it is possible to apply SBDs and MOSs of unipolar elements to high breakdown voltage regions where conventional silicon SBDs and MOSs, such as withstand voltages of 600 V to 3.3 kV, could not be applied.
- SiC has a high dielectric breakdown electric field strength
- the SiC sealing material is required to have high dielectric breakdown strength.
- the electric field strength exceeds the electric field strength (dielectric breakdown field strength) of silicone gel. Therefore, a method of inserting a high electric field sealing material between them is disclosed (Patent Document 1). According to this method, since the electric field strength in the silicone gel can be suppressed within the range of the electric field resistance in the vicinity of the termination region of the SiC chip, the reliability of the semiconductor device using SiC can be improved.
- FIG. 2 is a top view of one of the SiC chips constituting the power semiconductor module using SiC
- FIG. 3 is a cross-sectional view.
- FIGS. 4a and 4b are formed by superposing the formation region 30 of the high electric field sealing material on this
- FIG. 4a is a top view of the SiC chip
- FIG. 4b is a cross-sectional view of the SiC chip.
- 2, 3, 4 a, and 4 b are diodes, and there is a termination region 32 around the electrode 31.
- a high electric field resistant seal A stop material 34 is arranged.
- the formation of the high electric field sealing material is performed in a state where the chip is mounted on an insulating substrate.
- the insulating base 22 is mounted using solder 35 and the wire 13 is mounted. Is shown in a partial cross-section in a state where they are joined and covered with a gel 36 as a sealing material.
- the shape of the end portion 38 of the high electric field sealing material has a tapered shape with a skirt due to the forming method by the coating technique.
- the film thickness is particularly thin in the vicinity of the outer periphery of the chip, and the electric field from SiC cannot be sufficiently relaxed.
- the termination region width 39 is designed to be sufficiently wide, the electric field in this portion can be reduced, but in this case, the termination region that hardly contributes to electrical conduction on the expensive SiC chip is widened, resulting in an increase in cost. To do.
- a method for increasing the film thickness of the chip end portion of the high electric field sealing material is necessary so that the electric field at the end portion can be relaxed even if the termination region is reduced. .
- the second problem is caused by the TAT (turnaround time) of production and insufficient coating accuracy.
- the application process flow of the high electric field sealing material in the prior art is shown in FIG.
- the high electric field sealing material application step 40 is arranged after the step 41 for bonding the chip to the insulating substrate.
- the state of the coating process 40 is shown in FIG.
- the high electric field sealing material 34 is applied by a dispenser or the like so as to go around the termination region 32 of the SiC-SBD chip 12 soldered on the insulating substrate 22. It is necessary to repeatedly apply all the chips mounted on the insulating substrate while aligning the horizontal position and height of the coating nozzle 42 for each chip on the insulating substrate, and the production process takes time. After application, it is necessary to heat-treat the high electric field sealing material, and at this time, it is necessary to heat-treat each insulating substrate for several hours.
- each chip is soldered to an insulating substrate, but the solder is liquefied during reflow, causing variations in thickness, horizontal movement, and rotation, so the alignment is slightly different for each chip.
- the dispenser is equipped with a function of optically recognizing the chip position and correcting it, there is a problem that the application accuracy is likely to be lowered and a trade-off that increases the application time when the accuracy is improved.
- the inventors have proposed a new structure and manufacturing method of a semiconductor device described below.
- the semiconductor device of the present invention includes, for example, a semiconductor chip on which a wide gap semiconductor element is formed, and the cross-sectional shape of the high electric field sealing material formed on the periphery of the chip on the pattern surface side of the semiconductor chip is At least a part of the outer peripheral end side has a vertical or near end face shape, and the inner peripheral end side of the chip has a shape in which the film thickness decreases inward.
- the semiconductor device manufacturing method of the present invention is, for example, a semiconductor device manufacturing method including a semiconductor chip on which a wide gap semiconductor element is formed, and is disposed in the peripheral portion of the chip on the pattern surface side of the semiconductor chip. Forming a high electric field sealing material to be formed in a semiconductor wafer state, performing a heat treatment on the semiconductor wafer, and performing a dicing on the heat-treated semiconductor wafer.
- the semiconductor module of the present invention is, for example, a semiconductor module on which a semiconductor chip on which a wide gap semiconductor element is formed is mounted, and the semiconductor chip is formed in a peripheral portion of the chip on the pattern surface side of the semiconductor chip.
- the cross-sectional shape of the high electric field sealant has a shape in which at least a part of the chip outer peripheral end side is perpendicular or close to the end face shape, and the film thickness decreases inward on the inner peripheral end side of the chip. It is characterized by.
- the electric field strength is set so as not to exceed the dielectric breakdown electric field strength of a sealing material such as silicone gel for sealing the same.
- a sealing material such as silicone gel
- FIG. 1 It is sectional drawing which shows the semiconductor device which concerns on Example 1 which is one of typical embodiment of this invention. It is a top view of a SiC chip. It is sectional drawing of a SiC chip. It is a top view of the SiC chip which piled up the formation field of the high electric field sealing material. It is sectional drawing of the SiC chip which piled up the formation area of the high electric field sealing material. It is a figure which shows the mounting state by a prior art. It is a figure which shows the application
- FIG. 9 is an enlarged view of an insulating substrate mounted on the semiconductor module of FIG. 8. It is a figure which shows the flow of the main processes including the formation process of the high electric field sealing material in the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is a figure which shows the mode of the formation process of the high electric field sealing material in the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is a figure which shows the formation process of the high electric field sealing material in the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is a figure which shows the process of dicing the wafer in the manufacturing method of the semiconductor device which concerns on Example 1 of this invention.
- FIG. 6 is an enlarged view of a SiC-MOS in which a gate electrode pad is centrally arranged in Example 2 of the present invention.
- FIG. 6 is an enlarged view of a SiC-MOS in which the gate electrode pad according to the second embodiment of the present invention is arranged near the electrode end.
- the cross section of the high electric field sealing material formed in the vicinity of the termination region around the chip has a shape that is at least partially perpendicular to the outer peripheral end of the chip, Is characterized by having a shape in which the film thickness decreases inward.
- one or a plurality of configurations are used from among polyamideimide resin, polyetheramideimide resin, and polyetheramide resin.
- a manufacturing method in which a chip is mounted after a high electric field sealing material to be disposed in the vicinity of a termination region around the chip is formed in the state of a semiconductor wafer, subjected to heat treatment, and diced.
- the high temperature heat treatment in the chip mounting process is also applied to the high electric field sealing material.
- the temperature is preferably increased from 200 ° C.
- An additional heat treatment in the range of 360 ° C. is performed.
- the high electric field sealing material can be formed in a thick shape at the outer peripheral edge of the chip, it is possible to cope with a termination structure designed to reduce the area efficiently so that a high electric field is reached to the chip edge. The cost can be reduced by reducing the area.
- the TAT of the manufacturing process can be reduced.
- each chip in the state of a semiconductor wafer having uniform inclinations at equal intervals it is possible to improve the accuracy of the process for forming a high electric field sealing material and the inspection process.
- Supplementary information related to the inspection process is that the withstand voltage test on the wafer is facilitated by forming the high electric field sealing material in the wafer state.
- a pressure resistance test is performed without a sealant, air discharge will occur in excess of the pressure resistance in the air when a high voltage is applied, so there is a special incident that prevents discharge by dropping Fluorinert or locally increasing the pressure. Equipment was needed.
- the above-mentioned incidental facilities are unnecessary, and the inspection process can be simplified and speeded up.
- a semiconductor module (SiC hybrid module) having a withstand voltage of 3.3 kV and a current capacity of 1200 A mounted with a Si-IGBT as a switching element group and a SiC-SBD as a diode element group is mounted.
- SiC hybrid module SiC hybrid module having a withstand voltage of 3.3 kV and a current capacity of 1200 A mounted with a Si-IGBT as a switching element group and a SiC-SBD as a diode element group is mounted.
- Si-IGBT Si-IGBT
- SiC-SBD SiC-SBD
- the external appearance and internal configuration of the semiconductor module are as shown in FIG. 8, and four insulating substrates 22 are mounted therein.
- An enlarged view of the insulating substrate 22 is shown in FIG.
- An enlarged view of the SiCD-SBD is as shown in FIG. 2, and a termination region 32 is arranged outside the electrode 31 of the anode.
- the high electric field sealing material is formed so as to completely cover the termination region 32.
- the chip and insulating substrate 22 including the termination region 32 are sealed with a silicone gel 36 inside the case as shown in FIG.
- FIG. 11 schematically shows a process 40 for forming a high electric field sealing material.
- a high electric field sealing material 34 is formed on the scribe line 45 in a wafer state.
- the forming method is performed by applying a paste-like high electric field sealing material 34 in a lattice shape with a dispenser.
- the nozzle In the conventional method, there is misalignment of the tip tilt, in-plane position, rotation and the like due to soldering variation for each chip, and a highly accurate position correction technique is required for the dispenser for coating. Since the application amount is sensitive to the distance between the nozzle and the object, in addition to the in-plane position correction of the nozzle by image recognition, the sensor has a function of detecting the distance to the chip and correcting the inclination for application. However, in the method described here, the alignment with respect to the entire wafer is performed only once, and then the in-plane position is recognized by the image, and the application with the same accuracy is performed without requiring the height adjustment function. Is possible. In addition to reducing the cost of the coating apparatus, the recognition time in the coating process and the time required to move the nozzle for each chip are reduced, so that an effect of shortening the manufacturing time can be obtained.
- heat treatment for curing is performed.
- Heat treatment conditions were as follows: (1) 100 ° C, 30 minutes, (2) 200 ° C, 1 hour of conventional curing, and (3) inert atmosphere, 300 ° C, 1 hour.
- degassing can be suppressed even in a high-temperature heat treatment (maximum 355 ° C.) in the subsequent chip mounting process.
- the relationship between heat treatment and degassing can be evaluated by, for example, a TDS apparatus (temperature-programmed desorption gas analyzer).
- Outgassing is reduced by processing at a temperature of 200 ° C. or higher, which has not been conventionally used.
- the maximum temperature should just be below the maximum temperature of a subsequent chip mounting process, and if it is 400 degrees C or less, it is in the tolerance range of a high electric field sealing material.
- the application of the high electric field sealant is performed in a lattice pattern along the scribe line of the wafer, and as shown in FIG. 12, the surplus sealant spreads at the intersections 47 in the horizontal and vertical directions, thus terminating.
- the corner portion 48 of the region can be effectively covered.
- a characteristic inspection process 49 in the wafer state is performed.
- the termination region where the electric field strength is strong is covered with the high electric field sealing material 34, so that the discharge in the atmosphere is suppressed, so that the high voltage application test is facilitated.
- a process of dicing the cured wafer along the scribe line is schematically shown in FIG.
- the process proceeds to the step of bonding the chip to the insulating substrate (41 in FIG. 10). Since high-temperature solder is used here for chip bonding, heat treatment is performed in a reducing atmosphere at a maximum of 355 ° C. A step 43 of performing wire bonding on the bonded chip electrodes follows.
- the assembly process of the SiC hybrid power module of the present invention is completed after the step 51 of joining the insulating substrate to the base plate which is the bottom surface of the module connected to the heat sink, and the module assembly process set 52 such as case adhesion and gel encapsulation. To do.
- FIG. 14 is an enlarged cross-sectional view of a process of forming a high electric field sealing material in a wafer state.
- the high electric field sealing material 34 discharged from the application nozzle 42 of the dispenser is applied onto the termination region 32 on the wafer, the paste-like high electric field sealing material spreads slightly and both ends gradually become films.
- a tapered shape 54 with a reduced thickness is formed, resulting in a shape indicated by 55 in FIG.
- the merit of forming the tapered shape 54 toward the inner periphery of the chip is as follows. First, since the electrode 31 has an equipotential surface, the electric field from the termination region 32 spreads around the electrode end boundary 56 when viewed in cross section. Similarly, a tapered shape 54 in which a film of a high electric field sealing material is formed at a substantially constant distance from the electrode end boundary 56 is an ideal shape without waste. For example, a wire bonding junction (see FIG. 5). 57) is close to the end of the electrode due to misalignment, the rising portion of the heel 58 of the joint is unlikely to interfere with the high electric field sealing material.
- the taper shape is determined by the application conditions and the boundary is automatically formed, there is a great merit that no additional patterning step is required inside the electrode end. Since the chip mounted on the insulating substrate is misaligned both in the in-plane direction and in the height direction, accurate patterning is difficult. In addition, since a high electric field sealing material has a film thickness as thick as typically 80 ⁇ m, it is also difficult to apply a general photolithography process applied to a film of up to about 10 ⁇ m at most.
- the taper shape needs to overlap the electrode 31 so as to cover the electrode end 56 having high electric field strength, but if the overlap length 59 is too long, the area necessary for wire bonding is insufficient. Therefore, the application condition of the high electric field sealing material is set so as to be within this range on the basis of 1 mm at most.
- the application conditions of the high electric field sealant are: dispenser nozzle diameter, discharge pressure, gap length (distance between the nozzle and application target), application speed (in-plane movement speed of the nozzle), and high electric field seal resistance as a coating material.
- the temperature of the material as a parameter, it can be adjusted to a range where a desired coating film thickness and coating line width can be obtained.
- the high-voltage product of the present embodiment having a withstand voltage of 3.3 kV or higher has a strong internal electric field, and the necessary high-voltage electric field sealing material is thicker than a general coating material. Depending on the case, the desired film thickness may be insufficient.
- the thickness can be increased by a method of applying the high electric field sealing material a plurality of times. Specifically, after coating by the above-described method, temporary curing in the atmosphere is performed under a heat treatment condition lower than usual at 60 ° C., and then the second coating may be performed. This step may be repeated when applying three or more times. Thereby, although the man-hour increases, it becomes possible to apply a thick film that cannot be reached by a single process.
- the high electric field sealing material 34 has a substantially vertical cross-sectional shape at the outer periphery of the chip, and the film thickness is maintained at the maximum level up to the outer periphery of the chip. This is important in designing the termination region 32.
- the narrow termination region that can improve the area efficiency has a high electric field strength to the vicinity of the outer peripheral edge of the chip. Therefore, in the conventional structure as shown in FIG. In the sealing material such as silicone gel, the limit of the dielectric breakdown electric field strength allowed by the material is exceeded. In order to realize a narrow termination region that can make use of the excellent physical properties of wide band gap semiconductors such as SiC, it is necessary to increase the thickness of the high electric field sealing material in the shape shown in FIG. It is necessary to keep.
- FIG. 17 shows a cross section at the stage where wire bonding is performed on the electrode of the chip bonded to the insulating substrate 22.
- the cross-sectional shape of the high electric field sealing material is a case where a part of the upper part becomes a concave shape 60 as shown in FIG. 18 or a case where a convex shape is shown as shown by 61 in FIG.
- the concave shape or convex shape in FIG. 18 or FIG. 19 is mainly determined by the relationship between the strength of the thermosetting condition of the high electric field sealing material and the dicing conditions (blade rotation speed and moving speed). It may be optimized in consideration of other factors such as adhesion between the electric field sealing material and the chip.
- the chip formed with the high electric field sealing material may cause a problem depending on the subsequent bonding method to the insulating substrate.
- high-temperature lead solder is used for bonding, so the solder is reflowed by heat treatment at a maximum of 355 ° C in a hydrogen reduction furnace, but the side of the carbon jig that fixes the chip in an appropriate position on the insulating substrate and the chip end
- the high electric field sealing material of the part adheres. This is shown in FIGS. 20a and 20b.
- 20a shows a state before the high electric field sealing material is fixed to the carbon jig
- FIG. 20b shows a state where the high electric field sealing material is fixed to the carbon jig.
- Adhesion occurs at the contact portion 62 of the high electric field sealing material between the carbon jig and the chip end face.
- the cross section of the outer peripheral edge of the chip can be solved by using the structure shown in FIG.
- the outer peripheral end face is recessed from the end of the chip by a small amount of 150 ⁇ m or less, preferably 30 ⁇ m, which is 1/3 or less of the width of the termination region, which is the electric field relaxation region, to the extent that the original purpose of relaxing the high electric field is not affected.
- two kinds of dicers having different blade widths are used for chip dicing, and first, dicing is performed with a wide blade (100 ⁇ m) until reaching the wafer surface, and then a narrow blade. There is a method of cutting the center to the end with (50 ⁇ m).
- the high electric field sealing material is lightly etched using a solvent such as NMP (N-methyl-2-pyrrolidone), or ashing with oxygen plasma or the like is performed, so that the high electric field sealing is achieved.
- a desired shape can be formed by isotropic recessing of the surface of the material. In any method, the problem of sticking can be avoided by forming a gap that avoids contact between the tip end and the inner wall of the carbon jig.
- solderless bonding that does not use solder and a high-temperature heat treatment furnace for bonding the chip and the insulating substrate, it is not necessary to form the recess.
- solderless bonding requires pressurization of the chip and the insulating substrate both in the bonding method using sintered silver and in the method of cleaning the bonding surface with an ion beam or the like and bonding in a high vacuum.
- the high electric field sealing material can be an obstacle to pressurization from the upper surface.
- the pressurizing jig may be provided with the unevenness indicated by 63 in FIG. 22 so as not to contact the formation portion of the high electric field sealing material.
- the high electric field sealant one or a plurality of configurations are used from among polyamideimide resin, polyetheramideimide resin, and polyetheramide resin, and here, a combination of polyetheramide resin and polyimide resin is adopted.
- the dielectric breakdown electric field strength of the high electric field sealing material is 230 kV / mm, which is more than 10 times that of silicone gel.
- the viscosity of the resin was adjusted to a range in which the resin was paste-like in order to apply it to a desired film thickness.
- a SiC-SBD having a breakdown voltage of 3.3 kV is used.
- the structure on the termination region of the chip has a SiO 2 film 65 on the SiC p-type impurity region 64, and a polyimide film 66 as a protective film on it is 4 to 8 ⁇ m. It is formed with the thickness.
- a high electric field sealing material 34 is formed in a stacked manner thereon. In the case cross-sectional view shown in FIG. 24, in the silicone gel sealing the remaining space 67 in the case, the electric field from the SiC-SBD chip does not exceed the breakdown electric field strength (14 kV / mm) of the silicone gel.
- the film thickness of the high electric field sealing material 34 on the termination region is required to be at least 50 ⁇ m or more, preferably 80 ⁇ m or more between the points AB in FIG. 23 covering the main region.
- the thickness is preferably 500 ⁇ m or less.
- a high voltage product with a withstand voltage of 3.3 kV is targeted.
- the film thickness of the high electric field sealing material depends on the design of the termination region. The lower limit can be relaxed and at least 20 ⁇ m or more.
- the relative dielectric constant of the laminated polyimide film 66 and the high electric field sealing material 34 is about 2.9 for the protective film polyimide and about 3.2 for the main component polyetheramide of the high electric field sealing material.
- the relative dielectric constant of the underlying inorganic material layer SiO 2 film 65 is smaller than 3.8 to 4.1 and larger than the relative dielectric constant of the silicone gel 36 serving as the upper sealing material is approximately 2.7.
- a structure and manufacturing method of a full SiC module having a breakdown voltage of 3.3 kV, a current capacity of 1200 A, a SiC-MOS as a switching element group, and a SiC-SBD as a diode element group are shown. .
- the gate electrode pad 70 is different from the SiC-SBD.
- the gate electrode pad 70 is arranged at the center in consideration of equalization of the gate wiring.
- the gate electrode pad 71 may be disposed closer to the electrode end as the layout shown in FIG.
- the present invention can also be applied to a configuration of a full SiC module made of only SiC-MOS using a built-in diode of SiC-MOS with the SiC-SBD omitted.
- the essence of this invention is the structure which formed the high electric field sealing material used for the semiconductor chip using a wide band gap semiconductor with the required film thickness to the chip
- SiC hybrid module which is a combination of the above-mentioned Si-IGBT and SiC-SBD, or a full SiC module in which SiC-MOS is used alone or in combination with SiC-SBD.
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Abstract
Description
12 SiC-SBD
13 ワイヤ(ボンディング)
21 電極主端子
22 絶縁基板
25 ケース
26 カバー
27 共通エミッタ(ソース)回路パタン
28 共通エミッタ(ソース)主端子コンタクト
30 耐高電界封止材の形成領域
31 電極
32 ターミネーション領域
33 チップ外周部
34 耐高電界封止材
35 ハンダ
36 シリコーンゲル
37 回路配線金属
38 耐高電界封止材の端部
39 ターミネーション領域の幅
40 耐高電界封止材の塗布工程
41 チップを絶縁基板に接合する工程
42 ディスペンサーの塗布ノズル
43 ワイヤボンディング工程
44 ダイシング工程
45 スクライブライン
46 ウエハ
47 塗布時の横方向と縦方向の交差箇所
48 ターミネーション領域のコーナ部分
49 ウエハ特性検査工程
50 ダイサーのブレード
51 絶縁基板のベースプレートへの接合工程
52 ケース接着やゲル封入等のモジュールアセンブリ工程一式
53 チップ検査工程
54 テーパー形状
55 ウエハ状態での耐高電界封止材の塗布形状
56 電極端境界
57 ワイヤボンディングの接合部
58 ワイヤボンディング接合部のヒール
59 耐高電界封止材の電極へのオーバーラップ長
60 耐高電界封止材の凹形状
61 耐高電界封止材の凸形状
62 カーボン治具とチップ端面の耐高電界封止材の接触部
63 凹凸つきの加圧治具
64 SiCのp型不純物領域
65 SiO2膜
66 ポリイミド膜
67 ケース内の残りの空間
68 ベースプレート
69 チャネルストッパ
70 中央配置のゲート電極パッド
71 電極端部寄り配置のゲート電極パッド
Claims (15)
- ワイドギャップ半導体素子が形成された半導体チップを備え、
前記半導体チップのパタン面側のチップの周辺部に形成される耐高電界封止材の断面形状が、チップ外周端側の少なくとも一部が垂直またはそれに近い端面形状を有し、チップ内周端側では内側に向けて膜厚が減少する形状を有する
ことを特徴とする半導体装置。 - 請求項1において、
前記耐高電界封止材は、ポリアミドイミド樹脂、ポリエーテルアミドイミド樹脂、およびポリエーテルアミド樹脂のうちの少なくとも一種を含んで構成される
ことを特徴とする半導体装置。 - 請求項1において、
前記耐高電界封止材の膜厚が、少なくとも50μm以上で、かつ500μm以下である
ことを特徴とする半導体装置。 - 請求項1において、
前記耐高電界封止材の比誘電率が、下地の無機材料層の比誘電率より小さく、かつ上層の封止材の比誘電率より大きい
ことを特徴とする半導体装置。 - 請求項1において、
チップ外周端側の少なくとも一部が垂直ないしそれに近い端面形状を有する部分が、電界緩和領域幅の最大でも1/3以下だけチップ端からリセスした構造である
ことを特徴とする半導体装置。 - 請求項1において、
前記ワイドギャップ半導体素子はシリコンカーバイドを含んで構成される
ことを特徴とする半導体装置。 - ワイドギャップ半導体素子が形成された半導体チップを備えた半導体装置の製造方法であって、
前記半導体チップのパタン面側のチップの周辺部に配置する耐高電界封止材を半導体ウエハの状態で形成する工程と、
前記半導体ウエハに対して熱処理を実施する工程と、
熱処理された前記半導体ウエハに対してダイシングを実施する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項7において、
前記熱処理の温度が、200℃から400℃の範囲にある
ことを特徴とする半導体装置の製造方法。 - 請求項7において、
前記耐高電界封止材の形成工程は、ウエハのスクライブラインに沿って前記耐高電界封止材を少なくとも2つの方向から交差させて塗布する工程を含む
ことを特徴とする半導体装置の製造方法。 - ワイドギャップ半導体素子が形成された半導体チップを搭載した半導体モジュールであって、
前記半導体チップは、前記半導体チップのパタン面側のチップの周辺部に形成される耐高電界封止材の断面形状が、チップ外周端側の少なくとも一部が垂直またはそれに近い端面形状を有し、チップ内周端側では内側に向けて膜厚が減少する形状を有する
ことを特徴とする半導体モジュール。 - 請求項10において、
前記耐高電界封止材は、ポリアミドイミド樹脂、ポリエーテルアミドイミド樹脂、およびポリエーテルアミド樹脂のうちの少なくとも一種を含んで構成される
ことを特徴とする半導体モジュール。 - 請求項10において、
前記耐高電界封止材の膜厚が、少なくとも50μm以上で、かつ500μm以下である
ことを特徴とする半導体モジュール。 - 請求項10において、
前記耐高電界封止材の比誘電率が、下地の無機材料層の比誘電率より小さく、かつ上層の封止材の比誘電率より大きい
ことを特徴とする半導体モジュール。 - 請求項10において、
チップ外周端側の少なくとも一部が垂直ないしそれに近い端面形状を有する部分が、電界緩和領域幅の最大でも1/3以下だけチップ端からリセスした構造である
ことを特徴とする半導体モジュール。 - 請求項10において、
前記ワイドギャップ半導体素子はシリコンカーバイドを含んで構成される
ことを特徴とする半導体モジュール。
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JP2016565789A JP6416934B2 (ja) | 2014-12-26 | 2014-12-26 | 半導体装置およびその製造方法、並びに半導体モジュール |
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KR20180037770A (ko) * | 2016-10-05 | 2018-04-13 | 한국전기연구원 | 아민계 폴리머를 포함한 실리콘 카바이드 다이오드 및 제조방법 |
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