CN113271712A - 布线板和电子装置模块 - Google Patents
布线板和电子装置模块 Download PDFInfo
- Publication number
- CN113271712A CN113271712A CN202110125148.8A CN202110125148A CN113271712A CN 113271712 A CN113271712 A CN 113271712A CN 202110125148 A CN202110125148 A CN 202110125148A CN 113271712 A CN113271712 A CN 113271712A
- Authority
- CN
- China
- Prior art keywords
- disposed
- electronic device
- wiring board
- pad
- metal plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0225—Out-coupling of light
- H01S5/02253—Out-coupling of light using lenses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0233—Mounting configuration of laser chips
- H01S5/0234—Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/024—Arrangements for thermal management
- H01S5/02469—Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
- H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12043—Photo diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
一种布线板,包括:金属板,具有彼此相对的第一表面和第二表面,并具有贯穿第一表面和第二表面的至少一个通孔;至少一个导电穿通件,分别布置在至少一个通孔中并与金属板间隔开;绝缘结构,包括布置在至少一个通孔和至少一个导电穿通件之间的至少一个贯穿绝缘部,及分别在第一表面和第二表面上从至少一个贯穿绝缘部延伸并布置在围绕至少一个导电穿通件的第一区域中的第一绝缘层和第二绝缘层;至少一个第一上焊盘,布置在第一绝缘层上,并电连接至至少一个导电穿通件;至少一个第一下焊盘,布置在第二绝缘层上,并电连接至至少一个导电穿通件;第二上焊盘,布置在金属板的第一表面上;及第二下焊盘,布置在金属板的第二表面上。
Description
相关申请的交叉引用
本申请基于2020年1月30日在韩国知识产权局提交的韩国专利申请No.10-2020-0010939并且要求其优先权,该申请的全部公开以引用方式全部并入本文中。
技术领域
本公开涉及一种布线板和具有该布线板的电子装置模块。
背景技术
近年来,随着与电子装置相关的技术的发展,半导体装置的高性能和高输出已经得到发展。随着半导体装置获得高性能和高功率水平,可能发生与半导体装置中产生的热有关的问题。已经进行了各种研究来解决半导体装置中产生的热的问题。
发明内容
示例性实施例提供了一种具有改进的散热性能的布线板。
示例实施例提供了一种包含具有改善的散热性能的布线板的电子装置模块。
根据示例实施例,一种布线板包括:金属板,其具有彼此相对的第一表面和第二表面,并且具有贯穿第一表面和第二表面的至少一个通孔;至少一个导电穿通件,其分别布置在至少一个通孔中并与金属板间隔开;绝缘结构,其包括布置在至少一个通孔和至少一个导电穿通件之间的至少一个贯穿绝缘部、以及分别在第一表面和第二表面上从至少一个贯穿绝缘部延伸并布置在围绕至少一个导电穿通件的第一区域中的第一绝缘层和第二绝缘层;至少一个第一上焊盘,其布置在第一绝缘层上,并且电连接至至少一个导电穿通件;至少一个第一下焊盘,其布置在第二绝缘层上,并且电连接至至少一个导电穿通件;第二上焊盘,其布置在金属板的第一表面上;以及第二下焊盘,其布置在金属板的第二表面上,并通过金属板电连接至第一上焊盘。
根据示例实施例,一种电子装置模块包括:金属板,其具有彼此相对的第一表面和第二表面,并且具有贯穿第一表面和第二表面的多个通孔;多个导电穿通件,其分别布置在多个通孔中,并且与金属板间隔开;绝缘结构,其包括分别布置在多个通孔和多个导电穿通件之间的多个贯穿绝缘部、以及分别在第一表面和第二表面上从多个贯穿绝缘部延伸并且布置在围绕多个导电穿通件的区域中的第一绝缘层和第二绝缘层;多个第一上焊盘,其布置在第一绝缘层上,并且分别连接至多个导电穿通件;多个第一下焊盘,其布置在第二绝缘层上,并且分别连接至多个导电穿通件;第二上焊盘,其布置在金属板的第一表面上;第二下焊盘,其布置在金属板的第二表面上,并通过金属板电连接至多个第一上焊盘;第一电子装置,其安装在第二上焊盘上并且分别电连接至多个第一上焊盘和第二上焊盘;以及第二电子装置,其安装在多个第一上焊盘上,并且分别电连接至多个第一上焊盘和第二上焊盘。
根据示例实施例,一种电子装置模块包括:上述布线板;以及第一电子装置,其安装在第二上焊盘上并分别电连接至多个第一上焊盘和第二上焊盘。
根据示例实施例,一种电子装置包括:下封装件,其具有半导体芯片;以及上封装件,其包括布置在下封装件上的布线板以及布置在布线板上的第一电子装置和第二电子装置,其中,下封装件包括:封装基板,其具有布线电路,并且布置有安装在其上以连接至布线电路的半导体芯片;框架,其具有容纳半导体芯片的容纳部分;以及多个垂直连接导体,其贯穿框架的上表面和下表面并且电连接至布线电路,其中,上封装件的布线板包括:金属板,其具有面对框架的上表面的第一表面和与第一表面相对的第二表面,并且具有贯穿第一表面和第二表面的多个通孔;多个导电穿通件,其分别布置在多个通孔中,并且与金属板间隔开;绝缘结构,其包括分别布置在多个通孔和多个导电穿通件之间的多个贯穿绝缘部,以及分别在第一表面和第二表面上从多个贯穿绝缘部延伸并且设置在围绕多个导电穿通件的第一区域中的第一绝缘层和第二绝缘层;多个第一上焊盘和多个第一下焊盘,其分别布置在第一绝缘层和第二绝缘层上,并分别电连接至多个导电穿通件;以及第二上焊盘和第二下焊盘,其分别布置在金属板的第一表面和第二表面上,并且通过金属板彼此电连接,并且其中,第一电子装置和第二电子装置分别安装在多个第一上焊盘中的至少一个和第二上焊盘上,并且分别电连接至第一上焊盘和第二上焊盘,并且多个第一下焊盘和第二下焊盘分别电连接至垂直连接导体。
根据示例实施例,一种布线板包括:金属板,其具有彼此相对的第一表面和第二表面,第一表面和第二表面中的每一个被划分为第一区域和第二区域,其中,第一区域具有比第二区域低的水平高度,并且金属板包括贯穿第一表面和第二表面的第一区域的至少一个通孔;绝缘结构,其包括沿至少一个通孔的侧壁布置的至少一个贯穿绝缘部、从至少一个贯穿绝缘部延伸到第一表面的第一区域的第一绝缘层以及从至少一个贯穿绝缘部延伸到第二表面的第一区域的第二绝缘层;至少一个导电穿通件,其贯穿绝缘结构以位于至少一个通孔中,并且通过至少一个贯穿绝缘部与金属板电绝缘;至少一个第一上焊盘和至少一个第一下焊盘,其分别布置在第一绝缘层和第二绝缘层上,并且通过至少一个导电穿通件彼此电连接;以及第二上焊盘和第二下焊盘,其分别布置在第一表面的第二区域和第二表面的第二区域上,并且通过金属板彼此电连接。
附图说明
从以下结合附图的详细描述中,将更清楚地理解本公开的上述和其它方面、特征和优点,在附图中:
图1A是根据示例实施例的电子装置模块的平面图;
图1B是沿图1A中的线I-I’截取的电子装置模块的侧截面图;
图2是根据示例实施例的基于金属的布线板的透视图;
图3A至图8A是用于示出根据示例实施例的制造基于金属的布线板的方法的各个处理的平面图;
图3B至图8B是用于示出根据示例实施例的制造基于金属的布线板的方法的各个处理的截面图;
图9A和图9B分别是根据示例实施例的电子装置模块的平面图和底视图;
图9C是沿图9A中的线II-II’截取的电子装置模块的侧截面图;
图10是示出根据示例实施例的PoP型电子装置模块的示意性透视图;
图11是示出图10中示出的PoP型电子装置模块的分解透视图;以及
图12是沿图10中的线III-III’截取的PoP型电子装置模块(不包括透镜和壳体)的截面图。
具体实施方式
在下文中,将参照附图详细描述各种示例性实施例。
图1A是根据示例实施例的电子装置模块的平面图,并且图1B是沿图1A中的线I-I’截取的电子装置模块的侧截面图。
参照图1A和图1B,根据示例实施例的电子装置模块200包括布线板100以及安装在布线板100上的第一电子装置210和第二电子装置220。
根据本实施例的布线板100可包括具有彼此相对的第一表面110A和第二表面110B的金属板110,以及穿透第一表面110A和第二表面110B的多个通孔H1和H2。金属板110可包括具有高热导率和高电导率的金属或合金。例如,金属板110可包括铜(Cu)、铝(Al)或合金。
布线板100包括连接布线板100的上表面和下表面(即,第一表面110A和第二表面110B)的垂直布线结构。如图1B所示,这种垂直布线结构可包括分别布置在通孔H1和通孔H2中的多个导电穿通件CV1和CV2。导电穿通件CV1和CV2可通过绝缘结构120与金属板110电绝缘。
绝缘结构120可包括多个贯穿绝缘部120c,每个贯穿绝缘部分别布置在通孔H1和通孔H2中的每个通孔的内侧壁与导电穿通件CV1和导电穿通件CV2中的每个导电穿通件之间。此外,绝缘结构120可包括第一绝缘层120a和第二绝缘层120b,第一绝缘层120a和第二绝缘层120b从每个贯穿绝缘部120c延伸并布置在导电穿通件CV1和导电穿通件CV2中的每一个的周围的区域中,例如,分别在第一表面110A上的第一区域110A1中和第二表面110B上的第一区域110B1中。
在本实施例中,导电穿通件CV1和导电穿通件CV2并排布置为与一个侧边缘相邻,并且第一绝缘层120a和第二绝缘层120b沿着边缘形成,并且可分别以单层设置在第一表面110A和第二表面110B中的每一个上。此外,位于通孔H1和通孔H2中的贯穿绝缘部120c可由与第一绝缘层120a和第二绝缘层120b相同的材料形成,以与第一绝缘层120a和第二绝缘层120b集成。例如,绝缘结构120可包括诸如环氧树脂或聚酰亚胺的绝缘树脂(例如,绝缘墨)。
如图1B所示,在本实施例中采用的金属板110中,布置有第一绝缘层120a和第二绝缘层120b的区域可具有被设置为其水平高度比其它区域低的结构。详细地,金属板110的第一表面110A和第二表面110B可分别划分为第一区域110A1和110B1以及第二区域110A2和110B2。第一区域110A1和110B1是布置有第一绝缘层120a和第二绝缘层120b的区域,并且可具有比第二区域110A2和110B2低的水平高度。可通过蚀刻金属板110的相应区域来形成第一区域110A1和110B1。
通孔H1和通孔H2可穿透第一表面110A的第一区域110A1和第二表面110B的第一区域110B1。在本实施例中,第一表面110A的第一区域110A1和第二表面110B的第一区域110B1被示出为在竖直方向上实质上重叠,但是在另一实施例中,第一区域110A1和110B1的一些区域在竖直方向上可不重叠。
形成第一绝缘层120a和第二绝缘层120b的区域可由第一区域110A1和110B1限定,并且第一绝缘层120a和第二绝缘层120b可提供在其中将要形成第一上焊盘131a和第一下焊盘141a的区域。详细地说,通孔H1和通孔H2位于第一区域110A1和110B1的竖直地重叠的区域中,并且第一区域110A1和110B1的其它区域可根据第一上焊盘131a和第一下焊盘141a的所需设计而不同地改变。
在金属板110的第一表面110A上,布置在第一区域110A1中的第一绝缘层120a与第二区域110A2的表面实质上共面。类似地,在金属板110的第二表面110B上,布置在第一区域110B1中的第二绝缘层120b可具有与第二区域110B2的表面实质上共面的表面。然而,示例实施例不限于此,并且在一些实施例中,第一绝缘层120a和第二绝缘层120b的表面可分别具有与第二区域110A2和110B2的表面不同的水平高度。
布线板100可包括第一绝缘层120a上的分别连接至导电穿通件CV1和CV2的多个第一上焊盘131a和131b,以及第二绝缘层120b上的分别连接至导电穿通件CV1和CV2的多个第一下焊盘141a和141b。在本实施例中,尽管导电穿通件CV1和CV2被示出为分别连接至一个第一上焊盘131a和一个第一下焊盘141a的形式,但是在其它实施例中,一个第一上焊盘或一个第一下焊盘也可连接至至少两个导电穿通件。
如此,与导电穿通件CV1和CV2一起,第一上焊盘131a和131b以及第一下焊盘141a和141b可提供与金属板110电分离的多个垂直布线结构。如上所述,这些垂直布线结构可通过绝缘结构120与金属板110分离。
布线板100可包括布置在第一表面110A上的第二上焊盘132和布置在第二表面110B上的第二下焊盘142。与第一上焊盘131和第一下焊盘141不同,第二上焊盘132和第二下焊盘142直接连接至金属板110,并且可通过金属板110彼此电连接,而不需要单独的导电穿通件。
在本实施例中,第二上焊盘132的一部分可布置在第一绝缘层120a上。类似地,第二下焊盘142的一部分可布置在第二绝缘层120b上。
第一上焊盘131和第二上焊盘132以及第一下焊盘141和第二下焊盘142可在电镀工艺中被形成。例如,第一上焊盘131和第二上焊盘132以及第一下焊盘141和第二下焊盘422可分别包括种子层(例如,Ni、Cr、Ti或它们的组合的层)和形成在种子层上的电镀层(例如,Cu层)。类似地,导电穿通件CV1和CV2也可在电镀工艺中被形成。可通过相同的电镀工艺形成导电穿通件CV1和CV2,同时形成第一上焊盘131和第二上焊盘132以及第一下焊盘141和第二下焊盘422(见图7A和7B)。在本实施例中,导电穿通件CV1和CV2被示出为通过电镀形成的填充类型,但是也可具有以下形式:其中,具有预定厚度的电镀层沿贯穿绝缘部120c的内侧壁形成,并且其内部具有空的空间或者该空的空间填充有另一绝缘材料。
如图1A所示,第一上焊盘131的至少一个边缘和第二上焊盘132的至少一个边缘可布置在第一表面110A的一个边缘附近。类似地,第一下焊盘141的至少一个边缘和第二下焊盘142的至少一个边缘可布置在第二表面110B的一个边缘附近。焊盘的这种布置可被理解为在布线板的制造过程中在多个相邻布线板上形成用于焊盘的至少一部分的电镀层、并且在切割成单独的布线板的过程中将电镀层分离的结果。
在本实施例中,第一电子装置210和第二电子装置220可安装在第一上焊盘131和第二上焊盘132上。在本实施例中,第一电子装置210布置在第二上焊盘132上,并且第二电子装置220可布置在第一上焊盘131上。
第一电子装置210和第二电子装置220可通过表面安装方法或布线方法电连接至第一上焊盘131和第二上焊盘132中的至少一个或另一电子装置220或210。在本实施例中,第一电子装置210和第二电子装置220可以是具有如下结构的装置:该结构具有其上布置有第一电极的上表面和其上布置有第二电极的下表面。在第一电子装置210和第二电子装置220的情况下,第二电极可通过使用表面安装方法分别连接至第二上焊盘132和第一上焊盘131。例如,如图1B所示,第一电子装置210的第二电极通过导电接合层235电连接、机械地连接并且热连接至第二上焊盘132。例如,导电接合层235可是包含诸如Ag或Cu的金属的糊料。类似于第一电子装置210,第二电子装置220可使用导电接合层(未示出)连接至第一上焊盘131a。
第一电子装置210可在其上设置有多个第一电极,第一电子装置210的第一电极中的一个第一电极可通过导线W连接至布置在一个第一上焊盘131a上的第二电子装置220的第一电极,第一电子装置210的第一电极中的另一个第一电极可通过另一导线W连接至另一第一上焊盘131b。
第一电子装置210可以是具有比第二电子装置220的发热量大的发热量的主热源。从第一电子装置210产生的热可通过直接接触第二上焊盘132的金属板110有效地消散。
如图2所示,根据本实施例的布线板100的所有侧面可由金属板的侧表面110S提供。图2是根据示例实施例的布线板的透视图。
参照图2,布线板100具有四个侧面,金属板110的四个侧表面110S可连续地暴露于布线板100的四个侧面。因此,第一电子装置210产生的热通过第二上焊盘132传递至金属板110,并可通过侧表面110S有效地释放(见箭头“H”)。金属板110的连续暴露的部分的厚度T1可以是金属板110的总厚度T0的至少50%。
在一些实施例中,金属板110的总厚度T0可为800μm或更大,并且可通过将金属板的暴露的部分的厚度T1设计为大于或等于厚度T0的70%并且小于厚度T0的100%来实现有效散热功能。
例如,第一电子装置210可以是存储器芯片、逻辑芯片或高功率光源装置。例如,存储器芯片可以是易失性存储器芯片(诸如动态随机存取存储器(DRAM)(例如,高带宽存储器(HBM))或静态随机存取存储器(SRAM))或者非易失性存储器芯片(诸如相变随机存取存储器(PRAM)、磁阻随机存取存储器(MRAM)、铁电随机存取存储器(FeRAM)或电阻随机存取存储器(RRAM))。此外,逻辑芯片可以是例如微处理器、模拟装置或数字信号处理器。此外,高功率光源装置可以是高功率发光二极管或高功率激光二极管。第二电子装置220可是具有相对小热量的设备。例如,第二电子装置220可包括诸如光电二极管或电容器的无源装置。在特定实施例中,第一电子装置210是高功率发光二极管或高功率激光二极管,并且第二电子装置220可以是光电二极管。
图3A至图8A是用于示出制造图2所示的布线板100的方法的各个处理的平面图,图3B至图8B是用于示出制造图2所示的布线板100的方法的各个处理的截面图。
参照图3A和图3B,在金属板110的第一表面110A和第二表面110B上形成具有比第二区域110A2和110B2低的水平高度的第一区域110A1和110B1。
金属板110可包括具有高导热率和优异导电率的金属或合金。例如,金属板110可由铜(Cu)、铝(Al)或它们的合金形成。例如,铜不仅具有比陶瓷优异的导电率,而且具有比陶瓷优异的导热率(例如,约300W/mK),并且因此可有利地被使用。
可通过针对金属板110的其上将要布置第一绝缘层120a和第二绝缘层120b(见图5A和图5B)的区域的选择性蚀刻处理来执行该处理。第一绝缘层120a和第二绝缘层120b的厚度可由第一表面110A和第二表面110B上蚀刻的深度来限定。从散热的角度来看,厚度为T0的第二区域110A2具有比蚀刻后厚度为T1的第二区域110A1相对大的面积是有利的。此外,金属板110的蚀刻部分的厚度T1可以是金属板110的总厚度T0的50%或更多,详细地,70%或更多。在一些实施例中,金属板110的总厚度T0可以是800μm或更大,并且金属板110的暴露的部分的厚度T1可以是600μm或更大。在本实施例中,仅一个第一区域110A1和110B1设置在第一表面110A和第二表面110B上,但是多个分离的第一区域和第二区域可设置在第一表面110A和第二表面110B上(见图9A至9C)。
接下来,参照图4A与图4B,形成贯穿第一表面110A的第一区域110A1与第二表面110B的第一区域110B1的多个通孔H1与H2。
可使用激光钻孔或机械钻孔形成通孔H1和H2。通孔H1和H2可设置为用于连接第一表面110A和第二表面110B的垂直连接结构。在本实施例中,形成两个通孔,但是在另一实施例中,可形成一个通孔或者三个或更多个通孔。
接下来,参照图5A与图5B,在第一区域110A1与110B1上形成绝缘结构120,以填充通孔H1与H2。
可使用诸如环氧树脂或聚酰亚胺的绝缘树脂(例如,绝缘油墨)来形成绝缘结构120,但是用于形成绝缘结构120的材料不限于此。可将绝缘结构120形成为平坦的,同时填充通孔H1和H2。在形成绝缘材料层以覆盖第一表面110A和第二表面110B之后,对绝缘材料层执行抛光或回蚀工艺以暴露第二区域110A2和110B2。因此,可形成分别由第一区域110A1和110B1限定的第一绝缘层120a和第二绝缘层120b。
如上所述,绝缘结构120可包括填充通孔H1和H2内部的多个贯穿绝缘部120c,以及从贯穿绝缘部120c延伸并分别布置在第一表面110A的第一区域110A1和第二表面110B的第一区域110B1上的第一绝缘层120a和第二绝缘层120b。
随后,参照图6A与图6B,在绝缘结构120的贯穿绝缘部120c中形成多个接触孔H1’与H2’。
可使用激光钻孔或机械钻孔形成接触孔H1’和H2’。接触孔H1’和H2’具有比通孔H1和H2小的直径,并且可形成在贯穿绝缘部120c中。详细地,接触孔H1’和H2’可以以使得通孔H1和H2的内侧壁(例如,金属板110的表面)不被暴露的方式被贯穿绝缘部120c围绕。
接下来,参照图7A和图7B,可通过使用导电材料填充接触孔H1’和H2’来形成多个导电穿通件CV1和CV2。
例如,可通过使用诸如铜或银糊料的导电材料填充接触孔H1’和H2’来形成导电穿通件CV1和CV2。导电穿通件CV1和CV2可设置为连接第一表面110A的第一区域110A1和第二表面110B的110B1的垂直连接结构。在一些实施例中,导电穿通件CV1和CV2可包括与金属板110不同的材料。
参照图8A和图8B,可分别在金属板110的第一表面110A和第二表面110B上形成第一上焊盘131和第二上焊盘132以及第一下焊盘141和第二下焊盘142。
例如,可使用电镀工艺形成第一上焊盘131和第二上焊盘132以及第一下焊盘141和第二下焊盘142。在在第一表面110A和第二表面110B上形成种子层(例如,由Ni、Cr、Ti或它们的组合形成)之后,在种子层(未示出)上形成暴露出焊盘形成区域的光刻胶,并且使用电镀工艺形成电镀层(例如,由Cu形成),从而形成所需的第一上焊盘131和第二上焊盘132以及第一下焊盘141和第二下焊盘142。可通过在电镀工艺之后将暴露的种子层与光刻胶一起除去来制造图8A和图8B中所示的布线板。
虽然本实施例示出了通过与形成第一上焊盘131和第二上焊盘132以及第一下焊盘141和第二下焊盘142不同的工艺来形成导电穿通件CV1和CV2,但是可使用相同的电镀形成导电穿通件CV1和CV2。例如,种子层也形成在接触孔H1’和H2’的内侧壁上,以在接触孔H1’和H2’中形成所需的电镀层,从而形成导电穿通件CV1和CV2以及第一上焊盘131和第二上焊盘132以及第一下焊盘141和第二下焊盘142。在这种情况下,与图8B所示的填充类型的导电穿通件CV1和CV2不同,根据由电镀而得的电镀层的厚度,导电穿通件CV1和CV2中具有空的空间,或者可使用另一绝缘材料填充空的空间。
图9A和图9B是根据示例实施例的电子装置模块的平面图和底视图,图9C是沿图9A(或图9B)中的线II-II’截取的电子装置模块的侧截面图。
参照图9A至图9C,根据示例实施例的电子装置模块200A可具有与图1A和图1B中示出的示例实施例的结构类似的结构,除了具有相对低的水平高度的第一区域110A1和110B1分别被设置为第一表面110A和第二表面110B上的两个分离的区域、设置了六个垂直连接结构(金属板110和五个接触导电穿通件CV1至CV5)、以及设置了三个电子装置250、260和270之外。因此,除非另外特别说明,否则图1A和图1B中所示的实施例的描述可与本实施例的描述相结合。
根据本实施例的电子装置模块200A具有与前述实施例中采用的布线板100不同的布线板100A。布线板100A具有在第一表面110A和第二表面110B中的每一个上的两个第一区域110A1和110B1。详细地,第一区域110A1和110B1分别布置在金属板110的第一表面110A和第二表面110B的相对边缘部上。
第一绝缘结构和第二绝缘结构可分别布置在两侧的第一区域110A1和110B1中。在本实施例中,三个通孔H1、H2和H3布置在右侧的第一区域110A1和110B1中,两个通孔H4和H5布置在左侧的第一区域110A1和110B1中。
第一绝缘结构121可包括分别布置在第一通孔至第三通孔H1、H2和H3的内侧壁与第一导电穿通件至第三导电穿通件CV1、CV2和CV3之间的三个第一贯穿绝缘部121c,以及从第一贯穿绝缘部121c延伸并布置在第一导电穿通件至第三导电穿通件CV1、CV2和CV3所在的第一区域110A1和110B1上的第一绝缘层121a和第二绝缘层121b。类似地,第二绝缘结构122可包括分别设置在第四通孔H4和第五通孔H5的内侧壁以及第四导电穿通件CV4和第五导电穿通件CV5之间的两个第二贯穿绝缘部122c(未示出),以及从第二贯穿绝缘部122c延伸并布置在第四导电穿通件CV4和第五导电穿通件CV5所在的第一区域110A1和110B1上的第一绝缘层122a和第二绝缘层122b。
根据本实施例的电子装置模块200A可以是与3D感测模块一起应用于诸如移动通信终端的电子装置中的光源模块。
第一电子装置250可以是作为主热源的高功率发光二极管或高功率激光二极管。例如,第一电子装置250可包括高功率(例如,5W或更高)垂直腔表面发射激光器(VCSEL)。例如,第二电子装置260和第三电子装置270可分别是光电二极管芯片和齐纳(zener)二极管芯片。
第一电子装置250可布置在第二上焊盘132上。第二上焊盘132可与金属板110和第二下焊盘142一起提供另一垂直连接结构。此外,从第一电子装置250产生的热可通过直接接触第二上焊盘132的金属板110被有效地消散。
通过包括具有相互连接的上表面和下表面的垂直连接结构,图9A至图9C中所示的电子装置模块200A可与其它功能封装件(诸如驱动装置)一起实现为堆叠形式的PoP封装。本实施例在图10至图12中被示出。
图10是示出根据示例实施例的PoP型电子装置模块的示意性透视图,并且图11是示出图10中示出的PoP型电子装置模块的分解透视图。
参照图10和图11,根据示例实施例的PoP型电子装置模块500包括具有半导体芯片350的下封装件300和布置在下封装件300上的上封装件400。
上封装件400可包括图9A中所示的电子装置模块200A。例如,上封装件400可包括布线板100A以及布置在布线板100A上的第一电子装置至第三电子装置250、260和270。上封装件400还可包括布置在布线板100A上并具有向上开口的窗口Wd的透镜壳体410以及布置在窗口Wd中的透镜单元450。
下封装件300可包括安装有半导体芯片350的封装基板310以及布置在封装基板310上并具有容纳半导体芯片350的容纳部321H的框架320。半导体芯片350可以是例如驱动集成电路(IC)芯片。
参照图12,将详细描述上封装件400的电子装置模块200A与下封装件300的电连接结构。图12是沿图11中示出的线III-III’截取的PoP型电子装置模块(不包括透镜和壳体)的截面图,并且为了便于描述可将其理解为没有透镜单元450和透镜壳体410的截面图。
参照图12,封装基板310可包括基板主体311和形成在基板主体311中的布线电路315。框架320可包括连接至布线电路315的垂直连接导体322、323和325。
详细地,封装基板310可包括布置在基板主体311的上表面上并连接至布线电路315的接合焊盘317。可使用倒装芯片方法将半导体芯片350接合到封装基板310。例如,可使用导电凸块SB将半导体芯片350的接触焊盘350P连接至接合焊盘317。
此外,封装基板310可包括布置在基板主体311的上表面311A和下表面311B上并连接至布线电路315的上焊盘312和下焊盘313。框架320的垂直连接导体包括分别布置在框架主体321的上表面321A和下表面321B上的上图案322和下图案323,以及贯穿框架主体321以连接上图案322和下图案323的贯通孔325。
框架320的下部图案323分别连接至封装基板310的上焊盘312,并且可通过布线电路315电连接至半导体芯片350。
此外,框架320的上部图案322可通过贯通孔325连接至下部图案323,并且可分别电连接至布线板100A的第一下焊盘141a、141b、141c、141d和141e以及第二下焊盘142。布线板100A的第一下焊盘141a、141b、141c、141d和141e以及第二下焊盘142可布置在两个边缘部上与框架320的上图案322对应的位置,如图9B所示。
这样,布线板100A可通过框架320的垂直连接导体322、323和325电连接至封装基板310上的半导体芯片350,并且通过这种电连接路径,第一电子装置至第三电子装置250、260和270可向半导体芯片350发送电信号并从半导体芯片350接收电信号。
例如,当第一电子装置至第三电子装置250、260和270是诸如构成光源模块的VCSEL芯片或光电二极管芯片的光学元件时,这些光学元件由作为驱动IC芯片的半导体芯片350驱动。
在本实施例中,从作为主热源(例如VCSEL)的第一电子装置250产生的热可通过直接接触第二上焊盘132的金属板110有效地消散。
参照图11,布线板100A具有四个侧表面,并且可以以金属板110的四个侧表面110S连续地暴露于布线板100A的四个侧表面的方式被构造。因此,从第一电子装置250产生的热通过第二上焊盘132被传递到金属板110,并且可通过侧表面110S被有效地排放(参见“H”箭头)。
另一方面,在PoP型电子装置模块500中,即使在使用作为高热源的第一电子装置250的情况下,通过采用布线板100A,也可省略单独的散热器。此外,通过使用其中布线板100A的上表面和下表面导通的垂直连接结构,可将具有PoP结构的模块与驱动IC芯片封装件(例如,下封装件300)一起实现。如上所述,PoP型电子装置模块500可提高散热性能并且减小产品尺寸。
通过将上封装件400和下封装件300实现为在平面图中具有相同的尺寸,可实现紧凑的PoP结构。如图10和图11所示,下封装件300的侧表面可分别与上封装件400的侧表面实质上共面。
另外,在使用诸如VECSEL的高功率激光二极管(例如,第一电子装置250)的情况下,如果透镜单元450损坏,则人眼可能被高功率光损坏。因此,连接至透镜单元450的透镜损坏感测电极415可布置在透镜壳体410中。预先设置在透镜单元450中的透明电极线(未示出)连接至透镜损坏感测电极415,透镜损坏感测电极415电连接至位于透镜壳体410下方的多个第一上焊盘131d和131e中的至少一个,并且因此可通过布线板100A、框架320和封装基板310的电路连接而连接至作为驱动IC芯片的半导体芯片350。因此,当检测到透明电极线的损坏时,信息被传送到半导体芯片350,并且可停止对高功率激光二极管(例如,第一电子装置250)的驱动。
在本实施例中,半导体芯片350的上表面可以是非有源表面。如图12所示,热界面材料层330布置在半导体芯片350的上表面和第二下焊盘142之间,从而通过金属板110有效地释放半导体芯片350中产生的热。
如上所述,根据示例实施例,提供了一种具有增强的散热的布线板。布线板可用作高热源电子装置(诸如高功率光源(例如VCSEL))的模块的布线板。布线板可有利地用作需要高散热的层叠封装型(PoP)电子模块的上布线板。
尽管上面已经说明和描述了示例实施例,但是对于本领域技术人员来说将显而易见的是,在不脱离由所附权利要求限定的本公开的范围的情况下,可进行修改和变化。
Claims (20)
1.一种布线板,包括:
金属板,其具有彼此相对的第一表面和第二表面,并且具有贯穿所述第一表面和所述第二表面的至少一个通孔;
至少一个导电穿通件,其分别布置在所述至少一个通孔中并与所述金属板间隔开;
绝缘结构,其包括布置在所述至少一个通孔和所述至少一个导电穿通件之间的至少一个贯穿绝缘部、以及分别在所述第一表面和所述第二表面上的第一绝缘层和第二绝缘层,所述第一绝缘层和所述第二绝缘层从所述至少一个贯穿绝缘部延伸并且布置在围绕所述至少一个导电穿通件的第一区域中;
至少一个第一上焊盘,其布置在所述第一绝缘层上,并且电连接至所述至少一个导电穿通件;
至少一个第一下焊盘,其布置在所述第二绝缘层上,并且电连接至所述至少一个导电穿通件;
第二上焊盘,其布置在所述金属板的所述第一表面上;以及
第二下焊盘,其布置在所述金属板的所述第二表面上,并通过所述金属板电连接至所述至少一个第一上焊盘。
2.如权利要求1所述的布线板,还包括形成在所述第二上焊盘上以连接至电子装置的下表面的导电接合层。
3.如权利要求1所述的布线板,其中,所述布线板的所有侧表面由所述金属板的侧表面提供。
4.如权利要求1所述的布线板,其中,所述至少一个通孔包括多个通孔,并且所述至少一个导电穿通件包括分别布置在所述多个通孔中的多个导电穿通件。
5.如权利要求5所述的布线板,其中,所述至少一个第一上焊盘和所述至少一个第一下焊盘包括分别通过所述导电通孔彼此连接的多个第一上焊盘和多个第一下焊盘。
6.如权利要求1所述的布线板,其中,所述第一绝缘层具有与所述第一表面的未形成所述绝缘结构的第二区域的表面实质上共面的上表面。
7.如权利要求1所述的布线板,其中,所述第二绝缘层具有与所述第二表面的未形成所述绝缘结构的第二区域的表面实质上共面的上表面。
8.如权利要求1所述的布线板,其中,所述第二上焊盘的一部分布置在所述第一绝缘层上。
9.如权利要求1所述的布线板,其中,所述第二下焊盘的一部分布置在所述第二绝缘层上。
10.如权利要求1所述的布线板,其中,所述至少一个第一上焊盘、所述至少一个第一下焊盘、所述第二上焊盘和所述第二下焊盘均包括电镀层。
11.一种电子装置模块,包括:
如权利要求1所述的布线板;以及
第一电子装置,其安装在所述第二上焊盘上,并分别电连接至所述至少一个第一上焊盘和所述第二上焊盘。
12.如权利要求11所述的电子装置模块,还包括第二电子装置,所述第二电子装置布置在所述至少一个第一上焊盘上并且电连接至所述第一电子装置。
13.如权利要求11所述的电子装置模块,其中,所述至少一个通孔包括多个通孔,并且所述至少一个导电穿通件包括分别布置在所述多个通孔中的多个导电穿通件,
其中,所述至少一个贯穿绝缘部包括分别布置在所述多个通孔与所述多个导电穿通件之间的多个贯穿绝缘部,并且所述第一绝缘层和所述第二绝缘层分别在所述第一表面和所述第二表面上从所述多个贯穿绝缘部延伸并且布置在围绕所述多个导电穿通件的所述第一区域中,
其中,所述至少一个第一上焊盘包含多个第一上焊盘,所述多个第一上焊盘分别布置在所述第一绝缘层上,并且电连接至所述多个导电穿通件,并且
其中,所述至少一个第一下焊盘包括多个第一下焊盘,所述多个第一下焊盘分别布置在所述第二绝缘层上,并且电连接至所述多个导电穿通件,并且
其中,所述电子装置模块还包括第二电子装置,所述第二电子装置安装在所述至少一个第一上焊盘上并且电连接至所述至少一个第一上焊盘和所述第二上焊盘。
14.一种电子装置模块,包括:
下封装件,其具有半导体芯片;以及
上封装件,其包括布置在所述下封装件上的布线板以及布置在所述布线板上的第一电子装置和第二电子装置,
其中,所述下封装件包括:
封装基板,其具有布线电路,并且布置有安装在其上以连接至所述布线电路的所述半导体芯片;
框架,其具有容纳所述半导体芯片的容纳部;以及
多个垂直连接导体,其贯穿所述框架的上表面和下表面并且电连接至所述布线电路,
其中,所述上封装件的所述布线板包括:
金属板,其具有面对所述框架的所述上表面的第一表面和与所述第一表面相对的第二表面,并且具有贯穿所述第一表面和所述第二表面的多个通孔;
多个导电穿通件,其分别布置在所述多个通孔中,并且与所述金属板间隔开;
绝缘结构,其包括分别布置在所述多个通孔和所述多个导电穿通件之间的多个贯穿绝缘部、以及分别在所述第一表面和所述第二表面上的第一绝缘层和第二绝缘层,所述第一绝缘层和所述第二绝缘层从所述多个贯穿绝缘部延伸并且布置在围绕所述多个导电穿通件的第一区域中;
多个第一上焊盘和多个第一下焊盘,其分别布置在所述第一绝缘层和所述第二绝缘层上,并分别电连接至所述多个导电穿通件;以及
第二上焊盘和第二下焊盘,其分别布置在所述金属板的所述第一表面和所述第二表面上,并且通过所述金属板彼此电连接,并且
其中,所述第一电子装置和所述第二电子装置分别安装在所述多个第一上焊盘中的至少一个和所述第二上焊盘上,并且分别电连接至所述多个第一上焊盘中的所述至少一个和所述第二上焊盘,并且所述多个第一下焊盘和所述第二下焊盘分别电连接至所述垂直连接导体。
15.如权利要求14所述的电子装置模块,其中,所述半导体芯片包括驱动集成电路芯片,并且
其中,所述第一电子装置包括激光二极管芯片或半导体发光二极管芯片,所述第二电子装置包括光电二极管芯片。
16.如权利要求15所述的电子装置模块,其中,所述驱动集成电路芯片以倒装芯片方式接合到所述封装基板,并且所述驱动集成电路芯片的上表面是非有源表面。
17.如权利要求16所述的电子装置模块,还包括热界面材料层,所述热界面材料层布置在所述驱动集成电路芯片的所述上表面与所述第二下焊盘之间。
18.如权利要求14所述的电子装置模块,其中,所述上封装件还包括布置在所述布线板上并且具有向上开口的窗口的透镜壳体、以及布置在所述透镜壳体的所述窗口中的透镜单元。
19.如权利要求18所述的电子装置模块,其中,所述下封装件的侧表面分别与所述上封装件的侧表面实质上共面。
20.一种布线板,包括:
金属板,其具有彼此相对的第一表面和第二表面,所述第一表面和所述第二表面中的每一个被划分为第一区域和第二区域,其中,所述第一区域具有比所述第二区域低的水平高度,并且所述金属板包括贯穿所述第一表面和所述第二表面的所述第一区域的至少一个通孔;
绝缘结构,其包括沿所述至少一个通孔的侧壁布置的至少一个贯穿绝缘部、从所述至少一个贯穿绝缘部延伸到所述第一表面的所述第一区域的第一绝缘层、以及从所述至少一个贯穿绝缘部延伸到所述第二表面的所述第一区域的第二绝缘层;
至少一个导电穿通件,其贯穿所述绝缘结构以位于所述至少一个通孔中,并且通过所述至少一个贯穿绝缘部与所述金属板电绝缘;
至少一个第一上焊盘和至少一个第一下焊盘,其分别布置在所述第一绝缘层和所述第二绝缘层上,并且通过所述至少一个导电穿通件彼此电连接;以及
第二上焊盘和第二下焊盘,其分别布置在所述第一表面的所述第二区域和所述第二表面的所述第二区域上,并且通过所述金属板彼此电连接。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020200010939A KR20210097855A (ko) | 2020-01-30 | 2020-01-30 | 금속 베이스 배선 기판 및 전자소자 모듈 |
KR10-2020-0010939 | 2020-01-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113271712A true CN113271712A (zh) | 2021-08-17 |
Family
ID=77062751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110125148.8A Pending CN113271712A (zh) | 2020-01-30 | 2021-01-29 | 布线板和电子装置模块 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11670576B2 (zh) |
KR (1) | KR20210097855A (zh) |
CN (1) | CN113271712A (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020088208A1 (en) * | 2018-11-01 | 2020-05-07 | Changxin Memory Technologies, Inc. | Wafer stacking method and wafer stacking structure |
TWI751554B (zh) * | 2020-05-12 | 2022-01-01 | 台灣愛司帝科技股份有限公司 | 影像顯示器及其拼接式電路承載與控制模組 |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1758169A3 (en) | 1996-08-27 | 2007-05-23 | Seiko Epson Corporation | Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same |
USRE38466E1 (en) | 1996-11-12 | 2004-03-16 | Seiko Epson Corporation | Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device |
US7208725B2 (en) | 1998-11-25 | 2007-04-24 | Rohm And Haas Electronic Materials Llc | Optoelectronic component with encapsulant |
JP3906654B2 (ja) | 2000-07-18 | 2007-04-18 | ソニー株式会社 | 半導体発光素子及び半導体発光装置 |
US6818465B2 (en) | 2001-08-22 | 2004-11-16 | Sony Corporation | Nitride semiconductor element and production method for nitride semiconductor element |
US6787916B2 (en) | 2001-09-13 | 2004-09-07 | Tru-Si Technologies, Inc. | Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity |
JP2003218034A (ja) | 2002-01-17 | 2003-07-31 | Sony Corp | 選択成長方法、半導体発光素子及びその製造方法 |
JP3815335B2 (ja) | 2002-01-18 | 2006-08-30 | ソニー株式会社 | 半導体発光素子及びその製造方法 |
KR100499129B1 (ko) | 2002-09-02 | 2005-07-04 | 삼성전기주식회사 | 발광 다이오드 및 그 제조방법 |
US7002182B2 (en) | 2002-09-06 | 2006-02-21 | Sony Corporation | Semiconductor light emitting device integral type semiconductor light emitting unit image display unit and illuminating unit |
KR100714639B1 (ko) | 2003-10-21 | 2007-05-07 | 삼성전기주식회사 | 발광 소자 |
KR100506740B1 (ko) | 2003-12-23 | 2005-08-08 | 삼성전기주식회사 | 질화물 반도체 발광소자 및 그 제조방법 |
JP4960099B2 (ja) * | 2004-10-04 | 2012-06-27 | 株式会社東芝 | 発光装置及びそれを用いた照明器具または液晶表示装置 |
KR100664985B1 (ko) | 2004-10-26 | 2007-01-09 | 삼성전기주식회사 | 질화물계 반도체 소자 |
KR100665222B1 (ko) | 2005-07-26 | 2007-01-09 | 삼성전기주식회사 | 확산재료를 이용한 엘이디 패키지 및 그 제조 방법 |
KR100661614B1 (ko) | 2005-10-07 | 2006-12-26 | 삼성전기주식회사 | 질화물계 반도체 발광소자 및 그 제조방법 |
KR100723247B1 (ko) | 2006-01-10 | 2007-05-29 | 삼성전기주식회사 | 칩코팅형 led 패키지 및 그 제조방법 |
KR100735325B1 (ko) | 2006-04-17 | 2007-07-04 | 삼성전기주식회사 | 발광다이오드 패키지 및 그 제조방법 |
KR100930171B1 (ko) | 2006-12-05 | 2009-12-07 | 삼성전기주식회사 | 백색 발광장치 및 이를 이용한 백색 광원 모듈 |
KR100855065B1 (ko) | 2007-04-24 | 2008-08-29 | 삼성전기주식회사 | 발광 다이오드 패키지 |
KR100982980B1 (ko) | 2007-05-15 | 2010-09-17 | 삼성엘이디 주식회사 | 면 광원 장치 및 이를 구비하는 lcd 백라이트 유닛 |
KR101164026B1 (ko) | 2007-07-12 | 2012-07-18 | 삼성전자주식회사 | 질화물계 반도체 발광소자 및 그 제조방법 |
KR100891761B1 (ko) | 2007-10-19 | 2009-04-07 | 삼성전기주식회사 | 반도체 발광소자, 그의 제조방법 및 이를 이용한 반도체발광소자 패키지 |
US8531024B2 (en) | 2008-03-25 | 2013-09-10 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and multilevel conductive trace |
US8288792B2 (en) * | 2008-03-25 | 2012-10-16 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base/post heat spreader |
KR101332794B1 (ko) | 2008-08-05 | 2013-11-25 | 삼성전자주식회사 | 발광 장치, 이를 포함하는 발광 시스템, 상기 발광 장치 및발광 시스템의 제조 방법 |
KR20100030470A (ko) | 2008-09-10 | 2010-03-18 | 삼성전자주식회사 | 다양한 색 온도의 백색광을 제공할 수 있는 발광 장치 및 발광 시스템 |
KR101530876B1 (ko) | 2008-09-16 | 2015-06-23 | 삼성전자 주식회사 | 발광량이 증가된 발광 소자, 이를 포함하는 발광 장치, 상기 발광 소자 및 발광 장치의 제조 방법 |
US8008683B2 (en) | 2008-10-22 | 2011-08-30 | Samsung Led Co., Ltd. | Semiconductor light emitting device |
KR101124102B1 (ko) * | 2009-08-24 | 2012-03-21 | 삼성전기주식회사 | 발광 소자 패키지용 기판 및 이를 포함하는 발광 소자 패키지 |
KR101394205B1 (ko) | 2010-06-09 | 2014-05-14 | 에스케이하이닉스 주식회사 | 반도체 패키지 |
KR20140020114A (ko) * | 2012-08-08 | 2014-02-18 | 삼성전기주식회사 | 금속 방열기판 및 그 제조방법 |
KR102107038B1 (ko) | 2012-12-11 | 2020-05-07 | 삼성전기주식회사 | 칩 내장형 인쇄회로기판과 그를 이용한 반도체 패키지 및 칩 내장형 인쇄회로기판의 제조방법 |
KR102103375B1 (ko) | 2013-06-18 | 2020-04-22 | 삼성전자주식회사 | 반도체 패키지 |
US9252127B1 (en) | 2014-07-10 | 2016-02-02 | Invensas Corporation | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture |
US9601472B2 (en) | 2015-04-24 | 2017-03-21 | Qualcomm Incorporated | Package on package (POP) device comprising solder connections between integrated circuit device packages |
US20180130768A1 (en) | 2016-11-09 | 2018-05-10 | Unisem (M) Berhad | Substrate Based Fan-Out Wafer Level Packaging |
-
2020
- 2020-01-30 KR KR1020200010939A patent/KR20210097855A/ko active Search and Examination
- 2020-10-01 US US17/060,248 patent/US11670576B2/en active Active
-
2021
- 2021-01-29 CN CN202110125148.8A patent/CN113271712A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US11670576B2 (en) | 2023-06-06 |
US20210242118A1 (en) | 2021-08-05 |
KR20210097855A (ko) | 2021-08-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102615197B1 (ko) | 반도체 패키지 | |
US7276786B2 (en) | Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted | |
CN107708303B (zh) | 印刷电路板和包括印刷电路板的半导体封装件 | |
US7649249B2 (en) | Semiconductor device, stacked structure, and manufacturing method | |
KR101501739B1 (ko) | 반도체 패키지 제조 방법 | |
JP2902937B2 (ja) | 高性能コンピュータ用の3次元パッケージおよび構造 | |
JP4659488B2 (ja) | 半導体装置及びその製造方法 | |
KR100865125B1 (ko) | 반도체 패키지 및 그 제조방법 | |
US20170207200A1 (en) | Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same | |
JP4463178B2 (ja) | 半導体装置及びその製造方法 | |
US20070290300A1 (en) | Semiconductor device and method for manufacturing same | |
KR20130042936A (ko) | 칩 캐리어, 이를 이용한 반도체 칩, 반도체 패키지, 및 그 제조방법들 | |
KR20090047776A (ko) | 반도체 소자 및 그 형성 방법 | |
US20060220207A1 (en) | Stacked semiconductor package | |
KR20100099573A (ko) | 반도체 장치 및 그 제조방법 | |
KR102619532B1 (ko) | 반도체 패키지 | |
CN113271712A (zh) | 布线板和电子装置模块 | |
CN110364513A (zh) | 半导体芯片和包括半导体芯片的半导体封装 | |
US6858932B2 (en) | Packaged semiconductor device and method of formation | |
KR20220077762A (ko) | 방열층을 포함한 반도체 패키지 | |
JP3944898B2 (ja) | 半導体装置 | |
CN116705626A (zh) | 封装结构及其形成方法 | |
US7605475B2 (en) | Semiconductor device | |
KR20240005256A (ko) | 반도체 패키지 및 그 제조방법 | |
CN114520460A (zh) | 包括在导芯上具有导体填充沟槽的基板的光学设备 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |