CN1131560C - 集成电路及其制造方法 - Google Patents
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Abstract
一种形成集成电路的方法，包括：提供一基底，该基底具有一衬垫氮化物层，该衬垫氮化物层具有一第一氮化物层和一第二氮化物层，其中该衬垫氮化物层在含氮气氛中进行退火，使得所述第二氮化物层比所述第一氮化物层更致密和更硬。本发明的一种集成电路，包括一基底，在基底上形成有衬垫叠层，其中，衬垫叠层包括一衬垫内侧，其具有一第一氮化物层和一第二氮化物层，该第二氮化物层比第一氮化物层更致密和更硬。在NH3或N2气氛中将衬垫层退火提高了衬垫层的耐腐蚀性和抛光性。所以集成电路处理期间的过侵蚀减少，从而提高了成品率。
Description
技术领域
本发明一般涉及集成电路及其制造方法，特别涉及器件制造过程中采用氮化物腐蚀停止层。
背景技术
在器件的制造中，在衬底或晶片上形成绝缘层、半导体层和导电层。构图各层，产生图形和间隔，形成如晶体管、电容器和电阻器等器件。然后将这些器件互联以实现所需的电功能，于是得到集成电路(IC)或芯片。
氮化层一般用作腐蚀或抛光停止层，以便于各层的构图。这种氮化层被称为衬垫(Pad)氮化层。常规的衬垫氮化层是由低压化学汽相淀积(LPCVD)形成的。
然而，常规衬垫氮化层在腐蚀或抛光工艺中会过侵蚀。例如，器件处理后，由于化学机械抛光(CMP)，在晶片的中心，衬垫氮化层的厚度可能减少约30％，靠近晶片的边缘厚度减小量超过40％，反应离子刻蚀(RIE)和化学干法腐蚀(CDE)也有比化学机械抛光较小程度的过侵蚀，过量的侵蚀会导致成品率降低。
从上面的讨论可知，希望提供一种改进的腐蚀停止层。
沟槽形成后，采用常规处理，形成沟槽电容器DRAM单元260，如图2B所示。例如Nesbit等人在
有自对准掩埋条(BEST)的0.6μm 2 256Mb的沟 槽DRAM单元，IEDM 93-627(Nesbit et al.，
A 0.6μm2 256Mb Trench DRAM Cell With Self-Aligned Buried Strap(BEST)，IEDM 93-627)中描述了这种常规沟槽电容器DRAM单元，此处引用作为参考。其包括形成的掩埋极板265、节点介质268、轴环264、存储节点270、掩埋条263、STI273、表示有源和跨越字线的栅导体275和280、层间介质层282、接触开口280、及位线285。一般情况下，这种单元阵列借助字线和位线互联，形成DRAM芯片。
发明内容
从上面的讨论可知，希望提供一种改进的腐蚀停止层的集成电路及其形成方法。
为实现上述目的，本发明一方面提供一种形成集成电路的方法，包括：提供一基底，该基底具有一衬垫氮化硅层，该衬垫氮化硅层具有一第一氮化硅层和一第二氮化硅层，其中该衬垫氮化硅层在含氮气氛中进行退火，使得所述第二氮化硅层比所述第一氮化硅层更致密和更硬。
本发明另一方面提供一种集成电路，包括一基底，在基底上形成有衬垫叠层，其中，衬垫叠层包括一衬垫内侧，其具有一第一氮化硅层和一第二氮化硅层，该第二氮化硅层比第一氮化硅层更致密和更硬。
根据本发明，可以有效地防止衬垫氮化物层受到过度侵蚀。
附图说明
图1是根据本发明一个实施例的衬垫氮化层；
图2A-2B展示了根据本发明一个实施例形成沟槽电容器DRAM单元的工艺；
图3-4展示了根据本发明一个实施例由于所形成的衬垫氮化层降低了CMP速率的实验结果。
具体实施方式
本发明涉及改进的衬垫氮化层。为了说明的目的，以例如用于沟槽电容器DRAM单元制造的衬垫叠层为例进行描述。但是，本发明具有相当的普遍性，可延伸到用于一般集成电路(IC)的制造中的衬垫氮化层。这种集成电路例如包括随机存取存储器(RAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、静态RAM(SRAM)、和只读存储器(ROM)。其它IC包括如可编程逻辑阵列(PFA)、专用IC(ASIC)、合并DRAM或其它电路器件。一般情况下，在一块如硅晶片等半导体衬底上可并排制造大量IC。处理后，将晶片划片，以将IC分割成大量分立芯片。然后将这些芯片封装成例如周于如计算机系统、蜂窝电话、个人数字助手(PDAs)等用户产品和其它电子产品的最终产品。
参见图1，该图展示了根据本发明一个实施例的衬垫叠层105。该衬垫叠层形成于衬底101上。包括衬垫氧化层110、衬垫氮化层120和深沟槽硬腐蚀掩模130。该衬垫叠层用于深沟槽DRAM单元的制造。如图所示，该衬垫氮化层包括第一氮化层121和第二氮化层122。第二氮化层比第一氮化层更致密且更硬。通过提供第二较致密且较硬的氮化层，可以减少处理过程中衬垫氮化层的侵蚀。
图2A-2B展示了形成深沟槽DRAM单元的工艺，包括根据本发明形成衬垫叠层。参见图2A，提供将于其上制造DRAM单元的衬底201。对衬底主表面没有严格要求，可以用任何合适的晶向，如(100)、(110)、或(111)。在一个例示实施例中，衬底用第一导电类型的掺杂剂轻掺杂。在一个实施例中，衬底用如B等p型掺杂剂轻掺杂(p-)。B的浓度为约1-2×1016cm-3。
衬底可以包括含有第二导电类型掺杂剂的掩埋阱240。在一个实施例中，掩埋阱包括n型掺杂剂，如As或P掺杂剂。例如构图一个掩模，以限定掩埋阱区。然后向衬底的掩埋阱区注入P掺杂剂。注入以相当大的能量和剂量进行，以在将要形成的轴环下形成P掺杂剂的峰值浓度。掩埋阱的作用是隔离P阱与衬底，另外在电容器的掩埋极板之间构成导电桥。注入的浓度和能量大约大于1×1013原子/cm2在大约1.5MeV。可选择地是，通过注入然后在衬底表面上生长外延层来形成掩埋阱。Bronner等人的美国专利5250829中记载了这种技术，这里引入作为参考。
在衬底的表面上形成衬垫氧化层210。在衬垫氧化层上的是衬垫氮化层221。通过LPCVD淀积用作抛光停止层的衬垫氮化层。一般氮化层221的厚度为约200nm。自然，其实际厚度取决于特定的应用。
根据本发明，在NH3或N2气氛中将衬垫氮化层退火，以形成氮化层222。最好是在富氮的气氛中进行退火。在一个实施例中，采用快速热退火(RTA)。RTA在NH3或N2气氛中，温度为约900-1200℃，持续时间为0.01-10分钟。在一个实施例中，RTA在1150℃下进行约3分钟。另外也可以用炉退火氮化层。炉退火在NH3或N2气氛中、约900-1200℃的温度下进行1-600分钟。在一个实施例中，炉退火在1100℃下进行约60分钟。
通过提供带有第一层和第二硬化氮化层的衬垫氮化层，可以降低腐蚀和抛光的速率。所以，可以在随后的腐蚀和抛光步骤中减少对衬垫氮化层的过量侵蚀。具体说，可以避免晶片边缘比晶片中心的过侵蚀。因此可以减少晶片阈值电压的漂移和成品率降低。
然后在氮化层222上形成硬掩模层230。硬掩模例如包括TEOS。硬掩模也可用如BSG等其它材料。另外，可以采用抗反射涂层(ARC)改善光刻分辨率。
利用常规的光刻技术构图硬掩模层，限定将要形成沟槽的区。限定深沟槽区包括淀积光刻胶层，并按所需图形对之进行选择曝光。然后将光刻胶显影，并根据所用光刻胶的正或负性去掉曝光或未曝光的部分。然后腐蚀衬垫叠层的暴露部分，直到衬底的表面。通过反应离子刻蚀(RIE)形成深沟槽213。如果用BSG作硬掩模，则将它去掉。这是因为BSG层可以通过相对氧化物有选择性的湿法腐蚀被去掉。由此避免了沟槽开口中的衬垫氧化层的侵蚀。
形成沟槽后，采用常规工艺形成沟槽电容器DRAM单元260。如图2B所示。例如Nesbit等人在
有自对准掩埋条(BEST)的0.6μm 2 256Mb的沟槽 DRAM单元，IEDM 93-627中(Nesbit et al.，
A 0.6μm2 256Mb Trench DRAM Cell With Self-Aligned Buried Strap (BEST)，IEDM 93-627)描述了这种常规沟槽电容器DRAM单元，此处引用作为参考。其包括形成的掩埋极板265、节点介质268、轴环264、存储节点270、掩埋条263、STI273、表示有源和跨越字线的栅导体275和280、层间介质层282、接触开口280、及位线285。一般情况下，这种单元阵列借助字线和位线互联，形成DRAM芯片。
例1
进行该实验的目的是验证由于在NH3气氛中退火基底层导致的化学机械抛光(CMP)速率的降低。该实验测量了没进行退火、在950℃退火、1050℃退火和1150℃退火条件下的衬垫氮化层的CMP速率。实验结果示于图3。正如所看见的，CMP速率因退火而降低。CMP速率随退火温度升高和退火时间的加长而减小。在1150℃下退火2分钟，CMP速率比没有退火的衬垫氮化层降低约20％。所以增大热预算可以增大衬垫氮化层的厚度和硬度，因而降低了腐蚀率。
例2
图4展示了在NH3或N2气氛中退火(线410)和不退火(线420)条件下氮化层侵蚀情况的差异。在形成深沟槽电容器的各抛光步骤测量侵蚀情况。如图所示，与退火的衬垫氮化层相比，没有退火的衬垫氮化层发生了由CMP引起的严重侵蚀。
尽管这里参照实施例对本发明进行了具体描述，但本领域的技术人员应该认识到，在不背离本发明范围的情况下，可以对本发明作出各种改形和变化。因此，本发明的范围并非由以上的说明书所限定，而是由权利要求书及其等物的范围限定的。
Claims (2)
1.一种形成集成电路的方法，包括：
提供一基底，该基底具有一衬垫氮化硅层，该衬垫氮化硅层具有一第一氮化硅层和一第二氮化硅层，其中该衬垫氮化硅层在含氮气氛中进行退火，使得所述第二氮化硅层比所述第一氮化硅层更致密和更硬。
2.一种集成电路，包括一基底，在基底上形成有衬垫叠层，其中，衬垫叠层包括一衬垫内侧，其具有一第一氮化硅层和一第二氮化硅层，该第二氮化硅层比第一氮化硅层更致密和更硬。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US94089697A | 1997-09-30 | 1997-09-30 | |
| US940,896 | 1997-09-30 | ||
| US940896 | 1997-09-30 |
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| CN1224928A CN1224928A (zh) | 1999-08-04 |
| CN1131560C true CN1131560C (zh) | 2003-12-17 |
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| JP (1) | JPH11186242A (zh) |
| KR (1) | KR19990030192A (zh) |
| CN (1) | CN1131560C (zh) |
| TW (1) | TW406341B (zh) |
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| EP1282160A1 (de) * | 2001-07-31 | 2003-02-05 | Infineon Technologies AG | Verfahren zur Herstellung von Schichten eines Nitrid/Oxid-Dielektrikums |
| TWI340431B (en) * | 2007-06-11 | 2011-04-11 | Nanya Technology Corp | Memory structure and method of making the same |
| US9502263B2 (en) * | 2014-12-15 | 2016-11-22 | Applied Materials, Inc. | UV assisted CVD AlN film for BEOL etch stop application |
| CN109216153B (zh) * | 2017-07-03 | 2021-01-05 | 无锡华润上华科技有限公司 | 提高氮化硅耐腐蚀性的方法和半导体器件的制备方法 |
| CN108387423A (zh) * | 2018-02-23 | 2018-08-10 | 深圳顺络电子股份有限公司 | 一种改善ltcc基板盐雾可靠性的方法 |
| CN112768404A (zh) * | 2021-01-26 | 2021-05-07 | 上海华力微电子有限公司 | 半导体器件的制造方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5411913A (en) * | 1994-04-29 | 1995-05-02 | National Semiconductor Corporation | Simple planarized trench isolation and field oxide formation using poly-silicon |
| JPH0864705A (ja) * | 1994-08-26 | 1996-03-08 | Sony Corp | 半導体記憶装置の製造方法 |
| US5643823A (en) * | 1995-09-21 | 1997-07-01 | Siemens Aktiengesellschaft | Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures |
-
1998
- 1998-09-24 EP EP98118127A patent/EP0908942A3/en not_active Withdrawn
- 1998-09-28 KR KR1019980040204A patent/KR19990030192A/ko not_active Application Discontinuation
- 1998-09-30 JP JP10278465A patent/JPH11186242A/ja not_active Withdrawn
- 1998-09-30 CN CN98120589A patent/CN1131560C/zh not_active Expired - Fee Related
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1999
- 1999-01-26 TW TW087116257A patent/TW406341B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990030192A (ko) | 1999-04-26 |
| EP0908942A2 (en) | 1999-04-14 |
| TW406341B (en) | 2000-09-21 |
| EP0908942A3 (en) | 2002-03-13 |
| CN1224928A (zh) | 1999-08-04 |
| JPH11186242A (ja) | 1999-07-09 |
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