US20060246658A1 - A capacitor electrode having an interface layer of different chemical composition formed on a bulk layer - Google Patents
A capacitor electrode having an interface layer of different chemical composition formed on a bulk layer Download PDFInfo
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- US20060246658A1 US20060246658A1 US11/456,435 US45643506A US2006246658A1 US 20060246658 A1 US20060246658 A1 US 20060246658A1 US 45643506 A US45643506 A US 45643506A US 2006246658 A1 US2006246658 A1 US 2006246658A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Definitions
- the present invention relates to capacitor structures used in semiconductor devices and, in particular, relates to capacitor structures used to form memory cells in Dynamic Random Access Memory (DRAM) devices.
- DRAM Dynamic Random Access Memory
- circuit components such as capacitors and transistors
- circuit components such as capacitors and transistors
- circuit components having reduced dimensions are often unable to provide an acceptable performance
- further improvements in circuit density requires the development of improved circuit components.
- a typical high density Dynamic Random Access Memory (DRAM) device may include an array of hundreds of millions of memory cells. Each memory cell usually includes a charge storage capacitor such that the state of charge of the capacitor determines the binary state of the memory cell.
- the capacitor comprises an insulating material interposed between first and second conducting electrodes.
- the insulating material is a deposited dielectric material and one or both of the electrodes comprise doped semiconductor material such as doped polysilicon.
- the typical capacitor has a capacitance that is approximately proportional to a function of the design parameters of the capacitor according to C ⁇ A/d (2), wherein A is the area of each of the electrodes, d is the distance between the electrodes, and ⁇ is the dielectric constant of the insulating material.
- DRAM devices Because capacitors have a tendency to discharge relatively quickly, DRAM devices also incorporate refresh circuitry that periodically and selectively recharges the capacitors so as to enable the DRAM device to store information for extended periods of time. However, since memory cells cannot be accessed while they are being refreshed, it is desirable to extend the time between refresh cycles so as to provide the DRAM device with increased communication speeds. Thus, storage capacitors of DRAM devices are required to have a considerable capacitance so that they can effectively store charge for longer periods of time and, thus, require only a reasonably small refresh frequency.
- one or both electrodes of the storage capacitors can be formed with a roughened surface, such as that which is provided by hemispherical grained (HSG) polysilicon, so as to increase the area over that which is provided by electrodes having planar surfaces.
- HSG hemispherical grained
- Other methods of providing increased capacitance involve using an insulating material having an increased dielectric constant and reducing the thickness of the dielectric insulating layer so as to reduce the distance between the electrodes.
- a depletion region substantially devoid of mobile charge carriers develops within the electrode.
- the depletion region begins at the interface adjacent the insulating layer and progressively extends into the electrode away from the insulating layer as more charge carriers are removed from the electrode.
- the net charge of the electrode is essentially comprised of ionized dopant atoms fixedly disposed throughout the depletion region, further enlargement of the depletion region as a result of further mobile charge carriers being removed from the electrode causes the geometric center of the electrode charge to be displaced away from the interface. Consequently, since the effect of the displacement of the geometric center of charge is identical to that of increasing the separation between the electrodes, i.e., an increase in the variable d in equation (2), the capacitance decreases as the applied voltage to the capacitor is increased.
- an N-type polysilicon electrode is usually annealed in a phosphine (PH 3 ) ambient so as to induce phosphorus atoms to diffuse into the electrode.
- PH 3 phosphine
- the conditions of this process are chosen so that the doping concentration is greatest near the interface adjacent the insulating layer.
- the maximum achievable concentration is limited by the solid solubility limit of the polysilicon electrode and, if the electrode is exposed to increased temperatures in a subsequent processing step, it is likely that a substantial portion of the dopants will continue to diffuse so as to decrease the doping concentration adjacent the interface.
- a capacitor comprising a first conducting electrode having a richly doped interface layer.
- the first conducting electrode comprises a semiconductor bulk layer having a first surface and the interface layer extending from the first surface of the bulk layer.
- the interface layer comprises a plurality of dopant atoms chemically bonded thereto.
- the capacitor further comprises a second conducting electrode and an insulating layer interposed between the first and second conducting electrodes such that the insulating layer is disposed adjacent the interface layer of the first conducting electrode.
- a method of forming a capacitor comprises forming a first conducting electrode having a bulk layer and an interface layer chemically bonded to the bulk layer, wherein the interface layer comprises a plurality of doping atoms chemically bonded thereto so as to reduce the extent of the depletion region of the first conducting electrode.
- the method further comprises forming an insulating layer adjacent the first conducting electrode such that the insulating layer is disposed adjacent the interface layer of the first conducting electrode.
- the method further comprises forming a second conducting electrode adjacent the insulating layer such that the insulating layer is interposed between the first and second conducting electrodes.
- a method of forming a capacitor comprises forming a bulk layer of doped polysilicon and depositing a layer of adhesive material adjacent a first surface of the bulk layer, wherein the adhesive material comprises a plurality of CH 3 methyl groups.
- the method further comprises replacing a substantial portion of the plurality of CH 3 methyl groups of the adhesive material with PH 3 molecules so as to provide an interface layer having a relatively large concentration of phosphorus dopant atoms.
- the method further comprises passivating the interface layer so as to inhibit the formation of silicon dioxide therein.
- the method further comprises depositing an insulating layer adjacent the interface layer and depositing an electrode adjacent the insulating layer.
- a method of forming a capacitor on a semiconductor wafer comprises forming a first electrode on a surface of the semiconductor wafer, attaching an adhesive layer to an exposed surface of the first electrode, and transforming the adhesive layer into a doped layer.
- the doped layer is doped so as to provide an increased concentration of charge carriers adjacent an interface surface of the first electrode.
- the method further comprises forming a dielectric layer on the interface surface of the first electrode and forming a second electrode on the dielectric layer wherein the doped layer inhibits a decrease in the capacitance as a result of a charge carriers being stored on the second electrode.
- attaching an adhesive layer to an exposed surface of the first electrode comprises depositing a layer of material that have a plurality of first components and second components.
- the plurality of first components are selected to chemically bond to the first electrode.
- Transforming the adhesive layer comprises replacing at least some of the plurality of second components with dopant atoms to thereby increase the dopant concentration at the interface surface.
- Attaching the adhesive layer further comprises attaching a layer having a plurality of CH 3 methyl groups to the first electrode.
- Transforming the adhesive layer further comprises replacing a substantial portion of the plurality of CH 3 methyl groups of the adhesive material with PH 3 molecules so as to provide the interface surface with an increased concentration of phosphorus dopant atoms.
- Forming the adhesive layer preferably comprises depositing a layer of HMDS material and replacing a substantial portion of the plurality of CH 3 methyl groups comprises annealing the layer of HMDS material in a phosphine ambient.
- the aspects of the present invention therefore provide a technique whereby capacitors can be produced that have higher doping concentrations at the interface between the dielectric and at least one electrode.
- the increase in the doping concentration inhibits the formation of extended voltage dependent depletion regions in the electrode that can effectively decrease the capacitance of the capacitor.
- the dopant atoms are less likely to diffuse into the bulk of the electrode material as a result of subsequent processing of the device.
- FIG. 1 is a cross-sectional schematic diagram of a capacitor according to one embodiment of the present invention.
- FIG. 2 is a flow diagram describing a method used to form the capacitor of FIG. 1 ;
- FIG. 3 is a flow diagram describing a method used to form a first electrode of the capacitor of FIG. 1 ;
- FIG. 4 is a cross-sectional diagram of the first electrode of the capacitor of FIG. 1 that schematically illustrates an interface layer comprising a plurality of adhesive molecules bonding to a first surface of a bulk layer of the first electrode;
- FIG. 5 is a cross-sectional diagram of the first electrode of FIG. 4 that schematically illustrates the composition of the first electrode subsequent to an annealing process
- FIG. 6 is a cross-sectional schematic diagram of a DRAM device according to one embodiment of the present invention, wherein the DRAM device comprises the capacitor of FIG. 1 .
- the illustrated embodiment of the present invention comprises a miniaturized capacitor structure having improved operating characteristics and methods for providing the same.
- the capacitor structure is provided with electrodes having increased charge carrier concentrations adjacent an insulating layer such that problems associated with carrier depletion within the electrodes are reduced. Consequently, the capacitor structure is provided with an increased capacitance that is more stable in response to a changing voltage applied between the electrodes.
- Improved capacitors formed according to the methods of the illustrated embodiment are particularly useful in the manufacture of DRAM devices. It should be understood, however, that the methods of providing improved capacitors according to the present invention could be used in any application or structure in which it is desirable to include miniaturized capacitors having stable capacitance. Furthermore, the methods of the present invention are particularly well-suited for providing improved capacitors on or above a semiconductor substrate or substrate assembly, referred to herein generally as “substrate,” used in forming integrated circuits, such as a silicon wafer, with or without layers or structures formed thereon. It is to be understood that the methods of the present invention are not limited to deposition on silicon wafers; rather, other types of wafers (e.g., gallium arsenide, etc.) can be used as well.
- the capacitors provided by the methods of the present invention are not limited to any particular geometrical configuration.
- the capacitors described hereinbelow can have parallel planar electrodes, trench-type electrodes, or cylindrically shaped electrodes.
- the skilled artisan will find application for the processes and materials discussed below for any of a number of capacitor configurations.
- FIG. 1 illustrates a capacitor 30 in accordance with one embodiment of the present invention and FIG. 2 illustrates a method of providing the same.
- the capacitor comprises first and second conducting electrodes 32 and 34 , otherwise referred to hereinbelow as the lower and upper electrodes 32 and 34 .
- the capacitor 30 further comprises an insulating layer 36 interposed between the electrodes 32 and 34 such that the capacitor 30 has a capacitance that substantially depends on the surface area of the electrodes 32 and 34 , the distance, d, between the electrodes 32 and 34 , and the dielectric constant of the insulating layer 36 .
- At least one of the first and second electrodes 32 , 34 comprises semiconductor material, such as doped polysilicon and the insulating layer 36 comprises any of a number of known high- ⁇ insulating dielectrics such as silicon nitride or Ta 2 O 5 .
- the first electrode 32 comprises a bulk layer 40 of polysilicon and a richly doped and relatively thin interface layer 42 extending from the bulk layer 40 .
- the interface layer 42 is interposed between the bulk layer 40 and the insulating layer 36 in a substantially flush manner.
- the interface layer 42 is heavily doped so that the depletion region of the first electrode 32 caused by the removal of mobile charge carriers from the electrode 32 is confined within the thin interface layer 42 under normal operating conditions.
- the interface layer 42 of the first electrode has a thickness of 15 ⁇ and a doping concentration of 1 ⁇ 10 21 Atoms/cm 3 so that the thickness of the depletion region of the electrode 32 is less than 5 ⁇ in response to an applied voltage that varies within a range of ⁇ 3V-3V.
- the bulk layer 40 has a thickness of 350 ⁇ and a doping concentration of 4 ⁇ 10 20 Atoms/cm 3 .
- the bulk region 40 of the electrode 32 comprises Hemi-Spherical Grained (HSG) polysilicon and the interface layer 42 is conformally deposited thereon so that the electrode 32 has an effective surface area greater than that of a planar surface.
- the dopant atoms of the first electrode 32 are preferably selected from the pentavalent elements, such as phosphorus, so that the mobile charge carriers of the first electrode 32 are electrons.
- the interface layer could be deposited during formation of the HSG bulk layer 40 and the dopant atoms could be selected from trivalent atoms so that the mobile charge carriers are holes.
- the method of forming the capacitor 30 of FIG. 1 comprises, in a state 100 , first forming the first electrode 32 having the richly doped interface layer 42 so as to reduce the severity of the depletion effect.
- the method of forming the first electrode 32 will be described in greater detail below.
- the method of forming the capacitor 30 further comprises, in a state 102 , depositing the insulating layer 36 adjacent the first electrode in a well known manner and then, in a state 104 , depositing the second electrode 34 adjacent the insulating layer 36 .
- the second electrode 34 is formed in a well known manner.
- the second electrode 34 could comprise a semiconductor material and it could be provided with a similar richly doped interface layer adjacent the insulating layer 36 using the methods described hereinbelow so as to reduce carrier depletion within the second electrode 34 .
- FIGS. 3-5 illustrate the preferred method of forming the first electrode 32 of the capacitor 30 of FIG. 1 .
- the method comprises, in state 110 , forming the bulk layer 40 of the first electrode 32 of doped semiconductor material using any of a number of known deposition methods.
- U.S. Pat. No. 5,759,262, U.S. Pat. No. 5,882,979, U.S. Pat. No. 5,933,727, and U.S. Pat. No. 6,027,970 which are incorporated herein by reference in their entirety, disclose various acceptable methods of forming the bulk layer 40 of HSG silicon above a semiconductor substrate.
- the bulk layer 40 could be formed with a non-roughened surface using any of a number of known deposition processes, such as chemical vapor deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or the like, without departing from the spirit of the present invention.
- CVD chemical vapor deposition
- LPCVD Low Pressure Chemical Vapor Deposition
- PECVD plasma enhanced chemical vapor deposition
- PVD physical vapor deposition
- an exposed surface 44 of the bulk layer 40 includes a plurality of bonding sites that are capable of bonding with other atoms.
- the bonding sites correspond to the dangling bonds of Si atoms disposed adjacent the edge of the crystal lattice of the bulk layer 40 .
- These bonding sites can be detrimental if they bond with O 2 to form a layer of insulating SiO 2 on the surface 44 of the bulk layer 40 since the added layer of SiO 2 has a relatively small dielectric constant and, thus, contributes to the capacitor 30 having a reduced capacitance.
- the bonding sites of a silicon electrode are passivated by annealing the electrode in a nitrogen or NH 3 ambient so as to form a layer of S ix N y instead of SiO 2 .
- S ix N y has a larger dielectric constant, its effect on the capacitance is reduced. However, this usually requires exposing the electrode to relatively high temperatures.
- the method of forming the first electrode 32 of the illustrated embodiment utilizes the bonding sites of the bulk layer 40 to increase the doping concentration of the first electrode 32 .
- the method of forming the first electrode 32 further comprises, in a state 112 , depositing an adhesive layer 46 ( FIG. 4 ) having a plurality of adhesive molecules over the bulk layer 40 so that a substantial portion of the adhesive molecules bonds to the bonding sites of the bulk layer 40 .
- the purpose of the adhesive layer is to attract and capture dopant atoms with relatively high affinity so that the dopant atoms are disposed substantially near the adhesive layer.
- the adhesive layer 46 comprises a plurality of hexamethldisilazane (HMDS) molecules 50 .
- Each HMDS molecule 50 comprises a nitrogen atom 52 which is capable of bonding to a Si bonding site 54 of the bulk layer 40 of the first electrode 32 .
- Each HMDS molecule 50 further comprises first and second silicon atoms 56 and 58 that bond to the same nitrogen atom 52 .
- each HMDS molecule 50 comprises first, second, and third CH 3 methyl groups 60 , 62 and 64 that chemically bond to each of the silicon atoms 56 , 58 of the HMDS molecule.
- the HMDS adhesive layer 46 can be deposited using any of a number of conventional deposition processes.
- the layer 46 is deposited using LPCVD with a pressure of 100 mTorr and a temperature of 150° C.
- the layer 46 is preferably deposited so that it conformally covers the exposed surface 44 of the bulk layer 40 .
- a substantial portion of the HMDS molecules 50 are bonded directly to the bonding sites 54 of the bulk layer 40 disposed adjacent the surface 44 of the bulk layer 40 so that the adhesive layer 46 has a thickness approximately equal to the diameter of the HMDS molecule 50 .
- the method of forming the first electrode 32 further comprises, in a state 114 , doping the adhesive layer 46 so as to transform the adhesive layer 46 into the interface layer 42 of FIG. 1 .
- doping the adhesive layer 46 comprises annealing the adhesive layer 46 in a phosphorus ambient.
- the adhesive layer 46 is annealed in a phosphine ambient (PH 3 ) so as to modify the composition of the layer 46 .
- PH 3 phosphine ambient
- each HMDS molecule includes six CH 3 methyl groups, each HMDS molecule can accommodate up to six PH 3 molecules 66 each having a phosphorus atom disposed therein that contributes to the doping concentration of the interface layer 42 .
- the interface layer 42 can be doped with a relatively large concentration of phosphorus dopant atoms which substantially inhibits the depletion region of the first electrode 32 from extending beyond the interface layer 42 into the bulk layer 40 .
- the HMDS layer 46 is annealed in the PH 3 ambient at a temperature between 350° C. and 800° C.
- the interface layer 42 is provided with a concentration of phosphorus atoms that exceeds approximately 5 ⁇ 10 20 Atoms/cm 3 .
- the method of forming the lower electrode 32 further comprises, in a state 116 , passivating the interface layer 43 so as to reduce the number of dangling Si bonding sites disposed therein.
- the interface layer 42 is exposed to an ambient, such as NH 3 , that comprises nitrogen atoms so that nitrogen atoms from the ambient are attracted to the Si bonding sites 68 of the interface layer to form S ix N y .
- the activation energy required to form such bonds is less than that which is required to form S ix N y over a conventional polysilicon surface.
- the layer can be passivated at a reduced temperature resulting in less diffusion.
- passivating the interface layer 42 comprises exposing the interface layer 42 to an NH 3 ambient having a pressure approximately equal to 760 Torr and a temperature approximately equal to 800° C.
- prior art passivation methods require exposing the device to temperatures above 850° C.
- FIG. 6 illustrates an exemplary memory cell 70 of a DRAM device that includes the capacitor 30 of FIG. 1 .
- a plurality of transistor gate electrodes 72 overlie a substrate 74 , adjacent transistor active areas 76 within the substrate 74 . It will be understood that several transistors are formed across a memory array within a DRAM circuit or chip.
- Field oxide elements 78 isolate the active areas 76 of different transistors.
- An insulating layer is shown covering the gate electrodes 72 .
- a conductive contact 82 is shown extending through the insulating layer 80 to electrically contact an active area 76 between gate electrodes 72 .
- a barrier layer 84 is formed over the conductive contact 82 and a structural layer 86 is then formed over the insulating layer and a barrier layer 32 .
- the structural layer 86 is selectively etchable relative to the underlying insulating layer 80 .
- the surface area and, thus, the capacitance of the capacitor 30 of the memory cell 70 is influenced by the thickness of the structural layer 86 .
- the structural layer 86 preferably has a thickness of greater than about 0.4 ⁇ m, more preferably between about 0.4 ⁇ m and 2.0 ⁇ m.
- a via 88 is formed in the structural layer 86 to expose the underlying contact 82 , and the lower electrode 32 of the capacitor 30 of FIG.
- the insulating layer 36 of the capacitor 30 is deposited over the lower electrode 32 and the second electrode 34 is deposited over the insulating layer 36 .
- the capacitor 30 of the present invention and the methods for providing the same provide many advantages.
- the first electrode 32 of the capacitor 30 is provided with the interface layer 42 having a relatively large concentration of dopant phosphorus atoms.
- the phosphorus atoms are chemically bonded to the interface layer 42 , the phosphorus atoms are less likely to diffuse into the bulk layer 40 .
- the richly doped interface layer 42 of the lower electrode 32 provides the lower electrode 32 with a more localized depletion region that is disposed adjacent the insulating layer 36 of the capacitor 30 . Furthermore, the extent of the depletion region is less effected by mobile charge carriers entering or exiting the lower electrode 32 . Consequently, since reducing the extent of the depletion region reduces the effective distance between the charge on the lower electrode 32 and charge on the upper electrode 34 , the capacitor 30 is able to have an increased capacitance that is more stable in response to changes in the voltage applied between the electrodes.
- the interface layer 42 of the lower electrode 32 has a relatively large concentration of hydrogen atoms.
- hydrogen is provided by the remaining CH 3 methyl groups and by the PH 3 molecules inserted during the annealing process.
- the increased concentration of hydrogen in the interface layer 42 serves as a barrier for preventing oxygen atoms from subsequently diffusing into the lower electrode 32 and, thereby inhibits the formation of capacitance robbing SiO 2 within the lower electrode 32 .
- the increased concentration of hydrogen in the interface layer 42 can source H atoms to the insulating layer 36 so as to nullify dangling Si bonds within the insulating layer 36 .
- the hydrogen concentration is approximately greater than 1.5 ⁇ 10 21 Atoms/cm 3 .
- the capacitor 30 of the present invention is that the richly doped interface layer 42 can be passivated at a reduced temperature. This is a result of the dangling Si bonds of the interface layer requiring a reduced activation energy to form S ix N y when compared to the activation energy required to from S ix N y on a typical polysilicon surface. Consequently, the passivation process of the present invention is less damaging to other components adjacent the capacitor 30 .
Abstract
An improved capacitor that is less susceptible to the depletion effect and methods for providing the same. The capacitor comprises a first and second electrode and an insulating layer interposed therebetween. The first electrode includes a bulk layer comprising n-doped polysilicon. The first electrode also includes an interface layer extending from a first surface of the bulk layer to the insulating layer. The interface layer is heavily doped with phosphorus so that the depletion region of the first electrode is confined substantially within the interface layer. The method of forming the interface layer comprises depositing a layer of hexamethldisilazane (HMDS) material over the first surface of the bulk layer so that HMDS molecules of the HMDS material chemically bond to the first surface of the bulk layer. The method further comprises annealing the layer of HMDS material in a phosphine ambient so as to replace CH3 methyl groups with PH3 molecules. The interface layer is then passivated in a nitrogen ambient having a reduced temperature so as to reduce the number of dangling silicon bonds of the lower electrode in a manner that results in reduced thermal damage to neighboring circuit elements.
Description
- This application is a continuation of U.S. application Ser. No. 11/216,411, filed Aug. 31, 2005, which is a continuation of U.S. application Ser. No. 10/931,511, filed Sep. 1, 2004, which is a divisional application of U.S. application Ser. No. 09/615,549 filed Jul. 13, 2000. The entirety of each of these applications is hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to capacitor structures used in semiconductor devices and, in particular, relates to capacitor structures used to form memory cells in Dynamic Random Access Memory (DRAM) devices.
- 2. Description of the Related Art
- The trend in the semiconductor processing industry has been to provide integrated circuits with increasingly higher circuit densities. Consequently, circuit components, such as capacitors and transistors, disposed within these integrated circuits are required to have reduced dimensions. However, because conventional circuit components having reduced dimensions are often unable to provide an acceptable performance, further improvements in circuit density requires the development of improved circuit components.
- For example, a typical high density Dynamic Random Access Memory (DRAM) device may include an array of hundreds of millions of memory cells. Each memory cell usually includes a charge storage capacitor such that the state of charge of the capacitor determines the binary state of the memory cell. Essentially, the capacitor comprises an insulating material interposed between first and second conducting electrodes. Typically, the insulating material is a deposited dielectric material and one or both of the electrodes comprise doped semiconductor material such as doped polysilicon.
- When a voltage difference, V, is applied between the electrodes of the capacitor, each electrode develops a charge, Q, according to the linear relationship Q=CV (1), wherein C is the capacitance of the capacitor. The typical capacitor has a capacitance that is approximately proportional to a function of the design parameters of the capacitor according to CκA/d (2), wherein A is the area of each of the electrodes, d is the distance between the electrodes, and κ is the dielectric constant of the insulating material. Furthermore, each charged capacitor discharges in an exponentially decaying manner with a decay constant, τ, given by τ=RC (3), wherein R is the resistance between the electrodes.
- Because capacitors have a tendency to discharge relatively quickly, DRAM devices also incorporate refresh circuitry that periodically and selectively recharges the capacitors so as to enable the DRAM device to store information for extended periods of time. However, since memory cells cannot be accessed while they are being refreshed, it is desirable to extend the time between refresh cycles so as to provide the DRAM device with increased communication speeds. Thus, storage capacitors of DRAM devices are required to have a considerable capacitance so that they can effectively store charge for longer periods of time and, thus, require only a reasonably small refresh frequency.
- However, because storage capacitors of higher density DRAM devices are confined within smaller spaces, it is becoming difficult to provide them with sufficient capacitance. Most notably, smaller capacitor size translates into smaller electrode area, A, which, according to (2), results in a decreased capacitance. To provide increased capacitance, one or both electrodes of the storage capacitors can be formed with a roughened surface, such as that which is provided by hemispherical grained (HSG) polysilicon, so as to increase the area over that which is provided by electrodes having planar surfaces. Other methods of providing increased capacitance involve using an insulating material having an increased dielectric constant and reducing the thickness of the dielectric insulating layer so as to reduce the distance between the electrodes.
- However, as the distance between the electrodes is reduced, storage capacitors of DRAM devices are becoming more susceptible to the “depletion effect” such that the capacitance drops off in a voltage dependent manner. In particular, when mobile charge carriers are removed from the doped semiconductor electrode in response to an applied voltage, a depletion region substantially devoid of mobile charge carriers develops within the electrode. The depletion region begins at the interface adjacent the insulating layer and progressively extends into the electrode away from the insulating layer as more charge carriers are removed from the electrode. Because the net charge of the electrode is essentially comprised of ionized dopant atoms fixedly disposed throughout the depletion region, further enlargement of the depletion region as a result of further mobile charge carriers being removed from the electrode causes the geometric center of the electrode charge to be displaced away from the interface. Consequently, since the effect of the displacement of the geometric center of charge is identical to that of increasing the separation between the electrodes, i.e., an increase in the variable d in equation (2), the capacitance decreases as the applied voltage to the capacitor is increased.
- Attempts have been made to reduce the depletion effect by increasing the doping concentration of the interface region of the electrode using conventional diffusion doping techniques. For example, an N-type polysilicon electrode is usually annealed in a phosphine (PH3) ambient so as to induce phosphorus atoms to diffuse into the electrode. The conditions of this process are chosen so that the doping concentration is greatest near the interface adjacent the insulating layer. However, the maximum achievable concentration is limited by the solid solubility limit of the polysilicon electrode and, if the electrode is exposed to increased temperatures in a subsequent processing step, it is likely that a substantial portion of the dopants will continue to diffuse so as to decrease the doping concentration adjacent the interface.
- Thus, known doping methods are only able to provide the interface region of semiconductor electrodes with modest increases in doping concentration. Consequently, because capacitors having reduced sizes will be required in future generation DRAM devices, the problem of carrier depletion requires a more effective solution in order to satisfactorily address the issue of voltage dependent decreases in capacitance.
- From the foregoing, therefore, it will be appreciated that there is a need for a miniaturized semiconductor-based capacitor having more stable operating characteristics. In particular, there is a need for the capacitor to have a relatively large capacitance that is more stable in response to a changing applied voltage. To this end, there is a need for the interface region of the semiconductor electrodes of the capacitor to have a greater concentration of doping atoms so as to reduce the effects of charge carrier depletion.
- According to one aspect of the present invention, the aforementioned needs are satisfied by a capacitor comprising a first conducting electrode having a richly doped interface layer. The first conducting electrode comprises a semiconductor bulk layer having a first surface and the interface layer extending from the first surface of the bulk layer. The interface layer comprises a plurality of dopant atoms chemically bonded thereto. The capacitor further comprises a second conducting electrode and an insulating layer interposed between the first and second conducting electrodes such that the insulating layer is disposed adjacent the interface layer of the first conducting electrode.
- In another aspect of the invention, a method of forming a capacitor is provided. The method comprises forming a first conducting electrode having a bulk layer and an interface layer chemically bonded to the bulk layer, wherein the interface layer comprises a plurality of doping atoms chemically bonded thereto so as to reduce the extent of the depletion region of the first conducting electrode. The method further comprises forming an insulating layer adjacent the first conducting electrode such that the insulating layer is disposed adjacent the interface layer of the first conducting electrode. The method further comprises forming a second conducting electrode adjacent the insulating layer such that the insulating layer is interposed between the first and second conducting electrodes.
- In yet another aspect of the invention, a method of forming a capacitor is provided. The method comprises forming a bulk layer of doped polysilicon and depositing a layer of adhesive material adjacent a first surface of the bulk layer, wherein the adhesive material comprises a plurality of CH3 methyl groups. The method further comprises replacing a substantial portion of the plurality of CH3 methyl groups of the adhesive material with PH3 molecules so as to provide an interface layer having a relatively large concentration of phosphorus dopant atoms. The method further comprises passivating the interface layer so as to inhibit the formation of silicon dioxide therein. The method further comprises depositing an insulating layer adjacent the interface layer and depositing an electrode adjacent the insulating layer.
- In still yet another aspect of the present invention, a method of forming a capacitor on a semiconductor wafer is provided. The method comprises forming a first electrode on a surface of the semiconductor wafer, attaching an adhesive layer to an exposed surface of the first electrode, and transforming the adhesive layer into a doped layer. The doped layer is doped so as to provide an increased concentration of charge carriers adjacent an interface surface of the first electrode. The method further comprises forming a dielectric layer on the interface surface of the first electrode and forming a second electrode on the dielectric layer wherein the doped layer inhibits a decrease in the capacitance as a result of a charge carriers being stored on the second electrode.
- In one embodiment, attaching an adhesive layer to an exposed surface of the first electrode comprises depositing a layer of material that have a plurality of first components and second components. The plurality of first components are selected to chemically bond to the first electrode. Transforming the adhesive layer comprises replacing at least some of the plurality of second components with dopant atoms to thereby increase the dopant concentration at the interface surface. Attaching the adhesive layer further comprises attaching a layer having a plurality of CH3 methyl groups to the first electrode. Transforming the adhesive layer further comprises replacing a substantial portion of the plurality of CH3 methyl groups of the adhesive material with PH3 molecules so as to provide the interface surface with an increased concentration of phosphorus dopant atoms. Forming the adhesive layer preferably comprises depositing a layer of HMDS material and replacing a substantial portion of the plurality of CH3 methyl groups comprises annealing the layer of HMDS material in a phosphine ambient.
- The aspects of the present invention therefore provide a technique whereby capacitors can be produced that have higher doping concentrations at the interface between the dielectric and at least one electrode. The increase in the doping concentration inhibits the formation of extended voltage dependent depletion regions in the electrode that can effectively decrease the capacitance of the capacitor. As the increased doping is achieved through the use of chemical bonding of dopant atoms adjacent the interface, the dopant atoms are less likely to diffuse into the bulk of the electrode material as a result of subsequent processing of the device. These and other objects and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.
-
FIG. 1 is a cross-sectional schematic diagram of a capacitor according to one embodiment of the present invention; -
FIG. 2 is a flow diagram describing a method used to form the capacitor ofFIG. 1 ; -
FIG. 3 is a flow diagram describing a method used to form a first electrode of the capacitor ofFIG. 1 ; -
FIG. 4 is a cross-sectional diagram of the first electrode of the capacitor ofFIG. 1 that schematically illustrates an interface layer comprising a plurality of adhesive molecules bonding to a first surface of a bulk layer of the first electrode; -
FIG. 5 is a cross-sectional diagram of the first electrode ofFIG. 4 that schematically illustrates the composition of the first electrode subsequent to an annealing process; and -
FIG. 6 is a cross-sectional schematic diagram of a DRAM device according to one embodiment of the present invention, wherein the DRAM device comprises the capacitor ofFIG. 1 . - The illustrated embodiment of the present invention comprises a miniaturized capacitor structure having improved operating characteristics and methods for providing the same. In particular, the capacitor structure is provided with electrodes having increased charge carrier concentrations adjacent an insulating layer such that problems associated with carrier depletion within the electrodes are reduced. Consequently, the capacitor structure is provided with an increased capacitance that is more stable in response to a changing voltage applied between the electrodes.
- Improved capacitors formed according to the methods of the illustrated embodiment are particularly useful in the manufacture of DRAM devices. It should be understood, however, that the methods of providing improved capacitors according to the present invention could be used in any application or structure in which it is desirable to include miniaturized capacitors having stable capacitance. Furthermore, the methods of the present invention are particularly well-suited for providing improved capacitors on or above a semiconductor substrate or substrate assembly, referred to herein generally as “substrate,” used in forming integrated circuits, such as a silicon wafer, with or without layers or structures formed thereon. It is to be understood that the methods of the present invention are not limited to deposition on silicon wafers; rather, other types of wafers (e.g., gallium arsenide, etc.) can be used as well. Moreover, the capacitors provided by the methods of the present invention are not limited to any particular geometrical configuration. For example, the capacitors described hereinbelow can have parallel planar electrodes, trench-type electrodes, or cylindrically shaped electrodes. Thus, the skilled artisan will find application for the processes and materials discussed below for any of a number of capacitor configurations.
- Reference will now be made to the drawings wherein like numerals refer to like parts throughout.
FIG. 1 illustrates acapacitor 30 in accordance with one embodiment of the present invention andFIG. 2 illustrates a method of providing the same. The capacitor comprises first andsecond conducting electrodes upper electrodes capacitor 30 further comprises an insulatinglayer 36 interposed between theelectrodes capacitor 30 has a capacitance that substantially depends on the surface area of theelectrodes electrodes layer 36. At least one of the first andsecond electrodes layer 36 comprises any of a number of known high-κ insulating dielectrics such as silicon nitride or Ta2O5. - In one embodiment, the
first electrode 32 comprises abulk layer 40 of polysilicon and a richly doped and relativelythin interface layer 42 extending from thebulk layer 40. Theinterface layer 42 is interposed between thebulk layer 40 and the insulatinglayer 36 in a substantially flush manner. Theinterface layer 42 is heavily doped so that the depletion region of thefirst electrode 32 caused by the removal of mobile charge carriers from theelectrode 32 is confined within thethin interface layer 42 under normal operating conditions. For example, in one embodiment, theinterface layer 42 of the first electrode has a thickness of 15 Å and a doping concentration of 1×1021 Atoms/cm3 so that the thickness of the depletion region of theelectrode 32 is less than 5 Å in response to an applied voltage that varies within a range of −3V-3V. In one embodiment, thebulk layer 40 has a thickness of 350 Å and a doping concentration of 4×1020 Atoms/cm3. - Preferably, the
bulk region 40 of theelectrode 32 comprises Hemi-Spherical Grained (HSG) polysilicon and theinterface layer 42 is conformally deposited thereon so that theelectrode 32 has an effective surface area greater than that of a planar surface. Furthermore, the dopant atoms of thefirst electrode 32 are preferably selected from the pentavalent elements, such as phosphorus, so that the mobile charge carriers of thefirst electrode 32 are electrons. However, it will be appreciated that, in another embodiment, the interface layer could be deposited during formation of theHSG bulk layer 40 and the dopant atoms could be selected from trivalent atoms so that the mobile charge carriers are holes. - As indicated in
FIG. 2 , the method of forming thecapacitor 30 ofFIG. 1 comprises, in astate 100, first forming thefirst electrode 32 having the richly dopedinterface layer 42 so as to reduce the severity of the depletion effect. The method of forming thefirst electrode 32 will be described in greater detail below. The method of forming thecapacitor 30 further comprises, in astate 102, depositing the insulatinglayer 36 adjacent the first electrode in a well known manner and then, in astate 104, depositing thesecond electrode 34 adjacent the insulatinglayer 36. In one embodiment, thesecond electrode 34 is formed in a well known manner. However, in other embodiments, it will be appreciated that thesecond electrode 34 could comprise a semiconductor material and it could be provided with a similar richly doped interface layer adjacent the insulatinglayer 36 using the methods described hereinbelow so as to reduce carrier depletion within thesecond electrode 34. - Reference will now be made to
FIGS. 3-5 which illustrate the preferred method of forming thefirst electrode 32 of thecapacitor 30 ofFIG. 1 . The method comprises, instate 110, forming thebulk layer 40 of thefirst electrode 32 of doped semiconductor material using any of a number of known deposition methods. For example, U.S. Pat. No. 5,759,262, U.S. Pat. No. 5,882,979, U.S. Pat. No. 5,933,727, and U.S. Pat. No. 6,027,970, which are incorporated herein by reference in their entirety, disclose various acceptable methods of forming thebulk layer 40 of HSG silicon above a semiconductor substrate. However, it will be appreciated that thebulk layer 40 could be formed with a non-roughened surface using any of a number of known deposition processes, such as chemical vapor deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or the like, without departing from the spirit of the present invention. - After the
bulk layer 40 is formed and before any subsequent layers are deposited thereon, an exposedsurface 44 of thebulk layer 40 includes a plurality of bonding sites that are capable of bonding with other atoms. The bonding sites correspond to the dangling bonds of Si atoms disposed adjacent the edge of the crystal lattice of thebulk layer 40. These bonding sites can be detrimental if they bond with O2 to form a layer of insulating SiO2 on thesurface 44 of thebulk layer 40 since the added layer of SiO2 has a relatively small dielectric constant and, thus, contributes to thecapacitor 30 having a reduced capacitance. - Typically, the bonding sites of a silicon electrode are passivated by annealing the electrode in a nitrogen or NH3 ambient so as to form a layer of SixNy instead of SiO2. Because SixNy has a larger dielectric constant, its effect on the capacitance is reduced. However, this usually requires exposing the electrode to relatively high temperatures.
- In contrast to the prior art, the method of forming the
first electrode 32 of the illustrated embodiment utilizes the bonding sites of thebulk layer 40 to increase the doping concentration of thefirst electrode 32. In particular, as shown inFIG. 3 , the method of forming thefirst electrode 32 further comprises, in astate 112, depositing an adhesive layer 46 (FIG. 4 ) having a plurality of adhesive molecules over thebulk layer 40 so that a substantial portion of the adhesive molecules bonds to the bonding sites of thebulk layer 40. As will be described in greater detail below, the purpose of the adhesive layer is to attract and capture dopant atoms with relatively high affinity so that the dopant atoms are disposed substantially near the adhesive layer. - As shown in
FIG. 4 , in the preferred embodiment, theadhesive layer 46 comprises a plurality of hexamethldisilazane (HMDS)molecules 50. EachHMDS molecule 50 comprises anitrogen atom 52 which is capable of bonding to aSi bonding site 54 of thebulk layer 40 of thefirst electrode 32. EachHMDS molecule 50 further comprises first andsecond silicon atoms same nitrogen atom 52. Furthermore, corresponding to each of thesilicon atoms HMDS molecule 50 comprises first, second, and third CH3 methyl groups 60, 62 and 64 that chemically bond to each of thesilicon atoms - The HMDS
adhesive layer 46 can be deposited using any of a number of conventional deposition processes. Preferably, thelayer 46 is deposited using LPCVD with a pressure of 100 mTorr and a temperature of 150° C. Furthermore, thelayer 46 is preferably deposited so that it conformally covers the exposedsurface 44 of thebulk layer 40. In one embodiment, a substantial portion of theHMDS molecules 50 are bonded directly to thebonding sites 54 of thebulk layer 40 disposed adjacent thesurface 44 of thebulk layer 40 so that theadhesive layer 46 has a thickness approximately equal to the diameter of theHMDS molecule 50. - As shown in
FIG. 3 , the method of forming thefirst electrode 32 further comprises, in astate 114, doping theadhesive layer 46 so as to transform theadhesive layer 46 into theinterface layer 42 ofFIG. 1 . In one embodiment, doping theadhesive layer 46 comprises annealing theadhesive layer 46 in a phosphorus ambient. In particular, theadhesive layer 46 is annealed in a phosphine ambient (PH3) so as to modify the composition of thelayer 46. As a result, a substantial portion of the CH3 methyl groups 60, 62 and 64 of the HMDS layer ofFIG. 4 are replaced by PH3 molecules from the ambient as shown inFIG. 5 . Since each HMDS molecule includes six CH3 methyl groups, each HMDS molecule can accommodate up to six PH3 molecules 66 each having a phosphorus atom disposed therein that contributes to the doping concentration of theinterface layer 42. Thus, theinterface layer 42 can be doped with a relatively large concentration of phosphorus dopant atoms which substantially inhibits the depletion region of thefirst electrode 32 from extending beyond theinterface layer 42 into thebulk layer 40. In one embodiment, theHMDS layer 46 is annealed in the PH3 ambient at a temperature between 350° C. and 800° C. As a result, theinterface layer 42 is provided with a concentration of phosphorus atoms that exceeds approximately 5×1020 Atoms/cm3. - As a result of depositing the
adhesive layer 46 over thebulk layer 40, in thestate 112, a substantial portion of thebonding sites 54 of thebulk layer 40 are no longer active and, thus, are not likely to bond with O2 atoms to form capacitance reducing SiO2. However, it is possible that Si bonding sites 68 within theinterface layer 42 could develop as a result of stripped CH3 methyl groups not being replaced by PH3 molecules during the annealing process. However, as will be described in greater detail below, the remaining dangling Si bonds of thelower electrode 32 can be substantially reduced without exposing thelower electrode 32 to the relatively high temperature passivation processes required in the prior art. - As shown in
FIG. 3 , the method of forming thelower electrode 32 further comprises, in astate 116, passivating the interface layer 43 so as to reduce the number of dangling Si bonding sites disposed therein. Preferably, theinterface layer 42 is exposed to an ambient, such as NH3, that comprises nitrogen atoms so that nitrogen atoms from the ambient are attracted to the Si bonding sites 68 of the interface layer to form SixNy. Advantageously, the activation energy required to form such bonds is less than that which is required to form SixNy over a conventional polysilicon surface. Thus, the layer can be passivated at a reduced temperature resulting in less diffusion. - In one embodiment, passivating the
interface layer 42 comprises exposing theinterface layer 42 to an NH3 ambient having a pressure approximately equal to 760 Torr and a temperature approximately equal to 800° C. In comparison, prior art passivation methods require exposing the device to temperatures above 850° C. - Reference will now be made to
FIG. 6 which illustrates anexemplary memory cell 70 of a DRAM device that includes thecapacitor 30 ofFIG. 1 . A plurality oftransistor gate electrodes 72 overlie asubstrate 74, adjacent transistoractive areas 76 within thesubstrate 74. It will be understood that several transistors are formed across a memory array within a DRAM circuit or chip.Field oxide elements 78 isolate theactive areas 76 of different transistors. An insulating layer is shown covering thegate electrodes 72. Aconductive contact 82, is shown extending through the insulatinglayer 80 to electrically contact anactive area 76 betweengate electrodes 72. Abarrier layer 84 is formed over theconductive contact 82 and astructural layer 86 is then formed over the insulating layer and abarrier layer 32. Preferably, thestructural layer 86 is selectively etchable relative to the underlying insulatinglayer 80. The surface area and, thus, the capacitance of thecapacitor 30 of thememory cell 70 is influenced by the thickness of thestructural layer 86. For the illustrated circuit, using 0.25 μm resolution, thestructural layer 86 preferably has a thickness of greater than about 0.4 μm, more preferably between about 0.4 μm and 2.0 μm. A via 88 is formed in thestructural layer 86 to expose theunderlying contact 82, and thelower electrode 32 of thecapacitor 30 ofFIG. 1 is disposed over thestructural layer 86 and into the via 88 to coat the inner surfaces of the via 88 and to make electrical contact with thecontact 82. The insulatinglayer 36 of thecapacitor 30 is deposited over thelower electrode 32 and thesecond electrode 34 is deposited over the insulatinglayer 36. - It will be appreciated that the
capacitor 30 of the present invention and the methods for providing the same provide many advantages. In particular, thefirst electrode 32 of thecapacitor 30 is provided with theinterface layer 42 having a relatively large concentration of dopant phosphorus atoms. Furthermore, since the phosphorus atoms are chemically bonded to theinterface layer 42, the phosphorus atoms are less likely to diffuse into thebulk layer 40. - Thus, the richly doped
interface layer 42 of thelower electrode 32 provides thelower electrode 32 with a more localized depletion region that is disposed adjacent the insulatinglayer 36 of thecapacitor 30. Furthermore, the extent of the depletion region is less effected by mobile charge carriers entering or exiting thelower electrode 32. Consequently, since reducing the extent of the depletion region reduces the effective distance between the charge on thelower electrode 32 and charge on theupper electrode 34, thecapacitor 30 is able to have an increased capacitance that is more stable in response to changes in the voltage applied between the electrodes. - Another advantage provided by the
capacitor 30 ofFIG. 1 is that theinterface layer 42 of thelower electrode 32 has a relatively large concentration of hydrogen atoms. In particular, hydrogen is provided by the remaining CH3 methyl groups and by the PH3 molecules inserted during the annealing process. The increased concentration of hydrogen in theinterface layer 42 serves as a barrier for preventing oxygen atoms from subsequently diffusing into thelower electrode 32 and, thereby inhibits the formation of capacitance robbing SiO2 within thelower electrode 32. Furthermore, the increased concentration of hydrogen in theinterface layer 42 can source H atoms to the insulatinglayer 36 so as to nullify dangling Si bonds within the insulatinglayer 36. In one embodiment, the hydrogen concentration is approximately greater than 1.5×1021 Atoms/cm3. - Yet another advantage provided by the
capacitor 30 of the present invention is that the richly dopedinterface layer 42 can be passivated at a reduced temperature. This is a result of the dangling Si bonds of the interface layer requiring a reduced activation energy to form SixNy when compared to the activation energy required to from SixNy on a typical polysilicon surface. Consequently, the passivation process of the present invention is less damaging to other components adjacent thecapacitor 30. - Although the preferred embodiment of the present invention has shown, described and pointed out the fundamental novel features of the invention as applied to this embodiment, it will be understood that various omissions, substitutions and changes in the form of the detail of the device illustrated may be made by those skilled in the art without departing from the spirit of the present invention. Consequently, the scope of the invention should not be limited to the foregoing description, but should be defined by the appended claims.
Claims (14)
1. A method of confining a depletion region in a capacitor, comprising:
forming a first electrode comprising a plurality of dopant atoms, said first electrode having a first surface comprising a plurality of bonding sites thereon; and
forming an adhesive layer on an upper surface of the first electrode, said adhesive layer comprising a plurality of adhesive molecules, wherein a substantial portion of the adhesive molecules bonds to the bonding sites on the first electrode, wherein said adhesive molecules capture dopant atoms in the first electrode so that the dopant atoms are disposed adjacent the adhesive layer so as to substantially confine a depletion region in the first electrode to an area adjacent the adhesive layer.
2. The method of claim 1 , wherein forming the adhesive layer comprises forming a layer having a chemical composition that is different from that of the first electrode.
3. The method of claim 2 , wherein forming the adhesive layer comprises forming a layer comprising HMDS.
4. The method of claim 1 , wherein the dopant atoms in said interface layer comprises a plurality of phosphorous atoms.
5. The method of claim 1 , wherein forming the first electrode comprises forming a bulk layer comprised of silicon.
6. The method of claim 5 , further comprising passivating the first electrode so as to inhibit the formation of silicon dioxide.
7. The method of claim 1 , wherein forming the adhesive layer comprises forming a layer having a plurality of CH3 methyl groups.
8. The method of claim 1 , wherein said bonding sites in the first electrode comprises a plurality of dangling bonds of Si atoms disposed adjacent the upper surface of the first electrode.
9. A method of forming a capacitor, comprising:
forming a first conducting electrode comprising a bulk layer having a first surface and a plurality of bonding sites thereon;
forming an interface layer on the first surface, said interface layer having a chemical composition different from said bulk layer, wherein said interface layer is chemically bonded to the bonding sites on the first surface;
chemically bonding a plurality of dopant atoms to said interface layer;
forming an insulating layer adjacent said interface layer; and
forming a second conducting electrode adjacent to said insulating layer.
10. The method of claim 9 , wherein forming the interface layer comprises depositing a plurality of CH3 methyl groups on the first surface of the bulk layer.
11. The method of claim 10 , wherein chemically bonding a plurality of dopant atoms to said interface layer comprises replacing a substantial portion of the plurality of CH3 methyl groups with PH3 molecules.
12. The method of claim 9 , wherein forming said interface layer comprises depositing a layer of HMDS material.
13. The method of claim 12 , further comprising annealing the layer of HMDS material in phosphine environment.
14. The method of claim 9 , wherein forming the first electrode comprises depositing HSG silicon a surface above a semiconductor wafer.
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US11/456,435 US20060246658A1 (en) | 2000-07-13 | 2006-07-10 | A capacitor electrode having an interface layer of different chemical composition formed on a bulk layer |
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US09/615,549 US6825522B1 (en) | 2000-07-13 | 2000-07-13 | Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer |
US10/931,511 US6964909B1 (en) | 2000-07-13 | 2004-09-01 | Method of forming a capacitor electrode having an interface layer of different chemical composition from a bulk layer |
US11/216,411 US7092233B2 (en) | 2000-07-13 | 2005-08-31 | Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer |
US11/456,435 US20060246658A1 (en) | 2000-07-13 | 2006-07-10 | A capacitor electrode having an interface layer of different chemical composition formed on a bulk layer |
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US10/931,511 Expired - Fee Related US6964909B1 (en) | 2000-07-13 | 2004-09-01 | Method of forming a capacitor electrode having an interface layer of different chemical composition from a bulk layer |
US11/216,411 Expired - Fee Related US7092233B2 (en) | 2000-07-13 | 2005-08-31 | Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer |
US11/456,435 Abandoned US20060246658A1 (en) | 2000-07-13 | 2006-07-10 | A capacitor electrode having an interface layer of different chemical composition formed on a bulk layer |
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US10/931,511 Expired - Fee Related US6964909B1 (en) | 2000-07-13 | 2004-09-01 | Method of forming a capacitor electrode having an interface layer of different chemical composition from a bulk layer |
US11/216,411 Expired - Fee Related US7092233B2 (en) | 2000-07-13 | 2005-08-31 | Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer |
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US20070288312A1 (en) * | 2006-03-31 | 2007-12-13 | Caliber Data, Inc. | Purchase-transaction-settled online consumer referral and reward service using real-time specific merchant sales information |
US8314474B2 (en) * | 2008-07-25 | 2012-11-20 | Ati Technologies Ulc | Under bump metallization for on-die capacitor |
US8273629B2 (en) * | 2009-03-19 | 2012-09-25 | International Business Machines Corporation | Through-gate implant for body dopant |
CN101996767B (en) * | 2009-08-10 | 2013-03-13 | 小岛压力加工工业株式会社 | Film capacitor and method of producing the same |
US8416609B2 (en) | 2010-02-15 | 2013-04-09 | Micron Technology, Inc. | Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems |
CN111785614B (en) * | 2020-06-18 | 2022-04-12 | 上海空间电源研究所 | Bonding structure capable of reducing voltage loss and preparation method thereof |
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US7092233B2 (en) | 2006-08-15 |
US6964909B1 (en) | 2005-11-15 |
US6825522B1 (en) | 2004-11-30 |
US20060007631A1 (en) | 2006-01-12 |
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