CN112993006A - 一种终端结构、其制作方法及电子器件 - Google Patents

一种终端结构、其制作方法及电子器件 Download PDF

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CN112993006A
CN112993006A CN201911276730.3A CN201911276730A CN112993006A CN 112993006 A CN112993006 A CN 112993006A CN 201911276730 A CN201911276730 A CN 201911276730A CN 112993006 A CN112993006 A CN 112993006A
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field plate
substrate
terminal
conductive
groove
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CN112993006B (zh
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廖勇波
史波
曾丹
江伟
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Gree Electric Appliances Inc of Zhuhai
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Abstract

本申请涉及电力电子器件技术领域，特别涉及一种终端结构、其制作方法及电子器件，其中，终端结构包括衬底，衬底具有主结原胞区和终端区，终端区包括靠近主结原胞区的过渡区和位于过渡区远离主结原胞区一侧的截止环；其中，衬底在位于过渡区与截止环之间的部位具有至少一个沟槽，终端区内形成有电容场板，电容场板覆盖各沟槽的侧面。本申请公开的终端结构，能够降低终端结构的面积占比，从而降低芯片的制造成本。

Description

一种终端结构、其制作方法及电子器件
技术领域
本申请涉及电力电子器件技术领域，特别涉及一种终端结构、其制作方法及电子器件。
背景技术
随着战略性新兴产业的崛起，电力电子器件及装置在风能、太阳能、热泵、水电、新能源设备等先进制造业中将发挥重要作用。尤其是在新能源革命以及下游电力电子装置行业需求高速发展的拉动下，电力电子器件产业将迎来发展黄金期。
目前，MOSFET(金属-氧化物半导体场效应晶体管)和IGBT(绝缘栅双极型晶体管)作为电力电子器件市场的主力军，其具备高电压能力的一个重要前提条件就是具有合适优良的终端结构。
目前电力电子器件具有的终端结构主要有：场板结构、场限环结构、场限环结合场板结构、结终端延伸结构和横向变掺杂结构，其中，广泛用于中高压(2500V及其以上)的IGBT终端保护结构的主要是场限环机构和结终端延伸结构。但是，传统的场限环结构存在以下不足之处：由于场限环宽度较宽，面积占芯片总面积的比例较大，增加芯片的制造成本。
发明内容
针对于上述问题，本发明提供了一种终端结构、其制作工艺及电子器件，能够有效降低终端结构的面积占比，降低芯片的制造成本。
为了达到上述目的，本发明提供了一种终端结构，包括衬底，所述衬底具有主结原胞区和终端区，所述终端区包括靠近所述主结原胞区的过渡区和位于所述过渡区远离所述主结原胞区一侧的截止环；其中，所述衬底在位于所述过渡区与所述截止环之间的部位具有至少一个沟槽，且所述终端区内形成有电容场板，所述电容场板覆盖各所述沟槽的侧面。
上述终端结构，终端区具有至少一个沟槽，并在每一个沟槽的侧壁形成电容场板；由于多个沟槽相当于可以增加衬底的表面的宽度，就可在不增加衬底的实际宽度的前提下，通过在每一个沟槽的侧壁形成纵向的电容场板，来形成终端结构的保护结构，以提升器件的耐压能力，并节省了终端区的面积占比。
因此，本发明提供的终端结构，通过在衬底上形成至少一个沟槽，并在每一个沟槽的侧壁形成电容场板，能够降低终端结构的面积占比，从而降低芯片的制造成本。
优选地，所述电容场板还覆盖于各所述沟槽的底面的表面。
优选地，所述电容场板还覆盖于所述衬底与所述沟槽的开口方向相同的一侧、且位于所述沟槽之外的部位的表面。
优选地，所述电容场板包括至少两层导电场板，且每相邻两层所述导电场板之间具有绝缘介质层。
优选地，每相邻两层所述导电场板配合形成多个相互串联的电容场板。
优选地，每相邻三层导电场板中，中间的导电场板与前一层的导电场板配合形成的电容场板与中间的导电场板与后一层的导电场板配合形成的电容场板的至少一部分并联。
优选地，最靠近所述衬底的导电场板在位于每一个所述沟槽的底部的部位断开；和/或，最靠近所述衬底的导电场板在位于每相邻两个沟槽之间的部位断开。
优选地，所述截止环为位于所述终端区背离所述主结原胞区的一侧边缘的最外层的导电场板。
优选地，所述衬底与所述电容场板之间设有介质层，且所述介质层具有多个使得最靠近所述衬底的导电场板与所述衬底之间连接的开孔。
优选地，本发明还提供一种电子器件，包括如上述所述的终端结构。
优选地，本申请还提供一种终端结构的制作方法，包括：
在衬底上形成氧化层，并通过构图工艺对所述氧化层进行刻蚀以形成与终端区对应的至少一个沟槽；
在每一个所述沟槽的侧壁形成电容场板。
优选地，上述方法还包括：在各所述沟槽的底面形成电容场板。
优选地，上述方法还包括：在所述衬底与所述沟槽的开口方向相同的一侧、且位于所述沟槽之外的部位的表面形成电容场板。
附图说明
图1为本发明中的一种终端结构的结构示意图；
图2为本发明中的一种沟槽及导电场板的放大结构示意图；
图3a-3d为本发明中的一种终端结构的制作过程结构图。
图中：
1-衬底；2-主结原胞区；3-终端区；31-过渡区；32-截止环；33-沟槽；4-电容场板；41-导电场板；42-绝缘介质层；5-介质层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参考图1，本发明提供了一种终端结构，包括衬底1，衬底1具有主结原胞区2和终端区3，终端区3包括靠近主结原胞区2的过渡区31和位于过渡区31远离主结原胞区2一侧的截止环32；其中，衬底1在位于过渡区31与截止环32之间的部位具有至少一个沟槽33，且终端区3内形成有电容场板4，该电容场板4覆盖各沟槽33的侧面。
上述终端结构，终端区3内形成有电容场板4、过渡区31和截止环32之间的部位设置了至少一个沟槽33，其中，电容场板覆盖于各沟槽33的侧壁。通过设置多个沟槽33，可相当于增加衬底1的表面的宽度，并且在此基础上，通过在沟槽33的侧壁上形成纵向的电容场板4，以形成终端结构的保护结构，以提升器件的耐压能力，并节省了终端区的面积占比。
因此，上述终端结构，通过在衬底1上形成至少一个沟槽33，并在每一个沟槽33的侧壁形成电容场板4，能够降低终端结构的面积占比，从而降低芯片的制造成本。
进一步地，上述电容场板4还可覆盖各沟槽33的底面、以及衬底1位于沟槽33之外的部位的表面，以此来增加电容场板4的数量，进一步提升器件的耐压。
需要说明的是，本发明中的衬底1可以是N型衬底。
如图2所示，本发明中的终端结构中设有的电容场板4可以是多层电容场板4，即电容场板4包括至少两层导电场板41，且每相邻两层导电场板41之间具有绝缘介质层42，该电容场板4可调节附近硅的电势，从而提升器件的耐压。
进一步，现有的终端结构中，场限环结构及结终端延伸结构，极易受界面不稳定性和氧化层界面电荷的影响，影响器件的最终击穿电压和器件的可靠性，导致了终端结构耐压低，可靠性差。
针对于上述问题，继续参考图1和图2，本发明中的电容场板4可以是包括由每相邻两层导电场板41配合形成的多个相互串联的电容场板4，且当电容场板4包括三层及以上导电场板41时，每相邻三层导电场板41中，中间的导电场板41与前一层的导电场板41配合形成的电容场板4与中间的导电场板41与后一层的导电场板41配合形成的电容场板4的至少一部分之间并联。通过上述设置，通过设置多层、且每一层多个电容场板4，并根据电容的串并联的机理，可调节场板附近的硅的电势，从而优化硅的电场分布，从而优化提升器件的耐压。
具体地，为了每相邻两层导电场板41配合形成多个电容场板4，可将第一层形成于衬底1表面的导电场板41在位于每一个沟槽33底部的位置断开，或者在每相邻两个沟槽33之间的部位断开，或者既在每一个沟槽33底部的位置断开，又在每相邻两个沟槽33之间的部位断开。并且在后续制作第二层导电场板41、第三层导电场板41等时，根据实际的断开部位通过刻蚀工艺并使得第二层导电场板41、第三层导电场板41等在合适的部位断开，以形成每相邻两层导电场板41之间多个相互串联的多个电容场板4以及每相邻三层导电场板41中互相并联的多个电容场板4，以此来调节场板附近的硅的电势，从而优化硅的电场分布，优化提升器件的耐压。
进一步地，本发明中位于终端区3的截止环32可以是位于终端区3背离主结原胞区2的一侧最边上的且在外层的导电场板41。
进一步地，本发明中的终端结构，衬底1于第一层导电场板41之间还可以设置有一层介质层，且为了能够让导电场板41与硅接触以调节硅的电势，可在介质层上设置多个过孔以使得第一层导电场板41与硅接触。
基于同一发明思路，本发明还提供一种终端结构的制作方法：
S1：先在衬底1上生长一层氧化层，并通过构图工艺对氧化层进行刻蚀，以形成终端区3对应的至少一个沟槽33；
S2：在每一个沟槽33的侧壁形成至少一层电容场板4。
进一步地，上述方法中，还可包括在每一个沟槽33的底部以及衬底1在位于每两个沟槽33之间的部位的表面形成至少一层电容场板4，以增加电容场板4的数量，进一步提升器件的耐压。
具体地，以两层导电场板配合形成电容场板为例，来具体说明本申请中的一种终端结构的制作方法：
S101，如图3a所示，并如上述S1所述，形成沟槽33；
S102：如图3c所示，在衬底1上淀积第一层导电场板，并通过构图工艺对第一层导电场板进行刻蚀以使得该层导电场板在每一个沟槽33的底部的部位以及每相邻两个沟槽33之间的部位断开，以为形成多个电容场板4做准备；需要说明的是，该层导电场板的材料可以是多晶硅或者金属材料等；
S103：如图3d所示，在第一层导电场板上淀积一层绝缘介质层42，并通过构图工艺对该层绝缘介质层42进行刻蚀，使得该层绝缘介质层42在终端区3与其他区域连接的部分断开，以使得后续其他区域与芯片连接；
S104：在绝缘介质层42上淀积第二层导电场板，并通过构图工艺对该层导电场板进行刻蚀，以使得该层导电场板在位于每一个沟槽33与衬底1表面衔接的地方断开，以形成多个导电场板，并与前一层导电场板配合形成电容场板4，具体参见图1。
需要说明的是，本发明中的终端结构具有的主结原胞区2可以在制备终端区3的前两层导电场板41时同层制备，以此减少工艺程序，降低生产成本，或者也可单独制备。
且上述制作工艺中，位于终端区3的截止环32则是在步骤5完成后位于最外侧的第二层导电场板41。
需要说明的是，当上述电容场板4包括三层及以上的导电场板41时，可在制作完靠近衬底1的两层导电场板后，在第二层导电场板上继续制备一层绝缘介质层，然后在该层绝缘介质层上制备第三层导电场板，以此类推，完成最终的电容场板的制作。
进一步地，在上述制作方法中，如图3b所示，在S102的步骤中，在衬底1上淀积第一层导电场板前，还包括：在衬底1上形成一层介质层5，并通过构图工艺对该介质层5进行刻蚀以形成至少一个过孔，该过孔可用于使得第一层导电场板与衬底1连接。
基于同一发明思路，本发明还可提供一种电子器件，包括上述终端结构，由于上述终端结构不仅降低终端结构的面积占比，还提升了器件的耐压，优化了电场分布，因此，本申请中的电子器件不仅可降低生产成本，还可保证自身的可靠性。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (13)

1.一种终端结构，包括衬底，所述衬底具有主结原胞区和终端区，其特征在于，所述终端区包括靠近所述主结原胞区的过渡区和位于所述过渡区远离所述主结原胞区一侧的截止环；其中，所述衬底在位于所述过渡区与所述截止环之间的部位具有至少一个沟槽，且所述终端区内形成有电容场板，所述电容场板覆盖各所述沟槽的侧面。
2.根据权利要求1所述的终端结构，其特征在于，所述电容场板还覆盖于各所述沟槽的底面。
3.根据权利要求1所述的终端结构，其特征在于，所述电容场板还覆盖于所述衬底与所述沟槽的开口方向相同的一侧、且位于所述沟槽之外的部位的表面。
4.根据权利要求1所述的终端结构，其特征在于，所述电容场板包括至少两层导电场板，且每相邻两层所述导电场板之间具有绝缘介质层。
5.根据权利要求4所述的终端结构，其特征在于，每相邻两层所述导电场板配合形成多个相互串联的电容场板。
6.根据权利要求5所述的终端结构，其特征在于，每相邻三层导电场板中，中间的导电场板与前一层的导电场板配合形成的电容场板与中间的导电场板与后一层的导电场板配合形成的电容场板的至少一部分并联。
7.根据权利要求5所述的终端结构，其特征在于，最靠近所述衬底的导电场板在位于每一个所述沟槽的底部的部位断开；和/或，最靠近所述衬底的导电场板在位于每相邻两个沟槽之间的部位断开。
8.根据权利要求5所述的终端结构，其特征在于，所述截止环为位于所述终端区背离所述主结原胞区的一侧边缘的最外层的导电场板。
9.根据权利要求1所述的终端结构，其特征在于，所述衬底与所述电容场板之间设有介质层，且所述介质层具有至少一个使得所述电容场板与所述衬底之间连接的开孔。
10.一种电子器件，其特征在于，包括如权利要求1-9任一项所述的终端结构。
11.一种终端结构的制作方法，其特征在于，包括：
在衬底上形成氧化层，并通过构图工艺对所述氧化层进行刻蚀以形成与终端区对应的至少一个沟槽；
在各所述沟槽的侧壁形成电容场板。
12.根据权利要求11所述的终端结构的制作方法，其特征在于，还包括：在各所述沟槽的底面形成电容场板。
13.根据权利要求11所述的终端结构的制作方法，其特征在于，还包括：在所述衬底与所述沟槽的开口方向相同的一侧、且位于所述沟槽之外的部位的表面形成电容场板。
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