CN112909081A - Transverse power device - Google Patents
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- CN112909081A CN112909081A CN202110175348.4A CN202110175348A CN112909081A CN 112909081 A CN112909081 A CN 112909081A CN 202110175348 A CN202110175348 A CN 202110175348A CN 112909081 A CN112909081 A CN 112909081A
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- 230000005684 electric field Effects 0.000 abstract description 5
- 230000000779 depleting effect Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 238000009826 distribution Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000002028 premature Effects 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention belongs to the technical field of power semiconductors, and relates to a transverse power device. The invention is mainly characterized in that: the field plate structure on the surface of the drift region adopts a convex shape, and the length of the drift region is optimized. When the device is conducted in the forward direction, continuous electron accumulation layers are generated on the surfaces of the drift regions below the gate structure and the field plate structure to form an accumulation type transport mode so as to reduce the specific on-resistance of the device; when reverse blocking is carried out, a reverse biased PN junction in the field plate structure bears withstand voltage, and the field plate structure not only can assist in depleting the drift region to improve the doping concentration of the drift region and reduce the specific on-resistance of the device, but also can modulate the distribution of a transverse electric field to improve the withstand voltage. Compared with the traditional LDMOS, the high-voltage-resistant LDMOS has lower specific on-resistance while realizing high voltage resistance.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and relates to a transverse power device.
Background
Compared with a VDMOS (Vertical Double diffused MOS, Vertical Double diffused metal oxide semiconductor field effect transistor), the LDMOS has the characteristics of fast switching speed and easy integration, and is widely applied to power integrated circuits.
In a conventional LDMOS, there is a specific On-resistance (R)on,sp) Contradictory relationship with withstand Voltage (BV): ron,sp∝BV2.5It is referred to as the "silicon limit". By reducing the doping concentration of the drift region, the withstand voltage of the device can be improved by increasing the drift region, but the specific on-resistance of the device is increased at the same time, so that the power consumption is increased. To alleviate this contradiction, RESURF technology, super junction technology, and slot technology are common means. Both the resurf technology and the super junction technology essentially introduce a P-type region in the drift region to assist in depleting the N-type drift region to increase the doping concentration of the drift region and reduce Ron,sp. However, both of them cannot effectively reduce the length of the drift region, and the introduced P-type region may occupy the conductive path of the drift region, which is not favorable for reducing the device Ron,sp. The groove type technology can fold the drift region by introducing a medium groove structure in the drift region, thereby shortening the length of the drift region, and simultaneously the medium groove is used for assisting in depleting the drift region to improve the doping concentration of the drift region, thereby obviously reducing the R of the deviceon,sp. However, in the case of the trench technology, the super junction technology or the RESURF technology, the current is transported by drift of carriers in the neutral drift region in the forward conduction mode, and therefore R is the carrier transport modeon,spWill still be limited by the doping concentration of the drift region.
Disclosure of Invention
The present invention is directed to a lateral power device, which solves the above problems.
The technical scheme of the invention is as follows:
a transverse power device comprises a P substrate 1, an N drift region 2 and a field plate structure which are sequentially stacked from bottom to top along the vertical direction of the device;
along the transverse direction of the device, the surface of the N drift region 2 sequentially comprises a source electrode structure, a grid electrode structure and a drain electrode structure from one side to the other side; the field plate structure is positioned between the source electrode structure and the drain electrode structure;
the source electrode structure comprises a P-type well region 31, a P-type body contact region 5 and a first N-type heavily doped region 6; the P-type body contact region 5 and the first N-type heavily doped region 6 are in mutual contact and are arranged at one end, far away from the N drift region 2, of the upper layer of the P-type well region 31 in parallel, the first N-type heavily doped region 6 is arranged on one side, close to the N drift region 2, and source electrodes are led out of the upper surfaces of the P-type body contact region 5 and the first N-type heavily doped region 6 together;
the drain structure comprises an N-type buffer region 4 and a second N-type heavily doped region 7; the second N-type heavily doped region 7 is positioned on the upper surface of the N-type buffer region 4, and the leading-out end of the second N-type heavily doped region 7 is a drain electrode;
the field plate structure is characterized by comprising a first protruding part, a second protruding part and a plane part, wherein the first protruding part extends from the upper surface of the source electrode structure to the upper surface of the N drift region 2, and the first protruding part is a first medium layer 9 and a P well region 32 covering the first medium layer 9; the planar part is a first dielectric layer 9 and a P-type area 11 covering the first dielectric layer 9; the second protruding part extends to the P-type region 11 from the upper surface of the drain structure, the second protruding part is a first medium layer 9, and an N-type buffer region 13 and a P-type region 11 which cover the first medium layer 9, the N-type buffer region 13 is positioned between the P-type region 11 of the plane part and the P-type region 11 of the second protruding part, namely the N-type buffer region 13 penetrates through the P-type region 11 along the vertical direction to divide the P-type region into two parts, and a first P-type heavily doped region 16 is embedded in the upper layer of the P-type region 11 of the second protruding part, namely two sides of the first P-type heavily doped region 16 are surrounded by the P-type region 11 of the second protruding part; the convex part and the plane part are connected in the following way: the end of one side of the P-well region 32 is directly in contact with the P-type region 11 of the planar portion; the tail end of the N-type buffer region 13 is in contact with the P-type region 11 of the plane part, and an arc surface which is concave towards the direction of the source structure is formed, and the longitudinal width between the two ends of the arc surface is equal to the longitudinal width of the N-type buffer region 13; the tail end of the other side of the P-well region 32 covers part of the upper surface of the P-body contact region 5, the P-well region 32 between the P-body contact region 5 and the P-type region 11 is surrounded by the P-well region 31, so that the P-well region 32 is not in contact with the first N-type heavily doped region 6 and the N drift region 2, and the first N-type heavily doped region 6 and the N drift region 2 are isolated by the P-well region 31; the upper layer on the other side of the P-well region 32 is also provided with a second P-type heavily doped region 51, the second P-type heavily doped region 51 extends to the direction close to the P-type region 11 to exceed the edge of the P-type body contact region 5, and the transverse width of the part, exceeding the edge of the P-type body contact region 5, of the second P-type heavily doped region 51 is smaller than the transverse width of the first N-type heavily doped region 6; the second convex part is positioned on the upper surface of the N-type buffer region 4, and the N-type buffer region 4 also isolates the plane part from the second N-type heavily doped region 7, so that the second convex part, the plane part and the second N-type heavily doped region 7 are all spaced;
the gate structure is a planar gate structure, the planar gate structure is positioned on the upper surface of the N drift region 2 between the first dielectric layer 9 and the first N-type heavily doped region 6, and comprises a gate dielectric layer 8 and a conductive material 17 covering the upper surface of the gate dielectric layer 8; the planar gate structure extends towards two sides along the transverse direction of the device, covers part of the upper surface of the first N-type heavily doped region 6 and the upper surface of the P-type region 11, and covers the P-well region 32 along the longitudinal direction, but a space is reserved between the planar gate structure and the second P-type heavily doped region 51, and the common leading-out end of the conductive material 17 and the upper surface of the second P-type heavily doped region 51 is a gate electrode; the longitudinal direction refers to a third dimension direction perpendicular to both the device vertical direction and the device lateral direction.
Furthermore, the P-type region 11 of the planar portion is doped in a step from high to low in the direction from the source structure to the drain structure.
Compared with the traditional LDMOS structure, the invention has the advantages that the size of the device is favorably reduced by introducing the source-drain end protruding type field plate structure, and an accumulation type transport mode is formed during conduction to reduce Ron,spAnd the voltage endurance capability of the device is improved.
Drawings
FIG. 1 is a schematic diagram of the three-dimensional structure of a half-cell in example 1;
FIG. 2 is a top view of a full cell with the gate structure removed according to example 1;
FIG. 3 is a top view of a full cell with gate removal structure of example 2;
fig. 4 is a top view of a full cell with the gate structure removed according to example 3.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
example 1
As shown in fig. 1 and 2, the lateral power device of this embodiment includes a P-substrate 1, an N-drift region 2, and a field plate structure stacked in sequence from bottom to top along a vertical direction of the device;
along the transverse direction of the device, the surface of the N drift region 2 sequentially comprises a source electrode structure, a grid electrode structure and a drain electrode structure from one side to the other side; the field plate structure is positioned between the source electrode structure and the drain electrode structure;
the source electrode structure comprises a P-type well region 31, a P-type body contact region 5 and a first N-type heavily doped region 6; the P-type body contact region 5 and the first N-type heavily doped region 6 are in mutual contact and are arranged at one end, far away from the N drift region 2, of the upper layer of the P-type well region 31 in parallel, the first N-type heavily doped region 6 is arranged on one side, close to the N drift region 2, and source electrodes are led out of the upper surfaces of the P-type body contact region 5 and the first N-type heavily doped region 6 together;
the drain structure comprises an N-type buffer region 4 and a second N-type heavily doped region 7; the second N-type heavily doped region 7 is positioned on the upper surface of the N-type buffer region 4, and the leading-out end of the second N-type heavily doped region 7 is a drain electrode;
the field plate structure is composed of a first protruding portion, a second protruding portion and a plane portion, wherein the first protruding portion extends from the upper surface of the source electrode structure to the upper surface of the N drift region 2, and the first protruding portion is a first dielectric layer 9 and a P well region 32 covering the first dielectric layer 9; the planar part is a first dielectric layer 9 and a P-type area 11 covering the first dielectric layer 9; the second protruding part extends to the P-type region 11 from the upper surface of the drain structure, the second protruding part is a first medium layer 9, and an N-type buffer region 13 and a P-type region 11 which cover the first medium layer 9, the N-type buffer region 13 is positioned between the P-type region 11 of the plane part and the P-type region 11 of the second protruding part, namely the N-type buffer region 13 penetrates through the P-type region 11 along the vertical direction to divide the P-type region into two parts, and a first P-type heavily doped region 16 is embedded in the upper layer of the P-type region 11 of the second protruding part, namely two sides of the first P-type heavily doped region 16 are surrounded by the P-type region 11 of the second protruding part; the convex part and the plane part are connected in the following way: the end of one side of the P-well region 32 is directly in contact with the P-type region 11 of the planar portion; the tail end of the N-type buffer region 13 is in contact with the P-type region 11 of the plane part, and an arc surface which is concave towards the direction of the source structure is formed, and the longitudinal width between the two ends of the arc surface is equal to the longitudinal width of the N-type buffer region 13; the tail end of the other side of the P-well region 32 covers part of the upper surface of the P-body contact region 5, the P-well region 32 between the P-body contact region 5 and the P-type region 11 is surrounded by the P-well region 31, so that the P-well region 32 is not in contact with the first N-type heavily doped region 6 and the N drift region 2, and the first N-type heavily doped region 6 and the N drift region 2 are isolated by the P-well region 31; the upper layer on the other side of the P-well region 32 is also provided with a second P-type heavily doped region 51, the second P-type heavily doped region 51 extends to the direction close to the P-type region 11 to exceed the edge of the P-type body contact region 5, and the transverse width of the part, exceeding the edge of the P-type body contact region 5, of the second P-type heavily doped region 51 is smaller than the transverse width of the first N-type heavily doped region 6; the second convex part is positioned on the upper surface of the N-type buffer region 4, and the N-type buffer region 4 also isolates the plane part from the second N-type heavily doped region 7, so that the second convex part, the plane part and the second N-type heavily doped region 7 are all spaced;
the gate structure is a planar gate structure, the planar gate structure is positioned on the upper surface of the N drift region 2 between the first dielectric layer 9 and the first N-type heavily doped region 6, and comprises a gate dielectric layer 8 and a conductive material 17 covering the upper surface of the gate dielectric layer 8; the planar gate structure extends towards two sides along the transverse direction of the device, covers part of the upper surface of the first N-type heavily doped region 6 and the upper surface of the P-type region 11, and covers the P-well region 32 along the longitudinal direction, but a space is reserved between the planar gate structure and the second P-type heavily doped region 51, and the common leading-out end of the conductive material 17 and the upper surface of the second P-type heavily doped region 51 is a gate electrode; the longitudinal direction refers to a third dimension direction perpendicular to both the device vertical direction and the device lateral direction.
The working principle of the embodiment is as follows: the area used for connecting the electric potential in the field plate structure is arranged in the protruding part, so that the length of a drift region of the device can be effectively shortened, and the area utilization rate of the device is improved. When the device is conducted in the forward direction, continuous electron accumulation layers are generated on the surfaces of the drift regions below the gate structure and the field plate structure to form an accumulation type transport mode so as to reduce the specific on-resistance of the device; when reverse blocking is carried out, a reverse biased PN junction in the field plate structure bears withstand voltage, wherein the P-type region 11 not only assists in depleting the drift region to improve the doping concentration of the drift region and reduce the specific on-resistance of the device, but also modulates the distribution of a transverse electric field to improve the withstand voltage, so that the new device can have the characteristics of high withstand voltage and low specific on-resistance. The protruding parts at two ends of the source end of the field plate structure are respectively surrounded by the P well region 31 and the N-type buffer region 4 to form a chamfer region, so that electric field aggregation at the chamfer position can be relieved, and premature breakdown can be caused; in the aspect of process preparation, the P-well region 32, the second P-type heavily doped region 51/the first P-type heavily doped region 16 of the field plate structure can be manufactured with the same layout as the P-well region 31 and the P-type body contact region 5 of the source electrode structure, so that the manufacturing cost of the device is saved.
Therefore, compared with the traditional LDMOS structure, the invention can obtain smaller specific on-resistance while realizing high voltage resistance.
Example 2
Compared with embodiment 1, as shown in fig. 3, the P-type region 11 of the field plate structure in this example uses P-type step doping from high to low from the source end to the drain end, that is, the P-type region 11 of the field plate structure in this example is the second P-type heavily doped region 51, the P-well region 32, the P-type first-order doped region 111, the P-type second-order doped region 112, the N-type buffer region 13, and the first P-type heavily doped region 16 from the source end to the drain end along the lateral direction of the device. Compared with embodiment 1, the P-type region 11 on the field plate can better modulate the lateral electric field part of the device and improve the withstand voltage of the device when the reverse withstand voltage is applied.
Example 3
As shown in fig. 4, in comparison with embodiment 1, the N-type buffer region 13 in this example extends into the P-type region 11 toward the source end in the lateral direction and diffuses toward both ends in the longitudinal direction to surround the chamfered region of the convex portion.
Compared with embodiment 1, this case avoids the junction surface of the N-type buffer region 13 and the P-type region 11 appearing at the chamfer of the protruding portion, and avoids the premature breakdown of the PN junction on the field plate due to the electric field accumulation at the chamfer when the device is in reverse voltage withstanding, thereby improving the voltage withstanding capability of the device.
Claims (2)
1. A transverse power device comprises a P substrate (1), an N drift region (2) and a field plate structure which are sequentially stacked from bottom to top along the vertical direction of the device;
along the transverse direction of the device, the surface of the N drift region (2) sequentially comprises a source electrode structure, a grid electrode structure and a drain electrode structure from one side to the other side; the field plate structure is positioned between the source electrode structure and the drain electrode structure;
the source electrode structure comprises a P-type well region (31), a P-type body contact region (5) and a first N-type heavily doped region (6); the P-type body contact region (5) and the first N-type heavily doped region (6) are mutually contacted and are arranged at one end, far away from the N drift region (2), of the upper layer of the P-type well region (31), the first N-type heavily doped region (6) is arranged on one side close to the N drift region (2), and source electrodes are led out from the upper surfaces of the P-type body contact region (5) and the first N-type heavily doped region (6) together;
the drain electrode structure comprises an N-type buffer region (4) and a second N-type heavily doped region (7); the second N-type heavily doped region (7) is positioned on the upper surface of the N-type buffer region (4), and the leading-out end of the second N-type heavily doped region (7) is a drain electrode;
the field plate structure is characterized by comprising a first protruding portion, a second protruding portion and a plane portion, wherein the first protruding portion extends from the upper surface of the source electrode structure to the upper surface of the N drift region (2), and the first protruding portion is a first dielectric layer (9) and a P well region (32) covering the first dielectric layer (9); the planar part is a first dielectric layer (9) and a P-type area (11) covering the first dielectric layer (9); the second protruding portion extends to the P-type region (11) from the upper surface of the drain structure, the second protruding portion is a first medium layer (9), and an N-type buffer region (13) and a P-type region (11) which cover the first medium layer (9), the N-type buffer region (13) is located between the P-type region (11) of the plane portion and the P-type region (11) of the second protruding portion, namely the N-type buffer region (13) penetrates through the P-type region (11) along the vertical direction to divide the P-type region into two parts, a first P-type heavily doped region (16) is embedded in the upper layer of the P-type region (11) of the second protruding portion, and two sides of the first P-type heavily doped region (16) are surrounded by the P-type region (11) of the second protruding portion; the convex part and the plane part are connected in the following way: the end of one side of the P well region (32) is directly contacted with the P type region (11) of the plane part; the tail end of the N-type buffer region (13) is in contact with the P-type region (11) of the plane part, an arc surface which is concave towards the direction of the source structure is formed, and the longitudinal width between the two ends of the arc surface is equal to the longitudinal width of the N-type buffer region (13); the tail end of the other side of the P well region (32) covers part of the upper surface of the P body contact region (5), the P well region (32) between the P body contact region (5) and the P type region (11) is surrounded by the P well region (31), so that the P well region (32) is not in contact with the first N type heavily doped region (6) and the N drift region (2), and the P well region (31) also isolates the first N type heavily doped region (6) from the N drift region (2); the upper layer on the other side of the P well region (32) is also provided with a second P type heavily doped region (51), the second P type heavily doped region (51) extends to the direction close to the P type region (11) to exceed the edge of the P type body contact region (5), and the transverse width of the second P type heavily doped region (51) exceeding the edge of the P type body contact region (5) is smaller than the transverse width of the first N type heavily doped region (6); the second convex part is positioned on the upper surface of the N-type buffer region (4), and the N-type buffer region (4) also isolates the plane part from the second N-type heavily doped region (7), so that the second convex part, the plane part and the second N-type heavily doped region (7) are spaced;
the gate structure is a planar gate structure, the planar gate structure is positioned on the upper surface of the N drift region (2) between the first dielectric layer (9) and the first N-type heavily doped region (6), and comprises a gate dielectric layer (8) and a conductive material (17) covering the upper surface of the gate dielectric layer (8); the planar gate structure extends towards two sides along the transverse direction of the device, covers part of the upper surface of the first N-type heavily doped region (6) and the upper surface of the P-type region (11), and covers the P well region (32) along the longitudinal direction, but a gap is reserved between the planar gate structure and the second P-type heavily doped region (51), and the common leading-out end of the conductive material (17) and the upper surface of the second P-type heavily doped region (51) is a gate electrode; the longitudinal direction refers to a third dimension direction perpendicular to both the device vertical direction and the device lateral direction.
2. A lateral power device according to claim 1, wherein the P-type region (11) of the planar portion is doped in a step from high to low in a direction from the source structure to the drain structure.
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| CN115064582A (en) * | 2022-08-08 | 2022-09-16 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090008675A1 (en) * | 2005-10-12 | 2009-01-08 | Fuji Electric Holdings Co., Ltd. | Soi trench lateral igbt |
| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
| US20110101454A1 (en) * | 2009-11-05 | 2011-05-05 | Hisao Ichijo | Semiconductor device and method for producing the same |
| CN103325835A (en) * | 2013-05-28 | 2013-09-25 | 电子科技大学 | SOI power LDMOS device provided with junction type field plate |
| CN104201206A (en) * | 2014-08-29 | 2014-12-10 | 电子科技大学 | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device |
| CN105047702A (en) * | 2015-07-13 | 2015-11-11 | 电子科技大学 | Manufacturing method of LDMOS device |
| US20150333170A1 (en) * | 2012-12-20 | 2015-11-19 | University Of Electronic Science And Technology Of China | Lateral power device having low specific on-resistance and using high-dielectric constant socket structure and manufacturing method therefor |
| CN105633137A (en) * | 2016-01-08 | 2016-06-01 | 电子科技大学 | Trench gate power MOSFET (metal oxide semiconductor filed-effect transistor) device |
| CN105789314A (en) * | 2016-03-18 | 2016-07-20 | 电子科技大学 | Transverse SOI power LDMOS |
| CN107452805A (en) * | 2017-07-18 | 2017-12-08 | 电子科技大学 | A kind of LDMOS device with low on-resistance high withstand voltage |
| CN108649070A (en) * | 2018-05-14 | 2018-10-12 | 电子科技大学 | A kind of GaN hetero-junctions conductance modulation field-effect tube |
| CN109192778A (en) * | 2018-08-01 | 2019-01-11 | 长沙理工大学 | A kind of separate gate slot type power device with double longitudinal field plates |
| US20190288112A1 (en) * | 2018-03-19 | 2019-09-19 | Macronix International Co., Ltd. | High-voltage transistor devices with two-step field plate structures |
-
2021
- 2021-02-09 CN CN202110175348.4A patent/CN112909081B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090008675A1 (en) * | 2005-10-12 | 2009-01-08 | Fuji Electric Holdings Co., Ltd. | Soi trench lateral igbt |
| US20110101454A1 (en) * | 2009-11-05 | 2011-05-05 | Hisao Ichijo | Semiconductor device and method for producing the same |
| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
| US20150333170A1 (en) * | 2012-12-20 | 2015-11-19 | University Of Electronic Science And Technology Of China | Lateral power device having low specific on-resistance and using high-dielectric constant socket structure and manufacturing method therefor |
| CN103325835A (en) * | 2013-05-28 | 2013-09-25 | 电子科技大学 | SOI power LDMOS device provided with junction type field plate |
| CN104201206A (en) * | 2014-08-29 | 2014-12-10 | 电子科技大学 | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device |
| CN105047702A (en) * | 2015-07-13 | 2015-11-11 | 电子科技大学 | Manufacturing method of LDMOS device |
| CN105633137A (en) * | 2016-01-08 | 2016-06-01 | 电子科技大学 | Trench gate power MOSFET (metal oxide semiconductor filed-effect transistor) device |
| CN105789314A (en) * | 2016-03-18 | 2016-07-20 | 电子科技大学 | Transverse SOI power LDMOS |
| CN107452805A (en) * | 2017-07-18 | 2017-12-08 | 电子科技大学 | A kind of LDMOS device with low on-resistance high withstand voltage |
| US20190288112A1 (en) * | 2018-03-19 | 2019-09-19 | Macronix International Co., Ltd. | High-voltage transistor devices with two-step field plate structures |
| CN108649070A (en) * | 2018-05-14 | 2018-10-12 | 电子科技大学 | A kind of GaN hetero-junctions conductance modulation field-effect tube |
| CN109192778A (en) * | 2018-08-01 | 2019-01-11 | 长沙理工大学 | A kind of separate gate slot type power device with double longitudinal field plates |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115064582A (en) * | 2022-08-08 | 2022-09-16 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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