CN112820657B - 一种解决铝垫打线异常的方法 - Google Patents

一种解决铝垫打线异常的方法 Download PDF

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CN112820657B
CN112820657B CN202110007456.0A CN202110007456A CN112820657B CN 112820657 B CN112820657 B CN 112820657B CN 202110007456 A CN202110007456 A CN 202110007456A CN 112820657 B CN112820657 B CN 112820657B
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wire bonding
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aluminum pad
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CN112820657A (zh
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陈旭
吴庆才
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Suzhou Industrial Park Nano Industry Technology Research Institute Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明属于半导体封装技术领域，尤其涉及一种解决铝垫打线异常的方法。该方法具体为：在具有Al/Ti/TiN的膜层结构的半导体器件的封装程序中，先进行当层非结构区域金属膜层的刻蚀，然后进行钝化膜层的沉积，之后对钝化膜层及金属层进行刻蚀，再进行退火，Al层表面形成麻点，Al层上打线处理。本发明通过将退火工艺移至钝化膜层及金属层的刻蚀工艺后，此时由于Al层上的Ti/TiN膜层已被刻蚀干净，在退火后Al层表面会形成麻点，可正常打线。本发明从根源上消除了铝垫无麻点异常的现象，有效了提高铝垫的打线成功率。

Description

一种解决铝垫打线异常的方法
技术领域
本发明属于半导体封装技术领域，尤其涉及一种解决铝垫打线异常的方法。
背景技术
半导体封装程序是用来提供一种封装构造保护半导体芯片，使半导体芯片在通电
运作时能避免发生外力撞击、灰尘污染、受潮或氧化等问题，以便利用封装构造提升半导体芯片的使用可靠度及延长其使用寿命。在现有的半导体封装制造过程中，通常先取得半导体晶圆并对其进行晶圆测试，通过测试后的半导体晶圆会被切割成数个半导体芯片，而各半导体芯片随后被黏固在导线架或基板上，以进行打线结合程序。最后，再利用封胶材料包覆半导体芯片、导线以及导线架或基板的部分表面，如此即可大致完成半导体封装构造的半成品。
在镀制Al/Ti/TiN膜层结构的半导体器件时，在退火后，铝垫层常常会出现无麻点的情况，铝垫表面特别光滑，从而导致打线异常，影响封装效果，浪费时间和人力成本。
发明内容
本发明的目的在于提供一种解决铝垫打线异常的方法，通过将退火工艺移至Ti/TiN刻蚀工艺后，可以有效解决铝垫在退火后无麻点、不易打线的问题。
本发明提出了一种解决铝垫打线异常的方法，在具有Al/Ti/TiN的膜层结构的半导体器件的封装程序中，先进行当层非结构区域金属膜层的刻蚀，然后进行钝化膜层的沉积，之后对钝化膜层及金属层进行刻蚀，再进行退火，Al层表面形成麻点，Al层上打线处理。
本发明的有益效果在于：金属Al在退火时，会释放应力，晶粒间界扩散使得晶粒长大，晶粒间挤压而形成麻点。
在Al/Ti/TiN膜层结构中，退火后Ti与Al会形成合金，阻碍了Al的再结晶及应力释放，导致Al表面无麻点。并且形成的TiAl合金表面较光滑，当金属层比较薄时，不易打线。
本发明把退火工艺移至Ti/TiN刻蚀工艺后，由于Al层上的Ti/TiN膜层已被刻蚀干净，在退火后Al表面会形成麻点，可正常打线。本发明可以有效提高铝垫打线成功率，提高产品良率，节约成本。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，并可依照说明书的内容予以实施，以下以本发明的较佳实施例详细说明如后。
附图说明
图1为实施例1中Al层表面有麻点的照片。
图2为对比例1中Al层表面无麻点的照片。
具体实施方式
下面将结合附图对本发明的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
本实施例提供了一种解决铝垫打线异常的方法，具体为：在具有Al/Ti/TiN的膜层结构的半导体器件的封装程序中，先进行当层非结构区域金属膜层的刻蚀，然后进行钝化膜层的沉积，之后对钝化膜层及金属层进行刻蚀，再进行退火，Al层表面形成麻点，Al层上打线处理。参见图1，在退火后，Al层表面有麻点。
本发明通过将退火工艺移至Ti/TiN刻蚀工艺后，由于Al层上的Ti/TiN膜层已被刻蚀干净，在退火后Al层表面会形成麻点，可正常打线。本发明从根源上消除了铝垫无麻点异常的现象，有效了提高铝垫的打线成功率。
对比例1
本对比例提供了一种传统的半导体器件的封装程序，具体为：在具有Al/Ti/TiN的膜层结构的半导体器件的封装程序中，先进行当层非结构区域金属膜层的刻蚀，然后进行退火，再进行钝化膜层的沉积，之后对钝化膜层及金属层的刻蚀，最后制备成品。参见图2，该半导体器件在退火后，Al层表面光滑无麻点，不易打线。
以上所述实施例仅表达了本发明的实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。
因此，本发明专利的保护范围应以所附权利要求为准。

Claims (1)

1.一种解决铝垫打线异常的方法，其特征在于，在具有Al/Ti/TiN的膜层结构的半导体器件的封装程序中，先进行当层非结构区域金属膜层的刻蚀，然后进行钝化膜层的沉积，之后对钝化膜层及金属层进行刻蚀，以完全去除Al层上的Ti/TiN膜层，再进行退火，通过金属Al在退火时的应力释放和晶粒间界扩散，使得晶粒增大和晶粒间发生挤压，Al层表面形成麻点，Al层上打线处理。
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