CN1125484C - 在半导体芯片上形成保护层的方法 - Google Patents

在半导体芯片上形成保护层的方法 Download PDF

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CN1125484C
CN1125484C CN98106228A CN98106228A CN1125484C CN 1125484 C CN1125484 C CN 1125484C CN 98106228 A CN98106228 A CN 98106228A CN 98106228 A CN98106228 A CN 98106228A CN 1125484 C CN1125484 C CN 1125484C
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layer
manufacture process
reacting gas
oxide layer
silicon nitride
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张良冬
郑香平
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Vanguard International Semiconductor Corp
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Abstract

一种在半导体芯片上形成保护层的方法，该芯片具有一形成于其上做为绝缘层的介电层，该方法至少包含：在所述介电层上形成一导电层；在导电层上形成一光刻胶，以定义内连线的图案；以所述光刻胶做为蚀刻的掩膜，以蚀刻所述导电层，以形成内连线；用等离子体进行预处理，去除所述内连线表面上的有机金属化合物，反应气体为NH3以及N2O；在所述内连线以及所述介电层上形成一氧化层，以做为缓冲层；及在所述氧化层上形成氮化硅层。根据本发明，可以有效地消除保护层中的针孔(pin holes)。

Description

在半导体芯片上形成保护层的方法
技术领域
本发明涉及一种集成电路制造过程中形成保护层的方法，特别是涉及一种去除氮化硅保护层中针孔的方法。
背景技术
在集成电路制造过程中，形成在元件间做为绝缘的隔离区域起十分重要的作用。一般在制造集成电路时，必须在形成元件之前将隔离区制作完毕，然后再进行后续的制造过程，内连线的制作也是一项十分重要的工作，其提供元件间信号的传递路径。通常，内连线利用金属或合金做为内连线材料。
目前，铝或铝合金被广泛地应用于集成电路中做为连线。在多重内连线结构中，通常利用铝合金来防止尖峰现象(spiking)的产生。一般在铝金属中加入少量的铜来防止所谓的电迁移现象(electromigration)，大部分铝金属利用磁控DC溅镀法来沉积，其他经常应用于内连线的金属还有钨、钛等金属。
通常，在完成内连线制作之后，会有一介电层形成于金属内连线之上做为绝缘层，形成于多重内连线最上层的介电层通常称做保护层(passivation)，保护层除了做为绝缘层之外还具有防止水气穿透的功能。然而，传统的制造过程常常会在保护层之中产生针孔。
发明概述
本发明的一个目的是提供一种集成电路中多重内连线保护层的制造过程。
本发明的另一目的是提供一种去除氮化硅保护层中针孔的方法。
根据本发明，提供一种在半导体芯片上形成保护层的方法，该芯片具有一形成于其上做为绝缘层的介电层，该方法至少包含：在所述介电层上形成一导电层；在导电层上形成一光刻胶，以定义内连线的图案；以所述光刻胶做为蚀刻的掩膜，以蚀刻所述导电层，以形成内连线；用等离子体进行预处理，去除所述内连线表面上的有机金属化合物，反应气体为NH3以及N2O；在所述内连线以及所述介电层上形成一氧化层，以做为缓冲层；及在所述氧化层上形成氮化硅层。
本发明首先在一介电层之上形成一金属层，金属层做为电传递的内连线，金属层可以为铝、钛、钨、铜、金、铂或合金。随后，一光刻胶形成于金属层之上，用以定义内连线的图案，然后以此光刻胶做为蚀刻的掩膜以将金属层蚀刻形成内连线。完成内连线制作后，将上述光刻胶去除。施以预处理制造过程，以去除有机金属，此预处理制造过程采用等离子体轰击方式来去除该有机金属。反应气体为NH3以及N2O，制造过程的气压约为2.5乇(torr，1乇＝133Pa)，射频(radio freguency)范围内等离子体的功率约为100瓦(瓦特)，极板间距(susceptor spacing)约为1.14cm(450mils(密耳))，气体NH3以及N2O的流量分别为100sccm(标准立方厘米)以及1600sccm。接着，一薄的氧化层形成于上述金属层以及介电层之上，此氧化层做为缓冲层，用来降低金属层与后续氮化硅层之间的应力。制造过程的气压约为2.5乇，射频范围内淀积的功率约为240瓦，极板间距约为1.09cm(430mils)，反应气体N2O的流量为1600sccm，反应气体SiH4为90sccm。接着，氮化硅层形成氧化层之上，以做为保护层，氮化硅层可以用低压化学气相淀积法形成(lowpressure chemical vapor deposition)，或是用等离子体增强式化学气相淀积法(plasma enhance chemical vapor deposition)、高密度等离子体化学气相淀积法(high density plasma chemical vapor deposition)形成。制造过程的温度约为200至400℃，制造过程的气压约为3.35乇，淀积功率约为760瓦，极板间距(susceptor spacing)约为1.65cm(650mils)。反应气体为SiH4与NH3，气体NH3以及SiH4的流量分别为80sccm以及270sccm。利用本制造过程的制造过程参数将会有效地消除保护层中的针孔(pin holes)。
附图的简要说明
参照附图对本发明优选实施的详细描述，本发明的上述目的、优点和特征将变得更加明显，附图中：
图1为本发明制造过程中形成金属层的截面图；
图2为本发明制造过程中施以预处理制造过程的截面图；
图3为本发明制造过程中在金属层上形成氧化硅的截面图；和
图4为本发明制造过程中在氧化层上形成保护层的截面图。
具体实施方式
本发明揭示一种增进保护层品质的方法。本发明可以消除形成于保护层中的针孔，因此，本发明将提高集成电路制造过程的品质。本发明将详细说明如下。
如图1所示，一具有<100>晶向的P型或N型硅半导体晶片2上形成现有技术的半导体元件，接着，绝缘层以及内连线依所需要的设计而分别形成于晶片上。金属层6形成于介电层4之上，同理，金属层做为电传递的内连线，金属层可以为铝、钛、钨、铜、金、铂或合金。
随后，一光刻胶形成于金属层6上，用以定义内连线的图案，然后，以此光刻胶做为蚀刻的掩膜将金属层蚀刻形成内连线，此金属层6的厚度约为6000-9000埃(1埃＝10-10m)之间。完成内连线之制作后，将上述光刻胶去除。在形成内连线制造过程之中，经常会在内连线6以及介电层4的表面形成有机金属。
参阅图2，施以一预处理制造过程以去除上述有机金属。此预处理制造过程采用等离子体轰击方式来去除该有机金属，反应气体为NH3以及N2O，制造过程的气压约为2.5乇，射频(radio frequency)范围内等离子体的功率约为100瓦，极板间距(susceptor spacing)约为1.14cm(450mils)，气体NH3以及N2O的流量分别为100sccm以及1600sccm。
参阅图3，一薄的氧化层8接着形成于上述金属层6以及介电层4之上，此氧化层8做为缓冲层，用来降低金属层6与后续氮化硅层之间的应力。此氧化层8以二氧化硅组成，制造过程的气压约为2.5乇，射频范围内淀积的功率约为240瓦，极板间距(susceptor spacing)约为1.09cm(430mils)，反应气体N2O的流量为1600sccm，反应气体SiH4为90sccm，此淀积制造过程的温度约为200至400℃，氧化层8的厚度约为300至3000埃之间。
如图4所示，氮化硅层10接着形成于氧化层8之上，以做为保护层。氮化硅层10可以用低压化学气相淀积法形成(low pressure chemical vapordeposition)，或者用等离子体增强式化学气相淀积法(plasma enhance chemicalvapor deposition)、高密度等离子体化学气相淀积法(high density plasmachemical vapor deposition)形成，制造过程的温度约为200至400℃，制造过程的气压约为3.35乇，淀积的功率约为760瓦，极板间距约为1.65cm(650mils)，反应气体为SiH4与NH3，气体NH3以及SiH4的流量分别为80sccm以及270sccm。利用本制造过程的制造过程参数将会有效地消除保护层10中的针孔(pin holes)。
尽管对本发明以优选实施例进行了说明，而熟悉此领域技术人员可在不脱离本发明的精神范围内作一些更改修饰，其专利保护范围应由所附权利要求及其等同领域而定。

Claims (22)

1.一种在半导体芯片上形成保护层的方法，该芯片具有一形成于其上做为绝缘层的介电层，该方法至少包含：
在所述介电层上形成一导电层；
在导电层上形成一光刻胶，以定义内连线的图案；
以所述光刻胶做为蚀刻的掩膜，以蚀刻所述导电层，以形成内连线；
用等离子体进行预处理，去除所述内连线表面上的有机金属化合物，反应气体为NH3以及N2O；
在所述内连线以及所述介电层上形成一氧化层，以做为缓冲层；及
在所述氧化层上形成氮化硅层。
2.如权利要求1所述的方法，其中所述预处理过程的制造过程压力约为2.5乇。
3.如权利要求1所述的方法，其中所述预处理过程的制造过程功率约为100瓦。
4.如权利要求1所述的方法，其中所述预处理过程的反应气体N2O的流量约为1600sccm。
5.如权利要求1所述的方法，其中所述预处理过程的反应气体NH3的流量约为100sccm。
6.如权利要求1所述的方法，其中所述预处理过程的极板间距约为1.14cm。
7.如权利要求1所述的方法，其中所述氧化层以化学气相淀积法形成，反应气体为N2O与SiH4。
8.如权利要求7所述的方法，其中所述反应气体N2O流量约为1600sccm。
9.如权利要求7所述的方法，其中所述反应气体SiH4流量约为90sccm。
10.如权利要求7所述的方法，其中形成所述氧化层的制造过程功率约为240瓦。
11.如权利要求7所述的方法，其中形成所述氧化层的极板间距约为1.09cm。
12.如权利要求7所述的方法，其中形成所述氧化层的制造过程压力约为2.5乇。
13.如权利要求7所述的方法，其中形成所述氧化层的制造过程温度约为200至400℃。
14.如权利要求1所述的方法，其中所述氮化硅层可以利用低压化学气相淀积法、等离子体增强式化学气相淀积法以及高密度等离子体化学气相淀积法形成。
15.如权利要求14所述的方法，其中所述反应气体为SiH4与NH3。
16.如权利要求15所述的方法，其中所述反应气体SiH4流量约为270sccm。
17.如权利要求15所述的方法，其中所述反应气体NH3流量约为80sccm。
18.如权利要求14所述的方法，其中形成所述氮化硅层的制造过程功率约为760瓦。
19.如权利要求14所述的方法，其中形成所述氮化硅层的极板间距约为1.65cm。
21.如权利要求14所述的方法，其中形成所述氮化硅层的制造过程温度约为200至400℃。
22.如权利要求1所述的方法，其中所述导电层为铝金属。
23.如权利要求22所述的方法，其中形成所述氧化层之前还包含施以热处理的制造过程。
CN98106228A 1997-10-27 1998-04-07 在半导体芯片上形成保护层的方法 Expired - Lifetime CN1125484C (zh)

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US08/984,354 US6103639A (en) 1997-10-27 1997-12-03 Method of reducing pin holes in a nitride passivation layer
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US08/984,354 US6103639A (en) 1997-10-27 1997-12-03 Method of reducing pin holes in a nitride passivation layer
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CN107086174B (zh) * 2017-04-17 2020-02-07 上海华虹宏力半导体制造有限公司 改善顶层金属层的黏附强度的方法

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