CN112086364B - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
- Publication number
- CN112086364B CN112086364B CN201910931762.6A CN201910931762A CN112086364B CN 112086364 B CN112086364 B CN 112086364B CN 201910931762 A CN201910931762 A CN 201910931762A CN 112086364 B CN112086364 B CN 112086364B
- Authority
- CN
- China
- Prior art keywords
- conductive
- dielectric layer
- semiconductor structure
- hole
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 135
- 238000000034 method Methods 0.000 claims description 50
- 238000005530 etching Methods 0.000 claims description 26
- 230000000873 masking effect Effects 0.000 claims description 17
- 239000011241 protective layer Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910005540 GaP Inorganic materials 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000002411 adverse Effects 0.000 description 3
- 238000004380 ashing Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- BGTBFNDXYDYBEY-FNORWQNLSA-N 4-(2,6,6-Trimethylcyclohex-1-enyl)but-2-en-4-one Chemical compound C\C=C\C(=O)C1=C(C)CCCC1(C)C BGTBFNDXYDYBEY-FNORWQNLSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 206010027439 Metal poisoning Diseases 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1021—Pre-forming the dual damascene structure in a resist layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02313—Subtractive methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0235—Shape of the redistribution layers
- H01L2224/02351—Shape of the redistribution layers comprising interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开了一种半导体结构及其制造方法。半导体结构的制造方法包括以下步骤。在导线之上形成介电层。于介电层之上形成光阻层。图案化光阻层,以形成遮罩特征与开口,开口是被遮罩特征所定义。开口具有底部与顶部,顶部连通底部,且顶部比底部宽。以遮罩特征作为蚀刻遮罩蚀刻介电层,以在介电层中形成通孔孔洞。在通孔孔洞中填入导电材料,以形成导电通孔。通过使用上述的制造方法,通孔密度可以被改善。
Description
技术领域
本发明是有关于一种半导体结构与一种形成半导体结构的方法。更特别地,本发明是关于形成半导体结构的重分布层(redistribution layer;RDL)。
背景技术
随着电子工业的快速发展,集成电路(integrated circuits;ICs)的发展是为了实现高性能与微型化。集成电路材料与设计的技术进步已经产生了几代的集成电路,其中每一代的集成电路都具有比上一代的集成电路更小与更复杂的电路。因此,用于集成电路的重分布层(redistribution layer;RDL)的通孔孔洞也被缩小。
发明内容
本发明的目的在于提供一种半导体结构的制造方法,该方法可以改善通孔的密度。
本发明提供一种用于改善通孔密度的半导体结构及其制造方法。半导体结构的制造方法包括以下步骤。在导线之上形成介电层。在介电层之上形成光阻层。图案化光阻层,以形成遮罩特征与开口,开口是被遮罩特征所定义。开口具有底部与顶部,顶部连通底部,且顶部比底部宽。以遮罩特征作为蚀刻遮罩蚀刻介电层,以在介电层中形成通孔孔洞。在通孔孔洞中填入导电材料,以形成导电通孔。
依据本发明的一些实施方式中,半导体结构的制造方法还包括加深通孔孔洞,使得凹陷形成于导线之中。
依据本发明的一些实施方式,半导体结构的制造方法还包括在凹陷中填入导电材料。
依据本发明的一些实施方式,通过使用光罩来图案化光阻层,光罩具有透光部、半透光部与遮光部,半透光部位于透光部与遮光部之间。
依据本发明的一些实施方式,遮罩特征具有外部与内部,内部比外部宽,且内部接触于介电层。
依据本发明的一些实施方式,一种半导体结构包括半导体元件、导线、介电层以及重分布层。导线在半导体元件之上。介电层在导线之上。重分布层包括导电结构与导电通孔。导电结构位于介电层上方。导电通孔从导电结构向下延伸并穿过介电层。导电通孔包括底部、顶部与渐缩部。渐缩部位于底部与顶部之间。渐缩部的宽度变化大于底部与顶部的宽度变化。
依据本发明的一些实施方式,渐缩部从顶部往底部渐缩。
依据本发明的一些实施方式,底部接触于导线。
依据本发明的一些实施方式,半导体结构还包括保护层,位于重分布层之上。
依据本发明的一些实施方式,导电通孔的底表面低于导线的顶表面。
综上所述,本发明提供一种半导体结构及其制造方法。导电通孔包括底部、渐缩部与顶部。因为渐缩部与顶部比底部为宽,故渐缩部与顶部可以为随后的金属沉积工艺提供更多的空间,此也可以减轻例如金属沉积的外伸所导致的不利影响。再者,因为底部窄于渐缩部与顶部,故可具有改善通孔密度的功效。
应当了解前面的一般说明和以下的详细说明都仅是示例,并且旨在提供对本发明的进一步解释。
附图说明
本发明的各个方面可从以下实施方式的详细说明及随附的附图中得到进一步的理解。
图1是根据本发明的一些实施方式绘示的半导体结构的剖面示意图。
图2、图3以及图5至图14是根据本发明的一些实施方式在各个阶段形成半导体结构的方法的剖面图。
图4是根据本发明的一些实施方式的用于图案化光阻层的光罩的示意图。
主要附图标记说明:
10-半导体结构,110-基板,120-主动及/或被动元件(半导体元件),130-内连接结构,1400至140n-金属化层,1500至150n、1521至152n-介电层,1600-导电插塞,1701至170n-导线,1801至180n-导电通孔,300-介电层,400-光阻层,410-光罩,412-透光部,414-半透光部,416-遮光部,420-遮罩特征,422-外部,424-内部,500-开口,502-底部,504-顶部,600-通孔孔洞,600t-顶部区域,602-底部,604-渐缩部,606-顶部,700-导电层,700a-重分布层,710-导电通孔,712-底部,714-渐缩部,716-顶部,720、720a-导电结构,800-图案化遮罩层,900-保护层,910-氧化硅层,920-氮化硅层,930-聚酰亚胺层,R-凹陷,W1、W2-宽度。
具体实施方式
现在将参照本发明的实施方式,其示例被绘示在附图中。本发明在附图及说明书中尽量使用相同的附图元件号码,来表示相同或相似的部分。
图1是根据本发明的一些实施方式绘示的半导体结构10的剖面示意图。参阅图1,介电层300形成于内连接结构130之上,其中内连接结构130形成于基板110之上。重分布层(redistribution layer;RDL)700a位于基板110之上,且重分布层700a包括导电通孔710与导电结构720a。重分布层700a接触于介电层300。保护层900位于重分布层700a之上,且覆盖重分布层700a。
在一些实施方式中,基板110可以是硅基板。在一些其他的实施方式中,基板110可包括其他半导体元素,例如:锗(germanium),或包括半导体化合物,例如:碳化硅(siliconcarbide)、砷化镓(gallium arsenic)、磷化镓(gallium phosphide)、磷化铟(indiumphosphide)、砷化铟(indium phosphide)、及/或锑化铟(indium antimonide),或其他半导体合金,例如:硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、及/或磷砷化铟镓(GaInAsP),或其组合。在一些其他的实施方式中,基板110包括绝缘层覆硅(semiconductor-on-insulator;SOI)基板,例如具有埋层(buried layer)。
在一些实施方式中,一个或多个主动及/或被动元件120形成于基板110之上。一个或多个主动及/或被动元件120可包括各种N型金属氧化半导体(N-type metal-oxidesemiconductor;NMOS)及/或P型金属氧化半导体(P-type metal-oxide semiconductor;PMOS),例如晶体管、电容器、电阻器、二极管、光电二极管与熔丝等。
内连接结构130形成于一个或多个主动及/或被动元件120与基板110之上。内连接结构130电性连接一个或多个主动及/或被动元件120,以形成在半导体结构10内的功能电路。内连接结构130可以包括一个或多个金属化层1400至140n,其中n+1为一个或多个金属化层1400至140n的数量。在一些实施方式中,n的值会基于半导体结构10的设计规范而变化。金属化层1401至140n可以包括介电层1521至152n、导线1701至170n以及导电通孔1801至180n。介电层1521至152n形成于相对应的介电层1501至150n之上。
在一些实施方式中,金属化层1400可以包括通过介电层1500的导电插塞1600,并且金属化层1401至140n分别包括一个或多个导电内连接,例如分别在介电层1521至152n中的导线1701至170n,以及分别在介电层1501至150n中导电通孔1801至180n。导电插塞1600将一个或多个主动及/或被动元件120电性耦合到导线1701至170n以及导电通孔1801至180n。在半导体元件120是晶体管的一些实施方式中,导电插塞1600可以分别落在栅极电极与晶体管120的源极/漏极区上,因此可分别作为栅极接触与源极/漏极接触。
在一些实施方式中,导电插塞1600、导线1701至170n以及导电通孔1801至180n可以使用任何适当的方法来形成,例如镶嵌(damascene)、双镶嵌(dual damascene)等。导电插塞1600、导线1701至170n以及导电通孔1801至180n可以包括导电材料,例如铜、铝、钨,及其组合等。在一些实施方式中,导电插塞1600、导线1701至170n以及导电通孔1801至180n还可包括一个或多个阻挡/粘着层(未绘示),以保护相对应的介电层1500至150n以及介电层1520至152n免于扩散与金属中毒。一个或多个阻挡/粘着层可以包括钛、氮化钛、钽、氮化钽等,并且可以使用物理气相沉积(PVD)、化学气相沉积(CVD)、原子层气相沉积(ALD)等形成。
图2、图3以及图5至图14是根据本发明的一些实施方式在各个阶段形成一半导体结构10的方法的剖面图。为了清楚说明本发明的特征,基板110与内连接结构130(如图1所示)在图2、图3以及图5至图14中不绘示,合先叙明。
参阅图2。介电层300形成于导线170n之上。形成介电层300的方法可以使用例如物理气相沉积(PVD)、化学气相沉积(CVD)、原子层气相沉积(ALD),或其他适当的技术。在一些实施方式中,介电层300可包括单层或多层。介电层300可以包括氧化硅、氮化硅、氮氧化硅,或其他适当的材料。在一些实施方式中,在形成介电层300之前,在导线170n上形成阻挡层(未绘示)。阻挡层可以有利于导电线170n与介电层300之间的粘附。
参阅图3。光阻层400形成于介电层300之上。在一些实施方式中,形成光阻层400的方法可包括形成一个等离子体增强四乙氧基硅烷(plasma enhanced tetraethoxysilane;PETEOS)薄膜于介电层300之上。在一些实施方式中,光阻层400的材料可以包括有机材料,例如旋涂碳(spin-on carbon;SOC)材料等。
一并参阅图4与图5。图4是光罩410的示意图,此光罩410是用以图案化图3的光阻层400。如图4所示,光罩410包括透光部412、半透光部414以及遮光部416。遮光部416的遮光区域的密度大于半透光部414的遮光区域的密度。半透光部414位于透光部412与遮光部416之间。在一些实施方式中,形成具有透光部412、半透光部414以及遮光部416的光罩410的方法,可以使用玻璃上铬(chrome on glass;COG)、相位偏移遮罩(phase shift mask),或其他适当的方法。
如图5所示,光罩410(如图4所示)是用以图案化光阻层400(如图3所示),因而形成遮罩特征420。换句话说,通过使用适当的光刻技术,将光阻层400(如图3所示)图案化以形成遮罩特征420。遮罩特征420具有外部422与内部424。内部424比外部422更宽。内部424接触于介电层300。
在本实施方式中,开口500是由遮罩特征420所定义,且开口500暴露下面的介电层300。开口500具有底部502与顶部504,且顶部504连通底部502。详细来说,底部502具有宽度W1,而顶部504具有宽度W2。宽度W2比宽度W1宽。由于光罩410的透光部412、半透光部414与遮光部416具有不同的透光深度,而使得图5中的遮罩特征420具有开口500,且开口500具有宽度W1的底部502以及具有宽度W2的顶部504。
参阅图6。使用遮罩特征420作为蚀刻遮罩,以蚀刻介电层300。蚀刻工艺在介电层300中产生通孔孔洞600。由于蚀刻工艺使用遮罩特征420作为蚀刻遮罩,使得通孔孔洞600具有的宽度W1与遮罩特征420内的开口500的底部502的宽度W1实质上相同。
如图6所示,介电层300的一部分保留在通孔孔洞600的下面。通孔孔洞600位于开口500的下面。换句话说,介电层300的一部分保留在通孔孔洞600与下面的介电层300之间。
在一些实施方式中,蚀刻介电层300的方法可以使用干式蚀刻。当使用干式蚀刻以蚀刻介电层300时,所选择的干式蚀刻剂可包括氢气(H2)及氮气(N2)。
参阅图7。使用遮罩特征420作为蚀刻遮罩,以蚀刻介电层300,使得通孔孔洞600被加深与被扩展。详细来说,遮罩特征420的内部424在蚀刻工艺期间被消耗,且遮罩特征420的外部422的厚度减少,使得遮罩特征420的外部422对齐于遮罩特征420的内部424。换句话说,在遮罩特征420的内部424被消耗之后,蚀刻内部424下面的介电层300的一部分,进而使得通孔孔洞600具有渐缩轮廓(tapered profile)。再换句话说,因为遮罩特征420(如图6所示)具有阶梯状轮廓(stepped profile),例如遮罩特征420的内部424与外部422,所以通孔孔洞600具有渐缩轮廓。在一些实施方式中,开口500的顶部504的宽度等于开口500的底部502的宽度。由于遮罩特征420具有侧向扩展的底部502的开口500,因此蚀刻工艺导致在介电层300与遮罩特征420的界面中侧向扩展通孔孔洞600的顶部区域600t。详细来说,通孔孔洞600的顶部区域600t被扩展,且具有宽度W2。举例来说,通孔孔洞600的顶部区域600t的宽度W2等于图5中的开口500的顶部504的宽度W2。
在一些实施方式中,在图7中蚀刻介电层300以扩展通孔孔洞600可与图6的先前蚀刻工艺于原位(in-situ)进行。换句话说,可以在没有破真空(vacuum break)的情况下,进行图7的扩展通孔孔洞600的蚀刻工艺以及图6的蚀刻工艺。举例来说,图7的扩展通孔孔洞600的蚀刻工艺以及图6的蚀刻工艺可以在相同蚀刻工具中进行,并且具有实质上相同的蚀刻参数。
参阅图8。使用遮罩特征420作为蚀刻遮罩,以蚀刻介电层300。详细来说,蚀刻工艺加深通孔孔洞600,直到抵达导线170n。换句话说,导线170n被暴露。在一些实施方式中,在图8中蚀刻介电层300以加深通孔孔洞600可与图7的先前蚀刻工艺于原位进行。换句话说,可以在没有破真空的情况下,进行图8的加深通孔孔洞600的蚀刻工艺以及图7的扩展通孔孔洞600的蚀刻工艺。举例来说,图8的加深通孔孔洞600的蚀刻工艺以及图7的扩展通孔孔洞600的蚀刻工艺可以在相同蚀刻工具中进行,并且具有实质上相同的蚀刻参数。
参阅图9。使用遮罩特征420作为蚀刻遮罩,以蚀刻介电层300。蚀刻工艺加深通孔孔洞600,使得凹陷R形成于导线170n内。详细来说,通孔孔洞600具有底部602、渐缩部604以及顶部606。渐缩部604位于底部602之上,且顶部606位于渐缩部604之上。渐缩部604从顶部606往底部602渐缩。底部602的宽度变化小于渐缩部604的宽度变化,且顶部606的宽度变化也小于渐缩部604的宽度变化。通孔孔洞600的底部602接触于导线170n。换句话说,通孔孔洞600的底部602接触于介电层300与导线170n。
在一些实施方式中,底部602的宽度实质上是不变的,且顶部606的宽度也是实质上不变的。因为渐缩部604与顶部606比底部602宽,所以渐缩部604与顶部606可以为随后的金属沉积工艺提供更多的空间,此也可以减轻由于随后的金属沉积的外伸(overhang)而导致的不利影响。再者,因为底部602窄于渐缩部604与顶部606,所以可实现改善通孔密度的功效。
在一些实施方式中,在图9中在导线170n内加深通孔孔洞600可与图8的在介电层300内加深通孔孔洞600的先前蚀刻工艺于原位进行。换句话说,可以在没有破真空的情况下,进行图9的在导线170n内加深通孔孔洞600的蚀刻工艺以及图8的在介电层300内加深通孔孔洞600的蚀刻工艺。举例来说,图9的在导线170n内加深通孔孔洞600的蚀刻工艺以及图8的在介电层300内加深通孔孔洞600的蚀刻工艺可以在相同蚀刻工具中进行,并且具有实质上相同的蚀刻参数。
参阅图10。遮罩特征420被移除。在一些实施方式中,可以通过使用光阻剥离(photoresist strip)工艺来执行移除遮罩特征420。例如,光阻剥离工艺可为灰化(ashing)工艺。
参阅图11。导电材料被填入于通孔孔洞600中。换句话说,导电材料亦被填入于凹陷R中(如图10所示)。如图11所示,导电层700形成于介电层300之上。详细来说,导电层700包括导电通孔710与导电结构720。导电层700覆盖介电层300,并且被填入于通孔孔洞600中,以在此通孔孔洞600中形成导电通孔710。在一些实施方式中,导电层700包括金属或金属合金,例如铝(Al)、铜(Cu)、其他适当的导电材料,或其组合。导电层700可以通过例如溅射方法的物理气相沉积(PVD)方法或其他适当的方法来形成。
在本实施方式中,导电通孔710从导电结构720向下延伸并且穿过介电层300。因为导电通孔710填入通孔孔洞600,故导电通孔710继承通孔孔洞600的轮廓。详细来说,导电通孔710包括底部712、渐缩部714与顶部716。渐缩部714从顶部716往底部712渐缩。底部712的宽度变化小于渐缩部714的宽度变化,并且顶部716的宽度变化也小于渐缩部714的宽度变化。举例来说,底部712的宽度是实质上不变的,且顶部716的宽度也是实质上不变的。在一些实施方式中,导电通孔710的底表面低于导线170n的顶表面。
参阅图12。图案化遮罩层800形成于导电层700之上。图案化遮罩层800覆盖导电结构720的一部分,同时暴露导电结构720的另一部分。在本实施方式中,图案化遮罩层800可以是光阻层。形成图案化遮罩层800的方法可包括先形成光阻层,然后用光刻工艺图案化前述的光阻层。
随后,使用图案化遮罩层800为蚀刻遮罩来图案化导电层700,所得到的结构如图13所示。在使用适当的蚀刻技术对导电层700进行图案化之后,可通过例如灰化工艺移除图案化遮罩层800。如图13所示,重分布层700a包括导电结构720a与导电通孔710。导电结构720a覆盖导电通孔710与介电层300的一部分,同时暴露介电层300的另一部分。
参阅图14。保护层900形成于基板110之上,以覆盖重分布层700a与介电层300。在一些实施方式中,保护层900是单层、双层或多层结构。保护层900可包括硅、氧化硅、氮氧化硅、氮化硅、有机材料、聚合物,或其组合。有机材料可为例如苯并环丁烯(benzocyclobutene;BCB),并且聚合物可为例如聚酰亚胺(polyimide;PI)。保护层900可以通过化学气相沉积(CVD)方法、涂布(coating)方法,或其他适当的方法形成。在本实施方式中,保护层900包括氧化硅层910、氮化硅层920以及聚酰亚胺层930。
综上所述,导电通孔包括底部、渐缩部与顶部。因为渐缩部与顶部比底部为宽,故渐缩部与顶部可以为随后的金属沉积工艺提供更多的空间,此也有助于减轻例如金属沉积的外伸所导致的不利影响。再者,因为底部窄于渐缩部与顶部,故可具有改善通孔密度的功效。
虽然本发明已经将实施方式详细地公开如上,然而其他的实施方式也是可能的,并非用以限定本发明。因此,所附的权利要求的精神及其范围不应限于本发明实施方式的说明。
本领域任何的技术人员,在不脱离本发明的精神和范围内,当可作各种的改变或替换,因此所有的这些改变或替换都应涵盖于本发明的权利要求的保护范围之内。
Claims (10)
1.一种半导体结构的制造方法,其特征在于,包含:
在导线之上形成介电层;
在所述介电层之上形成光阻层;
图案化所述光阻层,以形成遮罩特征与开口,所述开口是被所述遮罩特征所定义,其中所述开口具有底部与顶部,所述顶部连通所述底部,且所述顶部比所述底部宽;
以所述遮罩特征作为蚀刻遮罩蚀刻所述介电层,以在所述介电层中形成通孔孔洞;以及
在所述通孔孔洞中填入导电材料,以形成导电通孔,其中所述导电通孔包含底部、顶部及位于所述底部与所述顶部之间的渐缩部,所述导电通孔的所述渐缩部的宽度变化大于所述导电通孔的所述底部与所述导电通孔的所述顶部的宽度变化,所述导电通孔的所述顶部具有从所述导电通孔的所述渐缩部的倾斜侧壁向上连续延伸且垂直所述导电通孔的最低表面的侧壁。
2.如权利要求1所述的半导体结构的制造方法,其特征在于,还包含:
加深所述通孔孔洞,使得凹陷形成于所述导线之中。
3.如权利要求2所述的半导体结构的制造方法,其特征在于,还包含:
在所述凹陷中填入所述导电材料。
4.如权利要求1所述的半导体结构的制造方法,其特征在于,通过使用光罩来图案化所述光阻层,所述光罩具有透光部、半透光部与遮光部,所述半透光部位于所述透光部与所述遮光部之间。
5.如权利要求1所述的半导体结构的制造方法,其特征在于,所述遮罩特征具有外部与内部,所述内部比所述外部宽,且所述内部接触于所述介电层。
6.一种半导体结构,其特征在于,包含:
半导体元件;
导线,位于所述半导体元件之上;
介电层,位于所述导线之上;以及
重分布层,包含导电结构与导电通孔,所述导电结构位于所述介电层上方,所述导电通孔从所述导电结构向下延伸并穿过所述介电层,其中所述导电通孔包含底部、顶部与渐缩部,所述渐缩部位于所述底部与所述顶部之间,其中所述渐缩部的宽度变化大于所述底部与所述顶部的宽度变化,且所述导电通孔的所述顶部具有从所述导电通孔的所述渐缩部的倾斜侧壁向上连续延伸且垂直所述导电通孔的最低表面的侧壁。
7.如权利要求6所述的半导体结构,其特征在于,所述渐缩部从所述顶部往所述底部渐缩。
8.如权利要求6所述的半导体结构,其特征在于,所述底部接触于所述导线。
9.如权利要求6所述的半导体结构,其特征在于,还包含:
保护层,位于所述重分布层之上。
10.如权利要求6所述的半导体结构,其特征在于,所述导电通孔的底表面低于所述导线的顶表面。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/439,690 | 2019-06-12 | ||
US16/439,690 US11189523B2 (en) | 2019-06-12 | 2019-06-12 | Semiconductor structure and fabrication method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112086364A CN112086364A (zh) | 2020-12-15 |
CN112086364B true CN112086364B (zh) | 2023-01-10 |
Family
ID=73734294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910931762.6A Active CN112086364B (zh) | 2019-06-12 | 2019-09-29 | 半导体结构及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US11189523B2 (zh) |
CN (1) | CN112086364B (zh) |
TW (1) | TWI708299B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11393908B1 (en) * | 2021-02-04 | 2022-07-19 | Micron Technology, Inc. | Methods of forming a microelectronic device, and related microelectronic devices, memory devices, and electronic systems |
US11742286B2 (en) * | 2021-06-11 | 2023-08-29 | Nanya Technology Corporation | Semiconductor device with interconnect part and method for forming the same |
US20230029763A1 (en) * | 2021-07-30 | 2023-02-02 | Cree, Inc. | Interconnect metal openings through dielectric films |
CN116053203B (zh) * | 2023-03-07 | 2023-06-30 | 合肥晶合集成电路股份有限公司 | 互连结构的制备方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060014381A1 (en) * | 2004-07-13 | 2006-01-19 | Dongbuanam Semiconductor Inc. | Method for forming interconnection line in semiconductor device using a phase-shift photo mask |
US20080012142A1 (en) * | 2006-02-15 | 2008-01-17 | International Business Machines Corporation | Structure and method of chemically formed anchored metallic vias |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0241480B1 (en) * | 1985-09-27 | 1991-10-23 | Unisys Corporation | Method of fabricating a tapered via hole in polyimide |
JP4571785B2 (ja) * | 2003-05-30 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7081408B2 (en) * | 2004-10-28 | 2006-07-25 | Intel Corporation | Method of creating a tapered via using a receding mask and resulting structure |
US8264086B2 (en) * | 2005-12-05 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via structure with improved reliability |
JP2007266030A (ja) * | 2006-03-27 | 2007-10-11 | Seiko Epson Corp | 半導体装置の製造方法および半導体装置 |
JP2008047582A (ja) * | 2006-08-11 | 2008-02-28 | Fujitsu Ltd | 半導体装置の製造方法及び半導体装置 |
US9293401B2 (en) * | 2008-12-12 | 2016-03-22 | Stats Chippac, Ltd. | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP) |
DE102009006798B4 (de) * | 2009-01-30 | 2017-06-29 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung eines Metallisierungssystems eines Halbleiterbauelements unter Anwendung einer Hartmaske zum Definieren der Größe der Kontaktdurchführung |
US8623753B1 (en) * | 2009-05-28 | 2014-01-07 | Amkor Technology, Inc. | Stackable protruding via package and method |
US8513057B2 (en) | 2011-09-16 | 2013-08-20 | Stats Chippac Ltd. | Integrated circuit packaging system with routable underlayer and method of manufacture thereof |
JP5826783B2 (ja) * | 2013-03-25 | 2015-12-02 | 株式会社東芝 | 半導体装置 |
JPWO2016075791A1 (ja) * | 2014-11-13 | 2017-08-24 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN108630540B (zh) * | 2017-03-24 | 2021-05-28 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
US10964636B2 (en) * | 2018-09-19 | 2021-03-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure with low resistivity and method for forming the same |
US10811309B2 (en) * | 2018-12-04 | 2020-10-20 | Nanya Technology Corporation | Semiconductor structure and fabrication thereof |
KR20200103468A (ko) * | 2019-02-25 | 2020-09-02 | 삼성전자주식회사 | 반도체 칩의 연결구조체 제조 방법 및 반도체 패키지 제조 방법 |
-
2019
- 2019-06-12 US US16/439,690 patent/US11189523B2/en active Active
- 2019-09-19 TW TW108133881A patent/TWI708299B/zh active
- 2019-09-29 CN CN201910931762.6A patent/CN112086364B/zh active Active
-
2021
- 2021-10-05 US US17/449,951 patent/US20220028734A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060014381A1 (en) * | 2004-07-13 | 2006-01-19 | Dongbuanam Semiconductor Inc. | Method for forming interconnection line in semiconductor device using a phase-shift photo mask |
US20080012142A1 (en) * | 2006-02-15 | 2008-01-17 | International Business Machines Corporation | Structure and method of chemically formed anchored metallic vias |
Also Published As
Publication number | Publication date |
---|---|
US20200395242A1 (en) | 2020-12-17 |
US11189523B2 (en) | 2021-11-30 |
TWI708299B (zh) | 2020-10-21 |
TW202046418A (zh) | 2020-12-16 |
CN112086364A (zh) | 2020-12-15 |
US20220028734A1 (en) | 2022-01-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN112086364B (zh) | 半导体结构及其制造方法 | |
US9543193B2 (en) | Non-hierarchical metal layers for integrated circuits | |
US8404581B2 (en) | Method of forming an interconnect of a semiconductor device | |
US6235628B1 (en) | Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer | |
CN108074911B (zh) | 跳孔结构 | |
US11929258B2 (en) | Via connection to a partially filled trench | |
TWI545694B (zh) | 形成積體電路之內連線結構的方法及半導體裝置 | |
US11450556B2 (en) | Semiconductor structure | |
US10204859B2 (en) | Interconnect structure and fabricating method thereof | |
KR20230098237A (ko) | 자기-정렬된 상단 비아 | |
US6833316B2 (en) | Semiconductor device including a pad and a method of manufacturing the same | |
US7241684B2 (en) | Method of forming metal wiring of semiconductor device | |
US7112537B2 (en) | Method of fabricating interconnection structure of semiconductor device | |
US20030153176A1 (en) | Interconnection structure and interconnection structure formation method | |
US20230102662A1 (en) | Top via interconnects with line wiggling prevention | |
KR100591155B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
KR100393968B1 (ko) | 반도체 소자의 이중 다마신 형성방법 | |
KR100521453B1 (ko) | 반도체 소자의 다층 배선 형성방법 | |
KR100358569B1 (ko) | 반도체소자의 금속배선 형성방법 | |
KR100249827B1 (ko) | 반도체 소자의 다층 금속 배선 제조방법 | |
KR20040009746A (ko) | 반도체 소자의 듀얼 다마신 패턴 형성방법 | |
KR20070064965A (ko) | 반도체 소자의 미세 패턴 형성 방법 | |
KR20030092531A (ko) | 반도체 소자의 금속배선 형성방법 | |
KR20040003905A (ko) | 반도체 소자의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |