CN108630540B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN108630540B
CN108630540B CN201710180158.5A CN201710180158A CN108630540B CN 108630540 B CN108630540 B CN 108630540B CN 201710180158 A CN201710180158 A CN 201710180158A CN 108630540 B CN108630540 B CN 108630540B
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Prior art keywords
layer
active region
gate
insulator layer
conductive contact
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CN108630540A (zh
Inventor
张先明
唐凌
袁雷兵
豆峰
陈�峰
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201710180158.5A priority Critical patent/CN108630540B/zh
Priority to US15/820,561 priority patent/US10312093B2/en
Publication of CN108630540A publication Critical patent/CN108630540A/zh
Priority to US16/392,107 priority patent/US10497791B2/en
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Abstract

本发明公开了一种半导体装置及其制造方法，涉及半导体技术领域。该制造方法包括：提供半导体结构，该半导体结构包括：有源区和位于该有源区内的栅极结构，该栅极结构至少包括栅极，该有源区露出该栅极的上表面；在该栅极的上表面上形成表面绝缘物层；在该半导体结构上形成图案化的层间电介质层，该层间电介质层覆盖表面绝缘物层，并且具有露出有源区的一部分的第一通孔；以及形成穿过该第一通孔且与有源区接触的导电接触层。本发明可以减小导电接触层与栅极之间可能产生的漏电流，从而可以改善器件性能。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体技术领域，特别涉及一种半导体装置及其制造方法。
背景技术
目前，在半导体器件(例如IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管))的制造过程中，常常涉及到制造有源区的连接线。如图1所示，在有源区101内存在栅极绝缘物层112和栅极111。在有源区101上形成有层间电介质层(InterlevelDielectric，简称为ILD)120，该层间电介质层120形成有露出有源区的通孔(该通孔可以称为接触通孔)。然后形成穿过通孔且与有源区101接触的铝接触层130。在铝接触层130上形成有钝化物层140，以及在铝接触层130上粘结有金属线150。通常可以采用PVD(PhysicalVapor Deposition，物理气相沉积)工艺形成铝接触层130。
发明内容
本发明的发明人发现，由于在器件工作或结束工作过程中，有时会产生栅极电压振荡，从而在铝接触层与栅极之间可能会产生漏电流，这将会降低器件的性能。
另外，本发明的发明人还发现，由于PVD工艺在通孔处形成阶梯覆盖以及在形成铝接触层时有比较大的接触角度，会导致在铝接触层中产生缝隙或孔洞。该缝隙或孔洞将会影响金属线粘结工艺，从而降低器件的可靠性。
根据本发明的第一方面，提供了一种半导体装置的制造方法，包括：提供半导体结构，所述半导体结构包括：有源区和位于所述有源区内的栅极结构，所述栅极结构至少包括栅极，所述有源区露出所述栅极的上表面；在所述栅极的上表面上形成表面绝缘物层；在所述半导体结构上形成图案化的层间电介质层，所述层间电介质层覆盖所述表面绝缘物层，并且具有露出所述有源区的一部分的第一通孔；以及形成穿过所述第一通孔且与所述有源区接触的导电接触层。
在一个实施例中，通过对所述栅极的上表面执行氧化以形成所述表面绝缘物层。
在一个实施例中，所述栅极的材料包括多晶硅；所述表面绝缘物层的材料包括硅的氧化物。
在一个实施例中，在空气或氧气的气氛中对所述栅极的上表面执行退火处理以使所述栅极的上表面氧化，从而形成表面绝缘物层。
在一个实施例中，所述退火处理为激光退火处理。
在一个实施例中，执行所述激光退火处理的步骤包括：在所述半导体结构上形成图案化的第一掩模层，所述第一掩模层具有露出所述栅极的上表面的第一开口；在空气或氧气的气氛中，透过所述第一开口向所述栅极的上表面照射激光脉冲以执行激光退火处理，从而将所述栅极的上表面氧化；以及去除所述第一掩模层。
在一个实施例中，所述激光脉冲的波长范围为200nm至350nm。
在一个实施例中，通过调节所述激光脉冲的能量和/或照射次数来控制调节所述表面绝缘物层的厚度。
在一个实施例中，所述第一通孔为锥形通孔，所述锥形通孔具有远离所述有源区上表面的上部开口和邻接所述有源区上表面的下部开口，其中所述上部开口的宽度大于所述下部开口的宽度。
在一个实施例中，所述锥形通孔的侧壁倾斜角的角度范围为30°至40°。
在一个实施例中，在所述半导体结构上形成图案化的层间电介质层的步骤包括：形成覆盖所述半导体结构的层间电介质层；在所述层间电介质层上形成图案化的第二掩模层，所述第二掩模层具有露出所述层间电介质层的一部分的第二开口；对所述第二掩模层执行回流处理，从而减小所述第二开口侧壁的倾斜角；以经过所述回流处理后的第二掩模层作为掩模，刻蚀所述层间电介质层以形成第一通孔；以及去除所述第二掩模层。
在一个实施例中，所述回流处理的温度范围为100℃至300℃；所述回流处理的时间范围为2分钟至5分钟。
在一个实施例中，在提供半导体结构的步骤中，所述栅极结构还包括将所述栅极和所述有源区隔离开的栅极绝缘物层；在形成所述表面绝缘物层的步骤中，所述表面绝缘物层和所述栅极绝缘物层将所述栅极包围。
在一个实施例中，所述方法还包括：在所述导电接触层上形成图案化的钝化物层，所述钝化物层具有露出所述导电接触层的一部分的第二通孔；以及形成穿过所述第二通孔且与所述导电接触层接触的金属连接件。
上述制造方法可以在栅极的上表面上形成表面绝缘物层，从而可以增加栅极与导电接触层的距离，这样可以减小导电接触层与栅极之间可能产生的漏电流，从而可以改善器件性能。
进一步地，在上述制造方法中，还可以使得层间电介质层的通孔(即第一通孔)相对现有技术呈现侧壁倾斜角更小的锥形，因此可以改善后续导电接触层的阶梯覆盖，尽量减小导电接触层可能形成的缝隙或空洞，从而有利于后续金属连接件(或金属线)的粘结，提高器件的可靠性。
根据本发明的第二方面，提供了一种半导体装置，包括：有源区；位于所述有源区内的栅极结构，所述栅极结构至少包括栅极，所述有源区露出所述栅极的上表面；在所述栅极的上表面上的表面绝缘物层；在所述有源区上的图案化的层间电介质层，所述层间电介质层覆盖所述表面绝缘物层，并且具有露出所述有源区的一部分的第一通孔；以及穿过所述第一通孔且与所述有源区接触的导电接触层。
在一个实施例中，所述栅极的材料包括多晶硅；所述表面绝缘物层的材料包括硅的氧化物。
在一个实施例中，所述第一通孔为锥形通孔，所述锥形通孔具有远离所述有源区上表面的上部开口和邻接所述有源区上表面的下部开口，其中所述上部开口的宽度大于所述下部开口的宽度。
在一个实施例中，所述锥形通孔的侧壁倾斜角的角度范围为30°至40°。
在一个实施例中，所述栅极结构还包括将所述栅极和所述有源区隔离开的栅极绝缘物层；其中，所述表面绝缘物层和所述栅极绝缘物层将所述栅极包围。
在一个实施例中，所述半导体装置还包括：在所述导电接触层上的图案化的钝化物层，所述钝化物层具有露出所述导电接触层的一部分的第二通孔；以及穿过所述第二通孔且与所述导电接触层接触的金属连接件。
在上述半导体装置中，在栅极的上表面上形成有表面绝缘物层，从而可以增加栅极与导电接触层的距离，这样可以减小导电接触层与栅极之间可能产生的漏电流，从而可以改善器件性能。
进一步地，在上述半导体装置中，由于层间电介质层的通孔(即第一通孔)相对现有技术呈现侧壁倾斜角更小的锥形，因此可以改善导电接触层的阶梯覆盖，尽量减小导电接触层可能形成的缝隙或空洞，从而有利于金属连接件的粘结，提高器件的可靠性。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1是示意性地示出现有技术中半导体器件的金属线粘结的结构的横截面图。
图2是示出根据本发明一个实施例的半导体装置的制造方法的流程图。
图3是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图4是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图5是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图6是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图7是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图8是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图9是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图10是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图11是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图12是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图13是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图14是示意性地示出根据本发明一个实施例的Si的吸收光谱图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
本发明的发明人发现，由于在器件工作或结束工作过程中，有时会产生栅极电压振荡(例如，器件关断时的电压变化率比较大，过冲电压也比较大，导致栅极电压振荡)，在铝接触层与栅极之间可能会产生漏电流，这将会降低器件性能。
另外，本发明的发明人还发现，由于PVD工艺在通孔处形成阶梯覆盖以及形成铝接触层时有比较大的接触角度(该接触角度是指层间电介质层120的接触通孔的侧壁与有源区101上表面的夹角，该夹角可以为直角或者比较大的锐角(例如50°至60°的锐角))，会导致在铝接触层中产生缝隙或孔洞135(如图1所示)。有时还可能会有钝化物的颗粒落入该缝隙或空洞内。该缝隙或孔洞将会影响金属线粘结(Wire bonding)工艺，例如出现虚焊或脱焊问题，从而最终降低器件的可靠性。
可以采用热金属(Hot metal)工艺来获得比较好的阶梯覆盖，或者通过各向同性刻蚀来优化接触通孔的形貌，从而减小上述缝隙或孔洞，但是这些工艺方法都需要购买新的设备，导致制造成本比较高。
图2是示出根据本发明一个实施例的半导体装置的制造方法的流程图。图3至图13是示意性地示出根据本发明一个实施例的半导体装置的制造过程中若干阶段的结构的横截面图。下面结合图2以及图3至图13来详细描述根据本发明一个实施例的半导体装置的制造过程。
首先，如图2所示，在步骤S201，提供半导体结构，该半导体结构包括：有源区和位于该有源区内的栅极结构，该栅极结构至少包括栅极，该有源区露出该栅极的上表面。
图3是示意性地示出根据本发明一个实施例的在步骤S201的结构的横截面图。如图3所示，提供半导体结构。该半导体结构可以包括：有源区301和位于该有源区301内的栅极结构310。该栅极结构310至少包括栅极311。该有源区301露出该栅极311的上表面。在该步骤S201中，该栅极结构310还可以包括将栅极311和有源区301隔离开的栅极绝缘物层312。
在一个实施例中，有源区301的材料可以包括硅等，栅极311的材料可以包括多晶硅(例如掺杂的多晶硅)等，栅极绝缘物层312的材料可以包括硅的氧化物等。
在一个实施例中，该步骤S201可以包括：提供有源区；对该有源区执行刻蚀以在该有源区中形成沟槽。可选地，该步骤S201还可以包括：例如通过沉积工艺在沟槽中形成栅极绝缘物层。可选地，该步骤S201还可以包括：例如通过沉积工艺在栅极绝缘物层上形成栅极材料层(例如该栅极材料层可以为多晶硅)。该栅极材料层一部分填充在沟槽中，另一部分形成在有源区之上。可选地，该步骤S201还可以包括：通过刻蚀或平坦化工艺去除在有源区之上的多余的栅极材料层，而剩余在沟槽中的栅极材料层作为栅极。
回到图2，在步骤S202，在栅极的上表面上形成表面绝缘物层。例如，该表面绝缘物层的材料可以包括硅的氧化物。在该步骤S202中，该表面绝缘物层和栅极绝缘物层将栅极包围。
在一个实施例中，可以通过对栅极的上表面执行氧化以形成该表面绝缘物层。例如，在空气或氧气的气氛中对栅极的上表面执行退火处理以使该栅极的上表面氧化，从而形成表面绝缘物层。优选地，退火处理可以为激光退火处理。通过激光退火处理，可以方便地使得栅极的上表面被氧化，而且可以控制所形成的硅的氧化物层的厚度，有利于提高器件性能。
当然，本领域技术人员可以理解，这里形成表面绝缘物层的方法并不仅限于上述方法，还可以使用其他方法，例如可以通过沉积形成表面绝缘物层，或者通过其他的退火工艺来执行氧化工艺等。
图4至图6是示意性地示出根据本发明一个实施例的执行激光退火处理步骤的若干阶段的结构的横截面图。下面结合图4至图6详细描述执行激光退火处理的过程。
例如，如图4所示，该执行激光退火处理的步骤可以包括：在半导体结构上形成图案化的第一掩模层410。该第一掩模层410具有露出栅极311的上表面的第一开口411。例如可以通过沉积和光刻工艺形成该图案化的第一掩模层。该第一掩模层的材料可以包括光刻胶。
接下来，如图5所示，该执行激光退火处理的步骤还可以包括：在空气或氧气的气氛中，透过第一开口411向栅极311的上表面照射激光脉冲420以执行激光退火处理(例如激光局域退火)，从而将该栅极311的上表面氧化，从而形成表面绝缘物层430。例如，该激光脉冲为紫外线(UV)激光脉冲。
在该步骤中，由于在激光照射下，栅极表面出现熔化(melting)，在该熔化过程中，栅极表面吸收了氧，因此在表面熔化和再固化过程中，由于在栅极的再生区域俘获了被吸收的氧，因而在该区域发生了快速氧化过程，形成氧化物层(例如硅的氧化物层)以作为表面绝缘物层。通过激光退火处理可以得到高质量的氧化物层(例如致密性更高)，并可以控制氧化物层的厚度。由于该激光退火工艺可以采用已经存在的设备执行，因此基本不增加成本。
优选地，该激光脉冲的波长范围可以为200nm至350nm(例如波长可以为250nm或300nm等)。例如可以参见本发明的发明人所研究的Si的吸收光谱图，即图14，从该图14中可以看出，Si比较容易吸收200nm至350nm波长范围的光。也就是说，利用该波长范围的光更容易使得Si表面熔化，从而吸收氧以形成硅的氧化物层。因此，采用该波长范围的激光脉冲，有利于控制生成的硅的氧化物层(作为表面绝缘物层)的厚度。
在一个实施例中，可以通过调节激光脉冲的能量和/或照射次数来控制调节表面绝缘物层的厚度。通过调节表面绝缘物层的厚度，可以优化导电接触层(后面将描述)与栅极之间的漏电流，提高器件性能。
在一个实施例中，该表面绝缘物层430的厚度可以小于
Figure BDA0001253409160000091
例如，该表面绝缘物层的厚度可以是
Figure BDA0001253409160000092
或
Figure BDA0001253409160000093
等。
接下来，如图6所示，该执行激光退火处理的步骤还可以包括：去除第一掩模层410。通过上述执行激光退火处理的步骤，在栅极311的上表面上形成了表面绝缘物层430。
回到图2，在步骤S203，在半导体结构上形成图案化的层间电介质层，该层间电介质层覆盖表面绝缘物层，并且具有露出有源区的一部分的第一通孔。
在一个实施例中，该第一通孔可以为锥形通孔(例如圆锥形)。该锥形通孔具有远离有源区上表面的上部开口和邻接有源区上表面的下部开口，其中该上部开口的宽度大于该下部开口的宽度。该锥形通孔有利于在后续形成导电接触层的过程中，使得导电接触层中尽量减小由于阶梯覆盖导致的缝隙或空洞，从而有利于金属连接件(或金属线)的粘结。
当然，本领域技术人员可以理解，本发明也可以采用其他形状的通孔，例如可以是具有多个阶梯且近似于锥形的通孔等，也可以采用现有的通孔，因此本发明的范围并不仅限于此。
优选地，上述锥形通孔的侧壁倾斜角的角度范围可以为30°至40°。例如该侧壁倾斜角可以为35°或38.9°等。这里需要说明的是，该侧壁倾斜角是指该锥形通孔的侧壁与有源区的上表面相交所成的锐角。该角度范围有利于减小后续导电接触层可能出现的缝隙或空洞，也不会由于角度太小导致层间电介质层的倾斜部分太薄而容易出现漏电流。
当然，本领域技术人员可以理解，上述侧壁倾斜角的范围也可以是其他范围，例如小于30°，因此本发明的范围并不仅限于上述所公开的角度范围。
图7至图10是示意性地示出根据本发明一个实施例的在半导体结构上形成图案化的层间电介质层步骤的若干阶段的结构的横截面图。下面结合图7至图10详细描述该形成图案化的层间电介质层的过程。
例如，如图7所示，在半导体结构上形成图案化的层间电介质层的步骤可以包括：例如通过沉积工艺形成覆盖半导体结构的层间电介质层620。例如该层间电介质层的材料可以包括二氧化硅。该层间电介质层的厚度可以为零点几微米至几微米，例如1μm。
接下来，如图8所示，在半导体结构上形成图案化的层间电介质层的步骤还可以包括：在层间电介质层620上形成图案化的第二掩模层630。该第二掩模层630具有露出层间电介质层620的一部分的第二开口632。例如可以通过涂覆和光刻工艺形成该第二掩模层。优选地，该第二掩模层的材料为光刻胶。采用光刻胶有利于执行后续的回流处理。
接下来，如图9所示，在半导体结构上形成图案化的层间电介质层的步骤还可以包括：对第二掩模层630执行回流(reflow)处理，从而减小第二开口侧壁的倾斜角θ，从而使得该第二开口形成侧壁倾斜角更小的锥形开口。需要说明的是，这里的倾斜角θ是指第二开口的侧壁与层间电介质层的上表面相交所成的锐角，如图9所示。优选地，该倾斜角θ角度范围为30°至40°。
在一个实施例中，该回流处理的温度范围可以为100℃至300℃。例如，该回流处理的温度可以为150℃、200℃或240℃等。当然，该回流处理的温度也可以是其他温度范围，本发明的范围并不仅限于此。
在一个实施例中，该回流处理的时间范围可以为2分钟至5分钟。例如，该回流处理的时间可以是3分钟或4分钟等。当然，该回流处理的时间也可以是其他时间范围，因此本发明的范围并不仅限于此。
接下来，如图10所示，在半导体结构上形成图案化的层间电介质层的步骤还可以包括：以经过回流处理后的第二掩模层630作为掩模，刻蚀层间电介质层620以形成第一通孔(该第一通孔也可以称为接触通孔)621。由于在刻蚀的过程中第二掩模层也被不断地刻蚀掉，第二掩模层中比较薄的部分被刻蚀掉得快，比较厚的部分被刻蚀掉的慢，因此该刻蚀工艺可以将第二掩模层的形貌复制到下面的层间电介质层上，从而在层间电介质层中形成锥形的第一通孔。
在该步骤中，如图10所示，在层间电介质层中形成了露出有源区的一部分的第一通孔621。该第一通孔621可以为锥形通孔(例如圆锥形)。该锥形通孔具有远离有源区301上表面的上部开口6211和邻接有源区301上表面的下部开口6212，其中该上部开口6211的宽度大于该下部开口6212的宽度。如果该锥形通孔为圆锥形通孔，则上部开口的直径大于下部开口的直径。
优选地，该锥形通孔的侧壁倾斜角α(即该锥形通孔的侧壁与有源区的上表面相交所成的锐角)的角度范围可以为30°至40°。例如该侧壁倾斜角α可以为35°或38.9°等。
接下来，如图10所示，在半导体结构上形成图案化的层间电介质层的步骤还可以包括：去除第二掩模层630。例如，可以将在上述刻蚀步骤中没有完全刻蚀掉而剩余的第二掩模层去除。
至此，在半导体结构上形成了图案化的层间电介质层620。该层间电介质层620覆盖表面绝缘物层430，并且具有露出有源区301的一部分的第一通孔621。
回到图2，在步骤S204，形成穿过第一通孔且与有源区接触的导电接触层。
图11是示意性地示出根据本发明一个实施例的在步骤S204的结构的横截面图。如图11所示，例如通过沉积工艺形成穿过第一通孔621且与有源区301接触的导电接触层730。该导电接触层730覆盖在层间电介质层620上。例如该导电接触层730的材料可以包括诸如铝等的金属。该导电接触层730的厚度为可以几微米，例如4μm。
至此，提供了根据本发明一个实施例的半导体装置的制造方法。通过该制造方法，可以在栅极的上表面上形成表面绝缘物层，从而可以增加栅极与导电接触层的距离，例如如图11中的双箭头直线所示，这样可以减小导电接触层与栅极之间可能产生的漏电流，从而可以改善器件性能。
进一步地，在上述制造方法中，还可以使得层间电介质层的通孔(即第一通孔)相对现有技术呈现侧壁倾斜角更小的锥形，因此可以改善导电接触层的阶梯覆盖，尽量减小导电接触层可能形成的缝隙或空洞(如图11所示)，甚至可以消除该缝隙或空洞，从而有利于后续金属连接件(或金属线)的粘结，提高器件的可靠性。另外，由于上述方法可以利用已经具有的设备实施，不需要购买新的设备，因此成本相对较低。
在本发明的实施例中，上述半导体装置的制造方法还可以包括：如图12所示，在导电接触层730上形成图案化的钝化物层740。该钝化物层740具有露出导电接触层730的一部分的第二通孔742。例如，先通孔沉积工艺在导电接触层730上形成钝化物层740；然后对该钝化物层740执行刻蚀以形成露出导电接触层730的一部分的第二通孔742。
在本发明的实施例中，上述半导体装置的制造方法还可以包括：如图13所示，(例如通过沉积或粘结等技术)形成穿过第二通孔742且与导电接触层730接触的金属连接件850。该金属连接件可以是金属线。
通过上述制造方法，形成了经由导电接触层连接有源区的金属连接件，由于在前面的步骤中，减小了导电接触层可能形成的缝隙或空洞，因此所形成的金属连接件能够更加牢固地连接导电接触层，减小出现虚焊或脱焊问题的可能性，从而提高器件的可靠性。
本发明还提供了一种半导体装置，例如如图13所示，该半导体装置可以包括：有源区301和位于该有源区301内的栅极结构310。该栅极结构310至少包括栅极311。该有源区301露出该栅极311的上表面。例如，该栅极311的材料可以包括多晶硅。该栅极结构310还可以包括将栅极311和有源区301隔离开的栅极绝缘物层312。该栅极绝缘物层312的材料可以包括硅的氧化物等。
如图13所示，该半导体装置还可以包括：在栅极311的上表面上的表面绝缘物层430。例如，该表面绝缘物层430的材料可以包括硅的氧化物。该表面绝缘物层430和该栅极绝缘物层312将栅极311包围。
如图13所示，该半导体装置还可以包括：在有源区301上的图案化的层间电介质层620。该层间电介质层620覆盖表面绝缘物层430，并且具有露出有源区301的一部分的第一通孔621。
在一个实施例中，该第一通孔621可以为锥形通孔。该锥形通孔具有远离有源区301上表面的上部开口(例如前面描述的上部开口6211)和邻接有源区301上表面的下部开口(例如前面描述的下部开口6212)。其中该上部开口的宽度大于该下部开口的宽度。
在一个实施例中，该锥形通孔的侧壁倾斜角α的角度范围可以为30°至40°。例如该侧壁倾斜角α可以为35°或38.9°等。
如图13所示，该半导体装置还可以包括：穿过第一通孔621且与有源区301接触的导电接触层730。例如该导电接触层730的材料可以包括诸如铝等的金属。该导电接触层730的厚度为可以几微米，例如4μm。
在一个实施例中，如图13所示，该半导体装置还可以包括：在导电接触层730上的图案化的钝化物层740。该钝化物层740具有露出导电接触层730的一部分的第二通孔742。
在一个实施例中，如图13所示，该半导体装置还可以包括：穿过该第二通孔742且与导电接触层730接触的金属连接件850。
在本发明实施例的半导体装置中，由于在栅极的上表面上形成有表面绝缘物层，从而可以增加栅极与导电接触层的距离，例如如图13中的双箭头直线所示，这样可以减小导电接触层与栅极之间可能产生的漏电流，从而可以改善器件性能。
进一步地，在上述半导体装置中，由于层间电介质层的通孔(即第一通孔)相对现有技术呈现侧壁倾斜角更小的锥形，因此可以改善导电接触层的阶梯覆盖，尽量减小导电接触层可能形成的缝隙或空洞，从而有利于金属连接件的粘结，提高器件的可靠性。
至此，已经详细描述了根据本发明的制造半导体装置的方法和所形成的半导体装置。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (16)

1.一种半导体装置的制造方法，其特征在于，包括：
提供半导体结构，所述半导体结构包括：有源区和位于所述有源区内的栅极结构，所述栅极结构至少包括栅极，所述有源区露出所述栅极的上表面；
在所述栅极的上表面上形成表面绝缘物层；
在所述半导体结构上形成图案化的层间电介质层，所述层间电介质层覆盖所述表面绝缘物层，并且具有露出所述有源区的一部分的第一通孔，所述第一通孔为锥形通孔，所述锥形通孔具有远离所述有源区上表面的上部开口和邻接所述有源区上表面的下部开口，其中所述上部开口的宽度大于所述下部开口的宽度，所述锥形通孔的侧壁倾斜角的角度范围为30°至40°；以及
形成穿过所述第一通孔且与所述有源区接触的导电接触层。
2.根据权利要求1所述的方法，其特征在于，
通过对所述栅极的上表面执行氧化以形成所述表面绝缘物层。
3.根据权利要求2所述的方法，其特征在于，
所述栅极的材料包括多晶硅；
所述表面绝缘物层的材料包括硅的氧化物。
4.根据权利要求2所述的方法，其特征在于，
在空气或氧气的气氛中对所述栅极的上表面执行退火处理以使所述栅极的上表面氧化，从而形成表面绝缘物层。
5.根据权利要求4所述的方法，其特征在于，
所述退火处理为激光退火处理。
6.根据权利要求5所述的方法，其特征在于，执行所述激光退火处理的步骤包括：
在所述半导体结构上形成图案化的第一掩模层，所述第一掩模层具有露出所述栅极的上表面的第一开口；
在空气或氧气的气氛中，透过所述第一开口向所述栅极的上表面照射激光脉冲以执行激光退火处理，从而将所述栅极的上表面氧化；以及
去除所述第一掩模层。
7.根据权利要求6所述的方法，其特征在于，
所述激光脉冲的波长范围为200nm至350nm。
8.根据权利要求6所述的方法，其特征在于，
通过调节所述激光脉冲的能量和/或照射次数来控制调节所述表面绝缘物层的厚度。
9.根据权利要求1所述的方法，其特征在于，在所述半导体结构上形成图案化的层间电介质层的步骤包括：
形成覆盖所述半导体结构的层间电介质层；
在所述层间电介质层上形成图案化的第二掩模层，所述第二掩模层具有露出所述层间电介质层的一部分的第二开口；
对所述第二掩模层执行回流处理，从而减小所述第二开口侧壁的倾斜角；
以经过所述回流处理后的第二掩模层作为掩模，刻蚀所述层间电介质层以形成第一通孔；以及
去除所述第二掩模层。
10.根据权利要求9所述的方法，其特征在于，
所述回流处理的温度范围为100℃至300℃；
所述回流处理的时间范围为2分钟至5分钟。
11.根据权利要求1所述的方法，其特征在于，
在提供半导体结构的步骤中，所述栅极结构还包括将所述栅极和所述有源区隔离开的栅极绝缘物层；
在形成所述表面绝缘物层的步骤中，所述表面绝缘物层和所述栅极绝缘物层将所述栅极包围。
12.根据权利要求1所述的方法，其特征在于，还包括：
在所述导电接触层上形成图案化的钝化物层，所述钝化物层具有露出所述导电接触层的一部分的第二通孔；以及
形成穿过所述第二通孔且与所述导电接触层接触的金属连接件。
13.一种半导体装置，其特征在于，包括：
有源区；
位于所述有源区内的栅极结构，所述栅极结构至少包括栅极，所述有源区露出所述栅极的上表面；
在所述栅极的上表面上的表面绝缘物层；
在所述有源区上的图案化的层间电介质层，所述层间电介质层覆盖所述表面绝缘物层，并且具有露出所述有源区的一部分的第一通孔，所述第一通孔为锥形通孔，所述锥形通孔具有远离所述有源区上表面的上部开口和邻接所述有源区上表面的下部开口，其中所述上部开口的宽度大于所述下部开口的宽度，所述锥形通孔的侧壁倾斜角的角度范围为30°至40°；以及
穿过所述第一通孔且与所述有源区接触的导电接触层。
14.根据权利要求13所述的半导体装置，其特征在于，
所述栅极的材料包括多晶硅；
所述表面绝缘物层的材料包括硅的氧化物。
15.根据权利要求13所述的半导体装置，其特征在于，
所述栅极结构还包括将所述栅极和所述有源区隔离开的栅极绝缘物层；
其中，所述表面绝缘物层和所述栅极绝缘物层将所述栅极包围。
16.根据权利要求13所述的半导体装置，其特征在于，还包括：
在所述导电接触层上的图案化的钝化物层，所述钝化物层具有露出所述导电接触层的一部分的第二通孔；以及
穿过所述第二通孔且与所述导电接触层接触的金属连接件。
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