CN111984583A - Master control device suitable for VPX framework server - Google Patents
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- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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Abstract
The invention provides a master control device suitable for a VPX architecture server, which comprises: the system comprises a processor, a DDR4SODIMM memory slot, a DDR4SODIMM memory bank, a PCI-E to USB chip, a PCI-E to SATA chip, a PCI-E to SRIO chip and an SRIO exchange chip; the memory of the main control device adopts a DDR4SODIMM memory slot mode, the problem that the traditional main control device adopts an on-board memory particle mode to occupy a large area of a printed board to cause difficult layout and wiring is solved, the main control device not only reduces the area of the printed board occupied by the memory by more than 70 percent, but also improves the memory capacity by 1 time, and the capacity can be further improved by subsequently flexibly replacing the memory bank.
Description
Technical Field
The invention relates to the technical field of VPX main boards, in particular to a main control device suitable for a VPX framework server.
Background
VPX is a new generation of high speed serial bus standard proposed by Versamoule Eurocard International trade Association that recommends the use of high speed buses such as SRIO,10GbE and PCI-E for server system interconnection. The server based on the VPX framework has the characteristics of high reliability, high bandwidth, high performance and the like, is suitable for severe environments, is widely applied to the scenes of networks, telecommunications, aerospace, storage, industry and the like, and executes tasks such as calculation, communication, control and the like. The core of the VPX architecture server is a main control device, most of the main control devices in the current market adopt core, super or MPC8640 series processors to run Windows or VxWorks operating systems, so that key software and hardware of the main control device are firmly controlled abroad. The main control device of the VPX architecture server in the market can not be controlled independently, so that the problems of implanted hardware trojans, software viruses and the like exist, huge risks are brought by foreign forbidden chips, and the safety of information equipment in China is threatened seriously.
Patent document CN105511574A discloses a VPX motherboard based on a Loongson processor. The VPX mainboard based on the Loongson processor takes a Loongson 3B eight-core processor as a platform, the master frequency is 1.2 GHz-1.5 GHz, a table memory is supported, the VPX mainboard is adaptive to an AMD RS780E + SB710 chipset, and an embedded flash memory single-chip hard disk is adopted; with the VPX architecture, 1 set of VGA signals, 1 set of DVI signals, 1 set of KB/MS signals, 8 sets of USB2.0 signals, 8 sets of URAT signals, 4 sets of 10/100/1000Mps Ethernet signals, 1 set of PCI signals and 1 set of PCIE 16 signals can be provided. The patent still leaves room for improvement in structure and performance.
Disclosure of Invention
In view of the defects in the prior art, the present invention is directed to a master control device for a VPX framework server.
The invention provides a master control device suitable for a VPX architecture server, which comprises: the system comprises a processor, a DDR4SODIMM memory slot, a DDR4SODIMM memory bank, a PCI-E to USB chip, a PCI-E to SATA chip, a PCI-E to SRIO chip and an SRIO exchange chip; the processor is connected with a DDR4SODIMM memory slot, a PCI-E to USB chip, a PCI-E to SATA chip and a PCI-E to SRIO chip; the DDR4SODIMM memory slot is connected with a DDR4SODIMM memory bar; the PCI-E to USB chip outputs a USB3.0 interface; the PCI-E to SATA chip outputs an M.2 interface and an SATA3.0 interface; the PCI-E to SRIO chip is connected with the SRIO switching chip; and the SRIO exchange chip outputs an SRIO2.0 interface.
Preferably, the method further comprises the following steps: the device comprises a display chip, a PCI-E (peripheral component interconnect-express) gigabit network control chip, a master control gigabit network PHY chip, a management gigabit network PHY chip, a serial port level conversion chip, a CAN (controller area network) level conversion chip, a BIOS (basic input output system) chip and a real-time clock chip; the processor is connected with the display chip, the PCI-E3.0X8 interface, the PCI-E gigabit network control chip, the master control gigabit network PHY chip, the management gigabit network PHY chip, the serial port level conversion chip, the CAN level conversion chip, the BIOS chip and the real-time clock chip; the display chip outputs a VGA display interface and an HDMI display interface; the PCI-E to gigabit network control chip outputs a gigabit Ethernet interface; the master control gigabit network PHY chip outputs a master control gigabit Ethernet interface; the management kilomega network PHY chip outputs a management kilomega network port; the serial port level conversion chip outputs a serial port; the CAN level conversion chip outputs a CAN interface; the processor adopts a Feiteng processor; the FT processor adopts an FT-2000/4 processor; the Feiteng processor is integrated with 6 paths of PCI-E3.0 interfaces including a PEU0_ X1, a PEU0_ X8a, a PEU0_ X8b, a PEU1_ X1, a PEU1_ X8a and a PEU1_ X8 b.
Preferably, the PEU0_ X1 is connected with a PCI-E-to-USB chip; the PEU0_ X8a is connected with a PCI-E to SATA chip; the PEU0_ X8b is connected with a PCI-E to SRIO chip; the PEU1_ X1 is connected with a display chip; the PEU1_ X8a is connected with a PCI-E3.0X8 interface; the PEU1_ X8b is connected with a PCI-E to ten-trillion network control chip.
Preferably, the Feiteng processor further integrates a 2-way DDR4 memory controller; the 2-way DDR4 memory controller is externally connected with 2 DDR4SODIMM memory banks through DDR4SODIMM memory slots; the processor also integrates RGMII0 and RGMII1 into a 2-way RGMII interface, wherein RGMII0 connects the master gigabit network PHY chip and RGMII1 connects the management gigabit network PHY chip.
Preferably, the PCI-E to USB chip adopts a TUSB7340 chip; the four paths of USB3.0 signals of the TUSB7340 chip are connected with the USB3.0 interface.
Preferably, the PCI-E to SATA chip adopts an 88SE9215 chip; the 88SE9215 chip outputs four paths of SATA3.0 signals; the four SATA3.0 signals include: -SATA0 signal; -SATA1 signal; -SATA2 signal; -SATA3 signal; the SATA0 is in signal connection with an M.2 interface; the SATA1 signal, the SATA2 signal and the SATA3 signal are connected with a SATA3.0 interface.
Preferably, the PCI-E to SRIO chip adopts a TSI721 chip; the TSI721 chip realizes the interconversion between the PCI-E2.1 protocol and the SRIO2.1 protocol; and the SRIO2.1X4 signal of the TSI721 chip is connected with the SRIO exchange chip.
Preferably, the SRIO switching chip adopts a CPS1432 chip, the CPS1432 chip has 8-path SRIO2.1X4 signal switching capability, and four paths of SRIO2.1X4 signals of the CPS1432 chip are connected to an SRIO2.1X4 interface; the display chip adopts SM768 chip, the VGA signal connection VGA display interface of SM768 chip, the HDMI signal connection HDMI display interface of SM768 chip.
Preferably, the PCI-E3.0X8 interface is connected with a PCI-E3.0X8 signal of a Feiteng processor PEU1_ X8a interface; the PCI-E to gigabit network control chip is 82599, and two KX4 signals of the 82599 chip are connected with a gigabit Ethernet interface.
Preferably, the master gigabit network PHY chip employs a JEM88E1111 chip, and an MDI signal of the JEM88E1111 chip is connected to the master gigabit ethernet interface; the management gigabit network PHY chip adopts a JEM88E1111 chip, and the MDI signal of the JEM88E1111 chip is connected with a management gigabit RJ45 network port; the Feiteng processor is connected with a serial port level conversion chip through a URAT interface, the serial port level conversion chip is an LC3232 chip, and URAT signals of the LC3232 chip are connected with a serial port; the Feiteng processor is connected with a CAN level conversion chip through a CAN interface, the CAN level conversion chip adopts an SM82C250 chip, and a CAN signal of the SM82C250 chip is connected with the CAN interface; the Feiteng processor is connected with a BIOS chip through an SPI interface, and the BIOS chip adopts a W25Q128FW chip; the Feiteng processor is connected with a real-time clock chip through an IIC interface, and the real-time clock chip is a BL5372 chip.
Compared with the prior art, the invention has the following beneficial effects:
1. the memory of the main control device adopts a DDR4SODIMM memory slot mode, the problem that the traditional main control device adopts an onboard memory particle mode to occupy large area of a printed board to cause difficult layout and wiring is solved, the area of the printed board occupied by the memory is reduced by more than 70%, the memory capacity is improved by 1 time, and the capacity can be further improved by subsequently flexibly replacing a memory bank;
2. the main control device provided by the invention has various interfaces such as SRIO,10GbE, PCI-E and SATA, and the VPX server based on the main control device has the characteristics of high reliability, high bandwidth, high performance, complete interfaces, strong universality, strong expansion capability and the like, is suitable for the fields of networks, telecommunications, national defense, industry and the like, and can excellently complete tasks such as calculation, communication, control and the like;
3. the master control device suitable for the VPX architecture server provided by the invention can adopt a domestic Feiteng processor, can carry domestic Kunlun firmware, runs a domestic Galaxy kylin operating system, is used as the core of the VPX server, realizes independent controllability of software and hardware ecological chains, primarily twists the situation that the software and hardware of the VPX server in China are limited by people for a long time, and eliminates potential safety hazards caused by using the foreign software and hardware.
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Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic view of the overall structure of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 1, a master control apparatus for a VPX architecture server according to the present invention includes: the system comprises a processor, a DDR4SODIMM memory slot, a DDR4SODIMM memory bank, a PCI-E to USB chip, a PCI-E to SATA chip, a PCI-E to SRIO chip and an SRIO exchange chip; the processor is connected with a DDR4SODIMM memory slot, a PCI-E to USB chip, a PCI-E to SATA chip and a PCI-E to SRIO chip; the DDR4SODIMM memory slot is connected with a DDR4SODIMM memory bar; the PCI-E to USB chip outputs a USB3.0 interface; the PCI-E to SATA chip outputs an M.2 interface and an SATA3.0 interface; the PCI-E to SRIO chip is connected with the SRIO switching chip; and the SRIO exchange chip outputs an SRIO2.0 interface.
Preferably, the method further comprises the following steps: the device comprises a display chip, a PCI-E (peripheral component interconnect-express) gigabit network control chip, a master control gigabit network PHY chip, a management gigabit network PHY chip, a serial port level conversion chip, a CAN (controller area network) level conversion chip, a BIOS (basic input output system) chip and a real-time clock chip; the processor is connected with the display chip, the PCI-E3.0X8 interface, the PCI-E gigabit network control chip, the master control gigabit network PHY chip, the management gigabit network PHY chip, the serial port level conversion chip, the CAN level conversion chip, the BIOS chip and the real-time clock chip; the display chip outputs a VGA display interface and an HDMI display interface; the PCI-E to gigabit network control chip outputs a gigabit Ethernet interface; the master control gigabit network PHY chip outputs a master control gigabit Ethernet interface; the management kilomega network PHY chip outputs a management kilomega network port; the serial port level conversion chip outputs a serial port; the CAN level conversion chip outputs a CAN interface; the processor adopts a Feiteng processor; the FT processor adopts an FT-2000/4 processor; the Feiteng processor is integrated with 6 paths of PCI-E3.0 interfaces including a PEU0_ X1, a PEU0_ X8a, a PEU0_ X8b, a PEU1_ X1, a PEU1_ X8a and a PEU1_ X8 b.
Preferably, the PEU0_ X1 is connected with a PCI-E-to-USB chip; the PEU0_ X8a is connected with a PCI-E to SATA chip; the PEU0_ X8b is connected with a PCI-E to SRIO chip; the PEU1_ X1 is connected with a display chip; the PEU1_ X8a is connected with a PCI-E3.0X8 interface; the PEU1_ X8b is connected with a PCI-E to ten-trillion network control chip.
Preferably, the Feiteng processor further integrates a 2-way DDR4 memory controller; the 2-way DDR4 memory controller is externally connected with 2 DDR4SODIMM memory banks through DDR4SODIMM memory slots; the processor also integrates RGMII0 and RGMII1 into a 2-way RGMII interface, wherein RGMII0 connects the master gigabit network PHY chip and RGMII1 connects the management gigabit network PHY chip.
Preferably, the PCI-E to USB chip adopts a TUSB7340 chip; the four paths of USB3.0 signals of the TUSB7340 chip are connected with the USB3.0 interface.
Preferably, the PCI-E to SATA chip adopts an 88SE9215 chip; the 88SE9215 chip outputs four paths of SATA3.0 signals; the four SATA3.0 signals include: -SATA0 signal; -SATA1 signal; -SATA2 signal; -SATA3 signal; the SATA0 is in signal connection with an M.2 interface; the SATA1 signal, the SATA2 signal and the SATA3 signal are connected with a SATA3.0 interface.
Preferably, the PCI-E to SRIO chip adopts a TSI721 chip; the TSI721 chip realizes the interconversion between the PCI-E2.1 protocol and the SRIO2.1 protocol; and the SRIO2.1X4 signal of the TSI721 chip is connected with the SRIO exchange chip.
Preferably, the SRIO switching chip adopts a CPS1432 chip, the CPS1432 chip has 8-path SRIO2.1X4 signal switching capability, and four paths of SRIO2.1X4 signals of the CPS1432 chip are connected to an SRIO2.1X4 interface; the display chip adopts SM768 chip, the VGA signal connection VGA display interface of SM768 chip, the HDMI signal connection HDMI display interface of SM768 chip.
Preferably, the PCI-E3.0X8 interface is connected with a PCI-E3.0X8 signal of a Feiteng processor PEU1_ X8a interface; the PCI-E to gigabit network control chip is 82599, and two KX4 signals of the 82599 chip are connected with a gigabit Ethernet interface.
Preferably, the master gigabit network PHY chip employs a JEM88E1111 chip, and an MDI signal of the JEM88E1111 chip is connected to the master gigabit ethernet interface; the management gigabit network PHY chip adopts a JEM88E1111 chip, and the MDI signal of the JEM88E1111 chip is connected with a management gigabit RJ45 network port; the Feiteng processor is connected with a serial port level conversion chip through a URAT interface, the serial port level conversion chip is an LC3232 chip, and URAT signals of the LC3232 chip are connected with a serial port; the Feiteng processor is connected with a CAN level conversion chip through a CAN interface, the CAN level conversion chip adopts an SM82C250 chip, and a CAN signal of the SM82C250 chip is connected with the CAN interface; the Feiteng processor is connected with a BIOS chip through an SPI interface, and the BIOS chip adopts a W25Q128FW chip; the Feiteng processor is connected with a real-time clock chip through an IIC interface, and the real-time clock chip is a BL5372 chip.
The memory of the main control device adopts a DDR4SODIMM memory slot mode, the problem that the traditional main control device adopts an onboard memory particle mode to occupy large area of a printed board to cause difficult layout and wiring is solved, the area of the printed board occupied by the memory is reduced by more than 70%, the memory capacity is improved by 1 time, and the capacity can be further improved by subsequently flexibly replacing a memory bank; the main control device provided by the invention has various interfaces such as SRIO,10GbE, PCI-E and SATA, and the VPX server based on the main control device has the characteristics of high reliability, high bandwidth, high performance, complete interfaces, strong universality, strong expansion capability and the like, is suitable for the fields of networks, telecommunications, national defense, industry and the like, and can excellently complete tasks such as calculation, communication, control and the like; the master control device suitable for the VPX architecture server provided by the invention can adopt a domestic Feiteng processor, can carry domestic Kunlun firmware, runs a domestic Galaxy kylin operating system, is used as the core of the VPX server, realizes independent controllability of software and hardware ecological chains, primarily twists the situation that the software and hardware of the VPX server in China are limited by people for a long time, and eliminates potential safety hazards caused by using the foreign software and hardware.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. A master control device suitable for a VPX architecture server, comprising: the system comprises a processor, DDR4SODIMM memory slots, DDR4SODIMM memory banks, a PCI-E to USB chip, a PCI-E to SATA chip, a PCI-E to SRIO chip and an SRIO exchange chip;
the processor is connected with a DDR4SODIMM memory slot, a PCI-E to USB chip, a PCI-E to SATA chip and a PCI-E to SRIO chip;
the DDR4SODIMM memory slot is connected with a DDR4SODIMM memory bank;
the PCI-E to USB chip outputs a USB3.0 interface;
the PCI-E to SATA chip outputs an M.2 interface and an SATA3.0 interface;
the PCI-E to SRIO chip is connected with the SRIO switching chip;
and the SRIO exchange chip outputs an SRIO2.0 interface.
2. The master control apparatus adapted to a VPX architecture server according to claim 1, further comprising: the device comprises a display chip, a PCI-E (peripheral component interconnect-express) gigabit network control chip, a master control gigabit network PHY chip, a management gigabit network PHY chip, a serial port level conversion chip, a CAN (controller area network) level conversion chip, a BIOS (basic input output system) chip and a real-time clock chip;
the processor is connected with the display chip, the PCI-E3.0X8 interface, the PCI-E gigabit network control chip, the master control gigabit network PHY chip, the management gigabit network PHY chip, the serial port level conversion chip, the CAN level conversion chip, the BIOS chip and the real-time clock chip;
the display chip outputs a VGA display interface and an HDMI display interface;
the PCI-E to gigabit network control chip outputs a gigabit Ethernet interface;
the master control gigabit network PHY chip outputs a master control gigabit Ethernet interface;
the management kilomega network PHY chip outputs a management kilomega network port;
the serial port level conversion chip outputs a serial port;
CAN level conversion chip output CAN interface
The processor adopts a Feiteng processor;
the FT processor adopts an FT-2000/4 processor;
the Feiteng processor is integrated with 6 paths of PCI-E3.0 interfaces including a PEU0_ X1, a PEU0_ X8a, a PEU0_ X8b, a PEU1_ X1, a PEU1_ X8a and a PEU1_ X8 b.
3. The master control device suitable for a VPX architecture server of claim 2, wherein the PEU0_ X1 is connected to a PCI-E to USB chip;
the PEU0_ X8a is connected with a PCI-E to SATA chip;
the PEU0_ X8b is connected with a PCI-E to SRIO chip;
the PEU1_ X1 is connected with a display chip;
the PEU1_ X8a is connected with a PCI-E3.0X8 interface;
the PEU1_ X8b is connected with a PCI-E to ten-trillion network control chip.
4. The master control device suitable for a VPX architecture server of claim 2, wherein the Feiteng processor further integrates a 2-way DDR4 memory controller;
the 2-path DDR4 memory controller is externally connected with 2 DDR4SODIMM memory banks through DDR4SODIMM memory slots;
the processor also integrates RGMII0 and RGMII1 into a 2-way RGMII interface, wherein RGMII0 connects the master gigabit network PHY chip and RGMII1 connects the management gigabit network PHY chip.
5. The master control device suitable for a VPX architecture server of claim 1, wherein the PCI-E to USB chip adopts a TUSB7340 chip;
the four paths of USB3.0 signals of the TUSB7340 chip are connected with the USB3.0 interface.
6. The master control device applicable to a VPX architecture server of claim 1, wherein the PCI-E to SATA chip is 88SE9215 chip;
the 88SE9215 chip outputs four paths of SATA3.0 signals;
the four SATA3.0 signals include:
-SATA0 signal;
-SATA1 signal;
-SATA2 signal;
-SATA3 signal;
the SATA0 is in signal connection with an M.2 interface;
the SATA1 signal, the SATA2 signal and the SATA3 signal are connected with a SATA3.0 interface.
7. The master control device suitable for the VPX architecture server of claim 1, wherein the PCI-E to SRIO chip adopts TSI721 chip;
the TSI721 chip realizes the interconversion between the PCI-E2.1 protocol and the SRIO2.1 protocol;
and SRIO2.1X4 signals of the TSI721 chip are connected with the SRIO switching chip.
8. The master control device suitable for the VPX architecture server as claimed in claim 2, wherein the SRIO switch chip adopts a CPS1432 chip, the CPS1432 chip has 8-way SRIO2.1X4 signal switching capability, and the four-way SRIO2.1X4 signal of the CPS1432 chip is connected with SRIO2.1X4 interface;
the display chip adopts SM768 chip, the VGA signal connection VGA display interface of SM768 chip, the HDMI signal connection HDMI display interface of SM768 chip.
9. The master control device suitable for a VPX architecture server of claim 2, wherein the PCI-E3.0X8 interface is connected to PCI-E3.0X8 signal of the Feiteng processor PEU1_ X8a interface;
the PCI-E to gigabit network control chip is 82599, and two KX4 signals of the 82599 chip are connected with a gigabit Ethernet interface.
10. Master control arrangement adapted for a VPX architecture server according to claim 2,
the master control gigabit network PHY chip adopts a JEM88E1111 chip, and the MDI signal of the JEM88E1111 chip is connected with a master control gigabit Ethernet interface;
the management gigabit network PHY chip adopts a JEM88E1111 chip, and the MDI signal of the JEM88E1111 chip is connected with a management gigabit RJ45 network port;
the Feiteng processor is connected with a serial port level conversion chip through a URAT interface, the serial port level conversion chip is an LC3232 chip, and URAT signals of the LC3232 chip are connected with a serial port;
the Feiteng processor is connected with a CAN level conversion chip through a CAN interface, the CAN level conversion chip adopts an SM82C250 chip, and a CAN signal of the SM82C250 chip is connected with the CAN interface;
the Feiteng processor is connected with a BIOS chip through an SPI interface, and the BIOS chip adopts a W25Q128FW chip;
the Feiteng processor is connected with a real-time clock chip through an IIC interface, and the real-time clock chip is a BL5372 chip.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113609046A (en) * | 2021-07-13 | 2021-11-05 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Storage device suitable for VPX framework server and VPX framework server |
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