CN106951383A - The mainboard and method of a kind of raising PCIE data channel utilization rates - Google Patents
The mainboard and method of a kind of raising PCIE data channel utilization rates Download PDFInfo
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- CN106951383A CN106951383A CN201710258574.2A CN201710258574A CN106951383A CN 106951383 A CN106951383 A CN 106951383A CN 201710258574 A CN201710258574 A CN 201710258574A CN 106951383 A CN106951383 A CN 106951383A
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- 238000001514 detection method Methods 0.000 claims description 3
- 238000012905 input function Methods 0.000 claims description 3
- 238000003780 insertion Methods 0.000 description 11
- 230000037431 insertion Effects 0.000 description 11
- 238000013461 design Methods 0.000 description 10
- 239000002699 waste material Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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Abstract
The invention provides a kind of mainboard of raising PCIE data channel utilization rates and method, mainboard includes port number and lanes quantity the first slot of identical of root bridge device, the lanes of described bridge device is all connected with the first slot, and all lanes of other PCIE slots contact is linked in sequence on the first slot on respective numbers lanes contact successively；PCH GPIO is connected with the signal in place of each PCIE slot respectively, is pulled up outside all GPIO signals by resistance R；The signal wire being connected with each slot is by resistance eutral grounding；BIOS program obtains signal PRSNT1# in place during starting up according to GPIO, obtains the quantity of PCIE device, configures the data channel width of root bridge device.Technical scheme, according to the situation in place of slot equipment, configures the width of bridge device, bridge device width is obtained maximized utilization rate.
Description
Technical field
The invention belongs to mainboard and the side of field of computer technology, more particularly to a kind of raising PCIE data channel utilization rates
Method.
Background technology
On mainboard, PCIE each data passage is called a Lane, by sending signal Tx and reception signal Rx groups
Into.The PCIE data channel Lane of the processor of different frameworks quantity is different, typically between 16 to 48 Lanes, data
16 Lanes can be configured to one group by passage maximum, 8 Lanes can also be configured to one group, minimum can be by 4
Lanes is configured to one group.After configuration is good, each group can link an outside PCIE device.Processor has been possible to multiple
Bridge device, so that processor one has 16 Lanes bridge device as an example, mainboard can design four kinds of configurations, configure 1 one x16
Slot, either configure 2 two x8 slot or configure 3 one x8 and two x4 slot, or 4 four x4 of configuration
Slot.
It is necessary to which which kind of specifically used configuration selected during motherboard design, design mainboard selectes PCIE with postponing, produces material object
After mainboard, it is not possible to hardware PCIE slots are modified again.If client insertion mainboard PCIE device width just and
The Breadth Maximum that PCIE slots are supported is consistent, could carry out maximization to PCIE data channel and use, but mainboard is in client
Applicable cases are numerous, and the situation of PCIE slot access devices is varied, and the limitation for PCIE data channel is wasted, and is just compared
It is common.The bridge device for having a 16 data passage Lanes of such as processor, when option and installment 1, has one on mainboard
Individual width is x16 PCIE slot interfaces, and client may be inserted into width x16 and following PCIE device, when client needs insertion
When width is x1 PCIE device, other 15 data passages will be idle waste, even if needing to meet x1 PCIE again
Equipment can not also be realized；There are the PCIE slot interfaces that two width are x8 when option and installment 2, on mainboard, client may be inserted into
Width x8 and following PCIE device, when it is x1 PCIE device that client, which needs insertion width, two slots, which amount to, 14
Data channel is idle to be wasted, while client operates in width if necessary will insert mainboard for x16 PCIE devices, is also
It is irrealizable；There are x8 and two x4 PCIE slot interfaces when option and installment 3, on mainboard, client may be inserted into three
X1 PCIE device is opened, there will be the idle waste of 13 data passages, while a width x16 can not be accessed on mainboard or same
When two width x8 PCIE device；There are four PCIE slot interfaces when option and installment 4, on mainboard, client can access four
X1 PCIE device is opened, there will be the idle waste of 12 data passages, while width can not be inserted for x16 or x8 PCIE device
Enter mainboard.As can be seen here, the PCIE socket designs of current mainboard, to the PCIE device flexible Application of client, limitation and idle wave
Expense is all than more serious.
The content of the invention
For above technical problem, the invention discloses a kind of mainboard of raising PCIE data channel utilization rates and method,
Designed by hardware circuit design and BIOS program, according to the PCIE device width of insertion slot, realize that PCIE data channel makes
Maximized with rate.
In this regard, the technical solution adopted by the present invention is：
A kind of mainboard of raising PCIE data channel utilization rates, it includes the integrated South Bridge chips of PCH, mainboard processor and BIOS bases
This input/output module；The data channel lanes of the root bridge device of mainboard processor quantity is n；PCIE slots on mainboard
For m, including port number and lanes quantity the first slot of identical of root bridge device, the lanes of described bridge device is complete
Portion is connected with the first slot, and all lanes of other PCIE slots contact is linked in sequence corresponding on the first slot successively
On quantity lanes contact；
The integrated South Bridge chips of PCH include m GPIO, respectively GPIO0~GPIOm-1, the GPIO0~GPIOm-1Respectively with each
The signal PRSNT1# in place electrical connections of PCIE slots, and be connected outside all GPIO signals by resistance R with pull-up power supply
Pulled up；The signal wire being connected with each slot lanes is by resistance eutral grounding；
BIOS program is during starting up, the signal PRSNT1# in place obtained according to GPIO, obtains the number of PCIE device
Amount, so as to configure the data channel width of root bridge device.
For current processor, the n is 16 or 8.
Using this technical scheme, PCIE data channel can be fully used as needed, various PCIE devices are flexibly tackled
Use.GPIO0 ~ GPIOm-1, is linked to the signal in place of each PCIE slot respectively（PRSNT1#）Above, all GPIO letters
Extra portion is pulled up by resistance R, if all slots do not have an equipment insertion, all GPIO input high levels signals,
If PCIE device is inserted into slot, PRSNT1#, which is dragged down, indicates PCIE device in slot.
As a further improvement on the present invention, the PCIE slots on the mainboard include width less than the second of the first slot
Slot, the 3rd slot and the 4th slot, the width of second slot are more than the 3rd slot and the 4th slot, and described second inserts
Groove, the lanes of the 3rd slot contact are linked in sequence on the lanes of the respective width of the first slot contact successively；It is described
The lanes of 4th slot contact is linked in sequence successively with the lanes of the respective width of the second slot contact respectively.
As a further improvement on the present invention, every data passage lanes of the root bridge device of mainboard processor Tx and
DN and DP signals and PCIE slot contact portion, DN the and DP signal and PCIE slot contact of the Rx by differential signal line
Position lead line be grounded by resistance R.
This technical scheme, per data passage lane, is made up of, Tx and Rx signals are all DP Tx and Rx（Data
Positive）And DN（Data Negative）Difference signal pair, therefore every lane has four signal lines.Data channel
When having data transfer above lane, what DN and DP were transmitted above is symmetrical rectangle square wave, by every lane DN and DP signals
With the position of slot contact point, lead line is grounded by resistance R, when there is equipment in slot, DN and DP transmission square-wave signals,
Earth resistance is on signal quality without influence, and when slot does not have equipment, DN and DP signals are grounded by resistance R, to other slot strings
Joining DN the and DP signals come does not influence.
It is preferred that, all slot all of the above lanes are grounded by resistance R.
As a further improvement on the present invention, the n is 16, and first slot is x16, and second slot is x8,
3rd slot and the 4th slot are x4, all lanes of second slot contact respectively successively with the first slot
9th article of all contact portions to the 16th article of lanes；Inserted successively with first respectively all lanes of 3rd slot contact
The 5th article of lanes to the 8th articles of lanes of groove all contact portions；All lanes of 4th slot contact respectively according to
Secondary the 5th article of lanes to the 8th articles of lanes with the second slot all contact portions.
After so designing, possess the ability of four kinds of designs of configuration above, may be inserted into the PCIE that 1 width is x16 and set
It is standby, the PCIE device that 2 width are x8 or the equipment that 1 width x8 of insertion and 2 width are x4 are either inserted, or insert
Enter the PCIE device that 4 width are x4 or x1, fully use PCIE data channel, flexibly tackle making for various PCIE devices
With.
As a further improvement on the present invention, the PCIE slots on the mainboard include the first slot and the second slot, institute
It is 8 to state n, and first slot is x8, and second slot is x4, and the lanes of second slot contact is suitable successively respectively
Sequence and the 5th article of lanes to the 8th articles of all contact portions of lanes of the first slot.
A kind of method of raising PCIE data channel utilization rates, mainboard is using raising PCIE numbers as above described in any one
According to the mainboard of passage utilization rate, the method for the raising PCIE data channel utilization rates comprises the following steps：
Step S1, starts BIOS program, initializes GPIO, GPIO0 ~ GPIOm-1 is set into input function, then read
The data value of GPIO0 ~ GPIOm-1 inputs, obtains the signal PRSNT1# in place of PCIE slots；
The signal PRSNT1# in place of step S2, PCIE slot passes to the basic input/output modules of BIOS by GPIO, according to each
The situation in place of individual slot equipment, BIOS program configures the width of bridge device.
Using this technical scheme, designed by hardware circuit design and BIOS program, according to the PCIE device of insertion slot
Width, realizes that PCIE data channel utilization rate is maximized.In this method, PCIE device number is detected by BIOS program start process
Amount and width, the data channel width of flexible configuration root bridge device, are allowed to and the external apparatus PC IE data channel width goodnesses of fit
Optimize, fully using the PCIE data channel of root bridge device, while inserting different PCIE device demands to client reaches maximum
Change and meet.
As a further improvement on the present invention, in step S1, the data value inputted according to GPIO0 ~ GPIOm-1 is detected
GPIO0 ~ GPIOm-1 incoming level situation；In step S2, if all GPIO0 ~ GPIOm-1 level is high level,
All slots do not have any PCIE device to insert, and the basic input/output modules of BIOS match somebody with somebody the default bandwidth that is configured to of bridge device
Put；When low level occurs in GPIO0 ~ GPIOm-1 level, then there is PCIE device access, the basic input/output modules of BIOS are matched somebody with somebody
The bandwidth of root bridge device is put, all PCIE devices is connected and completes initialization.
As a further improvement on the present invention, the n is 4 for 16, m, and the PCIE slots on the mainboard are included with a width of
X16 the first slot, the second slot with a width of x8, with a width of x4 the 3rd slot and the 4th slot；Second slot
The 9th article of all contact portions to the 16th article of lanes of all lanes contact respectively successively with the first slot；Described 3rd
All contact portions of all lanes of slot contact respectively successively with the 5th article of lanes to the 8th articles of lanes of the first slot；
All lanes of 4th slot contact is all with the 5th article of lanes to the 8th articles of lanes of the second slot successively respectively
Contact portion；The basic input/output modules of BIOS configure the width of root bridge device in the following ways：
When four slots have equipment, the PRSNT1# of four slots is dragged down, and is configured to x4 x4 x4 x4；
When only first slot has equipment, width configuration x16；
When the first slot and the 3rd slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4 x4 x4 x4；
When the first slot and the second slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8 x8；
When the first slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8 x4 x4；
When only the 3rd slot has equipment, width configuration x4 x4 x4 x4；
When the 3rd slot and the second slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4 x4 x8；
When the 3rd slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4 x4 x4 x4；
When only the second slot has equipment, width configuration x8 x8；
When the second slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8 x4 x4；
When only the 4th slot has equipment, width configuration x8 x4 x4.
Compared with prior art, beneficial effects of the present invention are：
First, technical scheme is designed by hardware circuit design and BIOS program, is set according to the PCIE of insertion slot
Standby width, realizes that PCIE data channel utilization rate is maximized.I.e. by BIOS program start process detect PCIE device quantity and
Width, the data channel width of flexible configuration root bridge device is allowed to optimal with the external apparatus PC IE data channel width goodnesses of fit
Change, fully using the PCIE data channel of root bridge device, while different PCIE device demands are inserted to client reaches that maximization is full
Foot.
Second, technical scheme, by DN and DP differential signal lines and slot contact point, lead connecting resistance R is arrived
The mode on ground, the hardware design of innovation, then signal PRSNT1# in place is passed into BIOS program by GPIO, inserted according to each
The situation in place of groove equipment, allows the width of BIOS program flexible configuration bridge device, bridge device width is obtained maximized use
Rate, gives full play to the performance of processor, fully meets the diversified demand of client.
Brief description of the drawings
Fig. 1 is the attachment structure schematic diagram of the PCIE slots of an embodiment of the present invention.
Fig. 2 is the attachment structure schematic diagram of the PCIE slots and PCH and mainboard processor of an embodiment of the present invention.
Fig. 3 is the flow chart of the BIOS program Part Methods of an embodiment of the present invention.
Embodiment
The preferably embodiment to the present invention is described in further detail below.
Embodiment 1
So that one of processor has 16 lanes root bridge devices as an example, 16 lanes, minimal configuration is 4 lanes.Using this
The mainboard of the raising PCIE data channel utilization rates of invention includes hardware circuit part and BIOS program part.
（1）Hardware circuit part
As shown in Fig. 1 ~ Fig. 2, the PCIE slots on the mainboard include the first slot 1 with a width of x16, second with a width of x8
Slot 2, with a width of x4 the 3rd slot 3 and the 4th slot 4；16 articles of lanes of mainboard processor are all linked to first
Above one slot 1, second group of 4 lanes is linked to above the second slot 2, third and fourth group of 8 lanes is linked to
Above 3rd slot 3, while 4 articles of lanes of the 4th slot are linked to above the 4th slot 4.I.e. described second slot 2 it is all
The 9th article of all contact portions to the 16th article of lanes of lanes contact respectively successively with the first slot 1；3rd slot
All contact portions of 3 all lanes contact respectively successively with the 5th article of lanes to the 8th articles of lanes of the first slot 1；Institute
The contact for stating all lanes of the 4th slot 4 is all with the 5th article of lanes to the 8th articles of lanes of the second slot 3 successively respectively
Contact portion.After so designing, possess the first slot 1 of configuration, the second slot 2, the 3rd slot 3,4 four kinds of the 4th slot above
The ability of design, may be inserted into the PCIE device that 1 width is x16, either insert 2 width for x8 PCIE device or
The equipment that 1 width x8 and 2 width are x4, or the PCIE device that 4 width of insertion are x4 or x1 are inserted, is fully used
PCIE data channel, flexibly tackles the use of various PCIE devices.In Fig. 1, the lanes of slot head and the tail connection illustrate only
Line, other lanes of slot are also such connection.
As shown in Fig. 2 so that one of processor has 16 lanes bridge device as an example, 4 GPIO are selected, GPIO0 ~
GPIO3, is linked to the signal in place of x16 slots, x4 slots, x8 slots, x4 slots respectively（PRSNT1#）Above, all GPIO
Pulled up outside signal by resistance R, the situation for the slot being wherein connected with GPIO0 is only depicted in Fig. 2, other slots
It is also such.If all slots do not have equipment insertion, all GPIO input high levels signals, if PCIE device is inserted
Into slot, PRSNT1#, which is dragged down, indicates PCIE device in slot.
As shown in Fig. 2 per data passage lane, being made up of Tx and Rx, Tx and Rx signals are all DP（Data
Positive）And DN（Data Negative）Difference signal pair, therefore every lane has four signal lines.Data channel
When having data transfer above lane, what DN and DP were transmitted above is symmetrical rectangle square wave, by every lane DN and DP signals
With the position of slot contact point, lead line is grounded by resistance R, when there is equipment in slot, DN and DP transmission square-wave signals,
Earth resistance is on signal quality without influence, and when slot does not have equipment, DN and DP signals are grounded by resistance R, to other slot strings
Joining DN the and DP signals come does not influence.First slot, the second slot, the 3rd slot, the 4th slot all of the above lanes
It is grounded by resistance R.
（2）BIOS program part
So that one of processor has 16 lanes bridge device as an example, as shown in figure 3, after BIOS program starts, first just
Beginningization GPIO, input function is set to by GPIO0 ~ GPIO3, then reads the data value of GPIO0 ~ GPIO3 inputs, detection
GPIO0 ~ GPIO3 incoming level situation, if all level are high level, all slots do not have any equipment to insert,
Bridge device is configured to acquiescence width configuration, such as x4x4x4x4 is configured, and when there is equipment access, situation is relatively more, due to
It is corresponding during GPIO and PRSNT# signals, just illustrated with PRSNT# signals, more understood.
1）When four slots have equipment, four slot PRSNT1# are dragged down, and are configured to x4x4x4x4；
2）When only first slot has equipment, width configuration x16；
3）When first slot and second slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to
x4x4x4x4；
4）When first slot and the 3rd slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8x8；
5）When first slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8x4x4；
6）When only second slot has equipment, width configuration x4x4x4x4；
7）When second slot and the 3rd slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4x4x8；
8）When second slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to
x4x4x4x4；
9）When only the 3rd slot has equipment, width configuration x8x8；
10）When the 3rd slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8x4x4；
11）When only the 4th slot has equipment, width configuration x8x4x4；
All slot insertion equipment situations, the width configuration situation of root bridge device are covered above.Configure bridge device width
After, start to link PCIE device, and Initialize installation is carried out, complete PCIE device function.
Involved Essential Terms are explained as follows in the present invention：
BIOS (Basic Input Output System)：Basic input output system, is mainly used in computer booting process
In various hardware devices initialization and detection.
PCH (Platform Controller Hub)：The integrated south bridge of Intel Company.
PCIE（PCI-Express）：A kind of high-speed serial bus interfacing standard.
GPIO（General Purpose Input Output）：Universal input/output.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to assert
The specific implementation of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (8)
1. a kind of mainboard of raising PCIE data channel utilization rates, it is characterised in that：It includes the integrated South Bridge chips of PCH, mainboard
Processor and the basic input/output modules of BIOS；The data channel lanes of the root bridge device of mainboard processor quantity is n；It is main
PCIE slots on plate are m, including port number and lanes quantity the first slot of identical of root bridge device, described
The lanes of bridge device is all connected with the first slot, and all lanes of other PCIE slots contact is linked in sequence successively
On the contact of respective numbers lanes on one slot；
The integrated South Bridge chips of PCH include m GPIO, respectively GPIO0~GPIOm-1, the GPIO0~GPIOm-1Respectively with each
The signal PRSNT1# in place electrical connections of PCIE slots, and be connected outside all GPIO signals by resistance R with pull-up power supply
Pulled up；The signal wire being connected with each slot lanes is by resistance eutral grounding；
BIOS program is during starting up, the signal PRSNT1# in place obtained according to GPIO, obtains the number of PCIE device
Amount, so as to configure the data channel width of root bridge device.
2. the mainboard of raising PCIE data channel utilization rates according to claim 1, it is characterised in that：On the mainboard
PCIE slots include the second slot, the 3rd slot and the 4th slot that width is less than the first slot, the width of second slot
More than the 3rd slot and the 4th slot, second slot, the lanes of the 3rd slot contact are linked in sequence inserted first successively
On the lanes of the respective width of groove contact；The respective width of the lanes of 4th slot contact respectively with the second slot
Lanes contact be linked in sequence successively.
3. the mainboard of raising PCIE data channel utilization rates according to claim 2, it is characterised in that：Mainboard processor
DN and DP signals and PCIE slot contact of every data passage lanes of the root bridge device Tx and Rx by differential signal line
Connection, DN the and DP signals and the position lead line of PCIE slots contact are grounded by resistance R.
4. the mainboard of raising PCIE data channel utilization rates according to claim 3, it is characterised in that：The n is 16, institute
The first slot is stated for x16, second slot is x8, the 3rd slot and the 4th slot are x4, the institute of second slot
There are the 9th article of all contact portions to the 16th article of lanes of lanes contact respectively successively with the first slot；Described 3rd inserts
All contact portions of all lanes of groove contact respectively successively with the 5th article of lanes to the 8th articles of lanes of the first slot；Institute
Touched successively with all of the 5th article of lanes to the 8th articles of lanes of the second slot respectively the contact for stating all lanes of the 4th slot
Point connection.
5. the mainboard of raising PCIE data channel utilization rates according to claim 1, it is characterised in that：The n is 8, institute
Stating the PCIE slots on mainboard includes the first slot and the second slot, and first slot is x8, and second slot is x4, institute
Distinguish the 5th article of lanes to the 8th articles of all contacts of lanes of order and the first slot successively in the contact for stating the lanes of the second slot
Connection.
6. a kind of method of raising PCIE data channel utilization rates, it is characterised in that：Mainboard is used as claim 1 ~ 5 is any one
The mainboard of raising PCIE data channel utilization rates described in, the method for the raising PCIE data channel utilization rates is including following
Step：
Step S1, starts BIOS program, GPIO is initialized, by GPIO0~GPIOm-1Input function is set to, GPIO is then read0~
GPIOm-1The data value of input, obtains the signal PRSNT1# in place of PCIE slots；
The signal PRSNT1# in place of step S2, PCIE slot passes to the basic input/output modules of BIOS by GPIO, according to each
The situation in place of individual slot equipment, BIOS program configures the width of bridge device.
7. the method for raising PCIE data channel utilization rates according to claim 6, it is characterised in that：In step S1, root
According to GPIO0~GPIOm-1The data value detection GPIO of input0~GPIOm-1Incoming level situation；In step S2, if all
GPIO0~GPIOm-1Level be high level, then all slots do not have any PCIE device to insert, the basic input and output of BIOS
Module is configured to default bandwidth configuration by bridge device；Work as GPIO0~GPIOm-1Level when there is low level, then there is PCIE to set
Standby access, the basic input/output modules of BIOS configure the bandwidth of root bridge device, connect all PCIE devices and complete initialization.
8. the method for raising PCIE data channel utilization rates according to claim 7, it is characterised in that：The n is 16, m
For 4, the PCIE slots on the mainboard include the first slot with a width of x16, the second slot with a width of x8, with a width of x4's
3rd slot and the 4th slot；All lanes of second slot contact respectively successively with the 9th article of the first slot to the
16 lanes all contact portions；Distinguish the 5th article successively with the first slot in all lanes of 3rd slot contact
Lanes to the 8th articles of lanes all contact portions；Inserted successively with second respectively all lanes of 4th slot contact
The 5th article of lanes to the 8th articles of lanes of groove all contact portions；The basic input/output modules of BIOS are in the following ways
Configure the width of root bridge device：
When four slots have equipment, the PRSNT1# of four slots is dragged down, and is configured to x4 x4 x4 x4；
When only first slot has equipment, width configuration x16；
When the first slot and the 3rd slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4 x4 x4 x4；
When the first slot and the second slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8 x8；
When the first slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8 x4 x4；
When only the 3rd slot has equipment, width configuration x4 x4 x4 x4；
When the 3rd slot and the second slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4 x4 x8；
When the 3rd slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x4 x4 x4 x4；
When only the second slot has equipment, width configuration x8 x8；
When the second slot and the 4th slot have equipment, the PRSNT1# of the two slots is dragged down, and is configured to x8 x4 x4；
When only the 4th slot has equipment, width configuration x8 x4 x4.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110347435A (en) * | 2019-07-03 | 2019-10-18 | 英业达科技有限公司 | Automatically configure the BIOS and method of PCIe slot |
| CN111008162A (en) * | 2019-11-22 | 2020-04-14 | 苏州浪潮智能科技有限公司 | Method and system for realizing single PCIE slot supporting multiple PCIE ports |
| CN111177055A (en) * | 2020-01-02 | 2020-05-19 | 英业达科技有限公司 | PCIE slot configuration setting method, system, medium and device |
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| CN111930660A (en) * | 2020-07-30 | 2020-11-13 | 长沙景嘉微电子股份有限公司 | PCIE path configuration method, device, terminal and medium |
| CN113448903A (en) * | 2021-05-21 | 2021-09-28 | 山东英信计算机技术有限公司 | PCIe bandwidth adjustment method, device, equipment and storage medium for NVMe expansion card |
| CN113448903B (en) * | 2021-05-21 | 2023-02-28 | 山东英信计算机技术有限公司 | PCIe bandwidth adjustment method, device, equipment and storage medium for NVMe expansion card |
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