CN111142630A

CN111142630A - Processor board card

Info

Publication number: CN111142630A
Application number: CN201911212269.5A
Authority: CN
Inventors: 田硕磊; 方自春
Original assignee: Hangzhou DPTech Technologies Co Ltd
Current assignee: Hangzhou DPTech Technologies Co Ltd
Priority date: 2019-12-02
Filing date: 2019-12-02
Publication date: 2020-05-12

Abstract

The application provides a processor board card, this processor board card accessible buckle structure installation to mainboard, processor board card includes: the processor is connected with the memory, the CPLD chip, the FLASH memory chip, the clock chip and the connector; the connector comprises a data interaction pin and a power input pin, the data interaction pin is used for enabling the processor board card to realize data interaction with the main board, and the power input pin is used for enabling the main board to supply power to the processor board card. The processor board card is arranged on a network equipment mainboard by adopting a detachable buckle plate structure, and uniform connector signals are regulated, so that the processor board card can be flexibly matched with different mainboards supporting the connector signals for use; in addition, the processor adopts a domestic Feiteng FT-2000 dual-core CPU chip, so that the hardware cost of the processor board card is effectively reduced while autonomous controllability is ensured.

Description

Processor board card

Technical Field

The application relates to the technical field of communication equipment, in particular to a processor board card.

Background

For network devices such as switches and routers, memory configurations and PCB routing on device motherboards of different manufacturers and models are not uniform, so processor boards used in network device products of different models are also different, and therefore when the same processor board is used in different motherboards, code adaptation needs to be performed according to the motherboards, so that the compatibility of the processor board with different motherboards is low, and the use flexibility is poor.

Disclosure of Invention

In view of the above, the present application provides a processor board card to solve the problems of poor compatibility and high cost of the processor board card.

In order to achieve the above purpose, the present application provides the following technical solutions:

the application provides a processor board card, processor board card accessible buckle structure installation to mainboard, processor board card includes: the processor is connected with the memory, the CPLD chip, the FLASH memory chip, the clock chip and the connector; the connector comprises a data interaction pin and a power input pin, the data interaction pin is used for enabling the processor board card to realize data interaction with the main board, and the power input pin is used for enabling the main board to supply power to the processor board card.

According to the technical scheme, the processor board card is connected with the main board through the detachable buckle plate structure, unified connector signals are defined, the processor board card can be flexibly used for the main board of the switch designed and manufactured according to the connector signals, independent adaptive codes are not needed, and therefore board card compatibility and use flexibility are improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without any creative effort.

FIG. 1 is a block diagram of a processor board card according to an exemplary embodiment of the present disclosure.

FIG. 2 is a block diagram illustrating a USB interface and an SD/CF interface of a processor board card according to an exemplary embodiment of the present application.

Fig. 3 is a schematic diagram illustrating a connection between a data interaction pin in a connector and a motherboard device according to an exemplary embodiment of the present application.

Fig. 4 is a schematic diagram illustrating a connection between a connector of a processor board card and a main board device according to an exemplary embodiment of the present application.

FIG. 5 is a schematic diagram of a group A pin header of a processor board card according to an exemplary embodiment of the present application.

FIG. 6 is a schematic diagram illustrating a connector B group pin arrangement of a processor board card according to an exemplary embodiment of the present application.

FIG. 7 is a connector C group pin diagram of a processor board card according to an exemplary embodiment of the present application.

FIG. 8 is a schematic diagram illustrating a connector D group pin arrangement for a processor board card according to an exemplary embodiment of the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first way pin may also be referred to as a second way pin, and similarly, the second way pin may also be referred to as a first way pin without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context. For further explanation of the present application, the following examples are provided. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments that can be derived from the embodiments given herein by a person of ordinary skill in the art are intended to be within the scope of the present disclosure.

FIG. 1 is a block diagram of a processor board card according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the processor board card according to this embodiment may be mounted to a motherboard via a clip structure, and includes: the Device comprises a processor, a memory, a CPLD (Complex Programmable Logic Device) chip, a FLASH memory chip, a clock chip and a connector, wherein the memory, the CPLD chip, the FLASH memory chip, the clock chip and the connector are connected with the processor; the connector comprises a data interaction pin and a power input pin, the data interaction pin is used for enabling the processor board card to realize data interaction with the main board, and the power input pin is used for enabling the main board to supply power to the processor board card.

The processor board card is suitable for network equipment and is connected with a main board of the network equipment through a detachable buckle plate structure, and when the processor board card on the main board needs to be replaced or the main board connected with the processor board card needs to be replaced, the buckle plate interface in a connection state can be disconnected, so that the processor board card is separated from the main board.

In this embodiment, the processor used by the processor board card is a FT-2000 dual-core processor, but other processor chips may be used under the condition that both hardware devices and software functions can meet the requirements.

In this embodiment, as an exemplary embodiment, the memory used by the processor board card may be 9 DDR3(Double Data Rate 3 synchronous dynamic random-access memory, third generation Double Data Rate synchronous dynamic random access memory) memory granules with a width of 8 bits, wherein the last 1 DDR3 granules are used as ECC (error checking and correcting) memory; as another exemplary embodiment, the memory used by the processor board card may also be 5 DDR3 memory granules with a width of 16 bits, wherein the last 1 DDR3 granules are used as ECC memory. The last indicates the last logical sequence of each DDR3 pellet, and since the logical sequence of each DDR3 pellet usually coincides with the physical arrangement sequence thereof, the last logical sequence of each DDR 3578 pellet is also referred to as the last physical arrangement sequence, but it is understood that when the physical arrangement sequence of each DDR3 pellet does not coincide with the logical sequence thereof, the last DDR3 pellet in the logical sequence should be preferentially selected as the EEC memory; of course, other combinations of memory particles are also within the scope of the present application. The DDR3 particles used as ECC memories are used for realizing error checking and correction aiming at the working state of the processor and/or the processor board card so as to avoid processor state errors; the other DDR3 granules are used for temporarily storing the operation data of the processor and the data exchanged with the external memory so as to cooperate with the processor to execute the corresponding program codes.

In one embodiment, the memory includes an SD card and/or a CF card; the processor board card further comprises: a PCIE (peripheral component interconnect express ) to USB (Universal Serial Bus) bridge chip and a USB to SD/CF bridge chip; one end of the PCIE-to-USB bridge chip is connected with the processor, the other end of the PCIE-to-USB bridge chip is connected with the USB-to-SD/CF bridge chip, and the USB-to-SD/CF bridge chip is provided with an SD/CF interface. Fig. 2 is a schematic diagram of an interface of the SD/CF interface, where fig. 2 is a schematic diagram of a USB interface and an SD/CF interface structure of a processor board card according to an exemplary embodiment of the present application. As shown in fig. 2, one end of the PCIE-to-USB bridge is connected to the corresponding pin of the processor, and the other end of the PCIE-to-USB bridge is connected to the USB-to-SD/CF bridge. The PCIE-to-USB bridge chip is used for converting signals of a PCIE standard and signals of a USB standard mutually, and a USB pin on the PCIE-to-USB bridge chip is connected with a USB interface on the mainboard through the connector; the USB-to-SD/CF bridge chip is used for converting signals of a USB standard into signals of an SD/CF standard, and is provided with an SD/CF interface for plugging the SD card and/or the CF card. The memory used by the processor board card may be an SD card and/or a CF card for storing software code executed in the processor. The memory can be only an SD card, only a CF card, or both the SD card and the CF card; when the software code executed in the processor needs to be upgraded or modified, the corresponding SD card and/or CF card can be removed from the SD/CF interface, and the new code is recorded and then reinstalled on the SD/CF interface, so that the loading, upgrading, and/or modifying of the software executed by the processor can be realized by using the memory.

In one embodiment, the CPLD chip used by the processor board card is used to control the reset and power-on sequence of the processor board card; the CPLD chip can be also connected with a watchdog (Watch dog) chip for regularly checking the internal state of the processor and sending a wake-up signal to the processor to wake up the processor under the condition that software running in the processor is in a circulation locking state, thereby ensuring the normal program running of the processor.

In one embodiment, the processor board card uses a FLASH memory chip for storing Boot firmware of the processor; the FLASH memory chip may be 1 SPI FLASH chip of 16MB, or may be another FLASH chip that can satisfy the above-mentioned memory function, which is not limited in this application.

In one embodiment, the processor board card uses a Clock chip to provide a Real Time Clock for the processor board card system and programs running on the processor, and the Clock chip may be a Real Time Clock (RTC) chip. In addition, the processor board card may further have other I2C (Inter-Integrated Circuit Bus) devices, such as a temperature sensing chip for detecting the temperature of the processor board card, a first EEPROM (Electrically Erasable and programmable read only memory) chip for storing information related to the manufacturer, model, date of manufacture, signal standard, etc. of the processor board card, and/or a second EEPROM chip for storing information related to the SPD (Serial detection of module Presence) of the memory, etc., and of course, other I2C devices may also be included. The clock chip and other I2C devices may be integrated into the I2C device module on the processor board card, or may be provided separately from the processor board card, which is not limited in this application.

In an embodiment, the connector on the processor board card includes a data interaction pin and a power input pin, where the data interaction pin is used to enable the processor board card to interact with a main board, and the power input pin is used to enable the main board to supply power to the processor board card.

According to the scheme, the processor board card is connected with the main board through the detachable buckle plate structure, so that the flexibility of connecting the processor board card with the main board is improved; moreover, the processor adopts a domestic FT-2000 dual-core processor chip with lower price, so that the hardware cost of the processor board card is reduced.

Fig. 3 is a schematic diagram illustrating a connection between a data interaction pin in a connector and a motherboard device according to an exemplary embodiment of the present application. The data interaction pins in the connector and the devices on the motherboard to which the data interaction pins are connected will be described with reference to fig. 3. First, it should be clear that the correspondence between the data exchange pins included in the connector, the motherboard devices connected to the pins, and the types of signals transmitted through the pins in this embodiment is defined in the following manner. Referring to fig. 3, the data interaction pin in the connector includes: gigabit Ethernet pin, USB pin, I2C pin, PCIEx4 pin, GPIO pin, RS232 pin, SPI pin and SGMII/SERDES pin, explained in sequence as follows:

and the I2C pin, the I2C pin has at least 2 paths, wherein the first path of I2C pin is used for connecting a CPLD register on the mainboard with the processor, and the second path of I2C pin is used for connecting an I2C device on the mainboard with the processor. The first I2C pin may use a CPLD connected to the pin and located on the motherboard to execute corresponding instructions under the control of the processor, such as data storage, data reading, etc., and may also execute related instructions for program debugging. The I2C device connected to the second pin and located on the motherboard may be a sensor module such as an optical module, a temperature detection module, and/or a humidity detection module, or may be another memory chip, which is not limited in this application.

And the SPI (Serial Peripheral Interface) pin is connected with the CPLD register on the motherboard and the processor, and is used to replace the first I2C pin. The CPLD register connected with the SPI pin and the CPLD register connected with the first path of I2C pin are the same register on the mainboard. According to specific debugging requirements, the SPI pin can be used for replacing the first path I2C pin so as to improve the communication efficiency in the test operation.

And the GPIO (General-purpose input/output) pin has at least 8 channels, wherein 4 channels are used for forming a 1-channel JTAG (Joint Test Action Group) interface so as to connect the CPLD register on the mainboard with the processor, and the other 4 channels are used as extension pins available for a user. The JTAG interface is formed by simulating 4 paths of GPIO pins of the processor, is not a special JTAG interface, and the 4 paths of GPIO pins forming the JTAG interface can be randomly selected from all GPIO pins of the processor and can also be preset into 4 paths of pins; the JTAG interface can be temporarily constructed during use, and can also be constructed in advance before use; the GPLD register connected to the GPIO pin may be a CPLD register on the motherboard connected to the aforementioned SPI pin, or may be another GPLD register on the motherboard, which is not limited in this application.

And a USB pin, where the USB pin is connected to a USB interface on the PCIE-to-USB bridge and a USB interface on the motherboard, and is used to import or export information of the network device, and a structure diagram related to the PCIE-to-USB bridge is shown in fig. 2, which is not described herein again.

The PCIE x4 pin is also used for configuring parameters of the switch chip.

And the RS232(RS-232-C standard serial communication interface) pin is connected with the RS232 interface on the mainboard and the processor and is used for serial port debugging and/or management of the network equipment. The UART serial port signal sent by the processor reaches corresponding equipment such as an RS232 interface on the mainboard through an RS232 pin in the connector so as to realize debugging of the serial port and/or management operation of network equipment.

An SGMII/SERDES pin, where the SGMII/SERDES pin connects the motherboard with a PHY (Physical port) chip external to a first RGMII (Reduced Gigabit Media independent interface) interface of the processor, and is used to provide an uplink data channel for the processor. Uplink data can enter from an SGMII/SERDES interface on the mainboard and reach the processor through an SGMII/SERDES pin in the connector.

And the gigabit Ethernet pins are connected with the processor and the gigabit Ethernet interface on the mainboard. Fig. 4 is a schematic diagram of a gigabit ethernet interface structure of a processor board card according to an exemplary embodiment of the present application. Referring to fig. 4, the connector may further include a PHY chip and a network transformer, where one end of the PHY chip is connected to the second RGMII interface on the processor, and the other end of the PHY chip is electrically connected to the gigabit ethernet pins through the network transformer, so as to form a gigabit ethernet interface on the motherboard, where the gigabit ethernet interface may be an RJ45 interface, and the gigabit ethernet interface may be used as a management interface for a user to manage the network device.

As can be seen from the above solution, the connector on the processor board card is used to connect the processor board card and the main board, and the signal type and the corresponding pins in the connector are defined, so that the data signals between the processor board card and the main board are standardized. The processor board card can be suitable for any main board designed and manufactured according to the signal standard, and code adaptation is not needed when the processor board card is connected with the main board, so that the processor board card can be commonly used among main boards of different models (even different manufacturers) under the same signal standard, and the compatibility and the use flexibility of the processor board card for the main boards are improved.

In addition, referring to fig. 1, the processor board card may further include:

the reset pin is used for transmitting a reset signal sent to the mainboard by the processor; the reset pin is connected with a reset pin of the processor and a reset module on the mainboard, and after the reset module receives a reset signal, relevant equipment on the mainboard is triggered to realize reset.

The state indicating pin is used for transmitting a state indicating signal sent to the mainboard by the processor, so that a state indicating module on the mainboard indicates the running state of the processor board card; the status indication signal is used for indicating the working status of the processor board card. In an exemplary embodiment, the status indication signal is a Light-emitting diode (LED) on/off signal, the LED on/off signal sent by the processor reaches an LED on the motherboard via a connector, so as to control the LED to be turned on/off, and status information of the processor, such as a normal operating status, a fault status, a standby status, an off status, and the like, is transmitted to a user in the LED on/off status.

The pin, P.G (Power Good, the normal signal of Power) pin connection Power module on the mainboard with the treater, be used for the transmission Power module sends for the normal signal of Power of treater, in order to inform the treater Power supply is normal. In an exemplary embodiment, the p.g. signal is only used to indicate that the power supply is normal, and when the power module supplies power to the processor board card and the devices on the motherboard, the power module sends the p.g. signal to the processor to inform the processor that the power supply is normal. In another exemplary embodiment, the p.g. signals include a first p.g. signal indicating that the power supply is normal and a second p.g. signal indicating that the power supply is failed, and when the power module is supplying power to the processor board card and the devices on the motherboard, the power module sends the first p.g. signal to the processor; otherwise, when the power module fails to supply power to any equipment, the power module sends a second P.G. signal to the processor.

And the interrupt pin is connected with the CPLD positioned on the mainboard and the processor and is used for transmitting an interrupt signal reported to the processor by the CPLD, and the interrupt signal is converged to the CPLD by the mainboard. When other equipment on the mainboard generates an interrupt signal, sending the corresponding interrupt signal to the CPLD, and when the CPLD receives an interrupt signal, sending the signal to the processor; when the CPLD receives a plurality of interrupt signals, the signals can be sent to the processor according to a preset interrupt priority.

The physical form corresponding to each pin of the connector may be a pin header or a solder joint located on the connector, and in order to more clearly describe the connector scheme of the processor board card of the present application, the actual pin number corresponding to each pin of the connector is described below with reference to fig. 5. Fig. 5-8 are A, B, C, D four-pin header diagrams of a processor board card connector according to an exemplary embodiment of the present application. The row numbering initials in fig. 5-8 are A, B, C, D in order. Fig. 5-8 are only for illustrating the serial numbers of the pins of the connector, and other peripheral circuits such as the power supply circuit and the timing circuit are not shown in the figure, but should not be omitted when the scheme is applied to ensure the normal operation of the connector, and will not be described herein again. The correspondence between the names of the pins in the connector and the pin numbers of the pin header is shown in table 1 below.

TABLE 1

The pin-to-pin number correspondence listed in table 1 above is valid only for the embodiment shown in fig. 5 and is exemplary. When the scheme of the application is implemented specifically, different corresponding relationships between the pins and the pins can be selected according to specific requirements or hardware equipment conditions, but the changed corresponding relationship does not exceed the protection scope of the scheme of the application.

The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A processor board card mountable to a motherboard via a clip structure, the processor board card comprising: the processor is connected with the memory, the CPLD chip, the FLASH memory chip, the clock chip and the connector; the connector comprises a data interaction pin and a power input pin, the data interaction pin is used for enabling the processor board card to realize data interaction with the main board, and the power input pin is used for enabling the main board to supply power to the processor board card.

2. The processor board card of claim 1, wherein the processor is a FT-2000 dual-core processor.

3. The processor board card of claim 1, wherein the data interaction pins in the connector comprise: gigabit Ethernet pins, USB pins, I2C pins, PCIE x4 pins, GPIO pins, RS232 pins, SPI pins, and SGMII/SERDES pins.

4. The processor board card of claim 3, further comprising:

one end of the PHY chip is connected with the second RGMII interface on the processor, and the other end of the PHY chip is electrically connected with the gigabit Ethernet pin through the network transformer so as to form the gigabit Ethernet interface on the mainboard.

5. The processor board card of claim 3, further comprising:

and one end of the PCIE-to-USB bridge piece is connected with the processor, and the other end of the PCIE-to-USB bridge piece is electrically connected with the USB pin so as to form a USB interface on the mainboard.

6. The processor board card of claim 1, wherein the connector further comprises:

the reset pin is used for transmitting a reset signal sent to the mainboard by the processor;

the state indicating pin is used for transmitting a state indicating signal sent to the mainboard by the processor, so that a state indicating module on the mainboard indicates the running state of the processor board card;

the P.G. pin is connected with the power supply module on the mainboard and the processor and used for transmitting a power supply normal signal sent to the processor by the power supply module so as to inform the processor that the power supply is normal;

and the interrupt pin is connected with the CPLD positioned on the mainboard and the processor and is used for transmitting an interrupt signal reported to the processor by the CPLD, and the interrupt signal is converged to the CPLD by the mainboard.

7. The processor board card of claim 1, wherein the memory comprises: 9 DDR3 memory grains that are 8bit wide, wherein the last 1 DDR3 grain is used as ECC memory; alternatively, 5 DDR3 memory cells that are 16bit wide, with the last 1 DDR3 cell being used as an ECC memory.

8. The processor board card of claim 1, wherein the memory comprises an SD card and/or a CF card; the processor board card further comprises:

PCIE converts USB bridge chip and USB converts SD/CF bridge chip;

one end of the PCIE-to-USB bridge chip is connected with the processor, the other end of the PCIE-to-USB bridge chip is connected with the USB-to-SD/CF bridge chip, and the USB-to-SD/CF bridge chip is provided with an SD/CF interface.

9. The processor board card of claim 1, further comprising:

an I2C device, the I2C device comprising:

at least 1 temperature sensing chip for detecting the temperature of the processor board card;

at least 2 EEPROM chips, wherein a first EEPROM chip is used for storing information of the processor board card; the second EEPROM chip is used for storing SPD information of the memory.

10. The processor board card of claim 1, further comprising:

and the watchdog chip is connected with the processor through the CPLD chip and is used for sending a wake-up signal to the processor to wake up the processor under the condition that software running in the processor is in a circulation locking state.