CN111651401B - Reinforcing method for Feiteng processor board card - Google Patents
Reinforcing method for Feiteng processor board card Download PDFInfo
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- CN111651401B CN111651401B CN202010513208.9A CN202010513208A CN111651401B CN 111651401 B CN111651401 B CN 111651401B CN 202010513208 A CN202010513208 A CN 202010513208A CN 111651401 B CN111651401 B CN 111651401B
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 230000003014 reinforcing effect Effects 0.000 title claims abstract description 25
- 230000002787 reinforcement Effects 0.000 claims abstract description 20
- 238000004891 communication Methods 0.000 claims abstract description 11
- 238000005476 soldering Methods 0.000 claims abstract description 9
- 238000003466 welding Methods 0.000 claims description 13
- 101100205847 Mus musculus Srst gene Proteins 0.000 claims description 3
- 238000009434 installation Methods 0.000 abstract description 12
- 238000013461 design Methods 0.000 abstract description 7
- 230000006870 function Effects 0.000 description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000009131 signaling function Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
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- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
A reinforcement method of a Feiteng processor board card comprises the steps of installing a processor, a DDR RAM, a FLASH and a power management module on the board card; soldering the board card to the base plate; stamp hole bonding pads and connectors are arranged on the board card to realize communication between the board card and the bottom plate; the connector and the stamp hole bonding pad are in signal connection with the processor, the DDR RAM, the FLASH and the power management module; stamp hole pads are arranged at the edges of the periphery of the board card. The reinforcing method is reasonable in design, convenient and reliable, and through the arrangement of the stamp hole bonding pad and the connector, not only is reinforcing installation of the board card and the bottom plate realized, but also communication between the board card and the bottom plate is ensured.
Description
Technical Field
The invention relates to the technical field of processors, in particular to a reinforcing method of a Feiteng processor board card.
Background
At present, the communication between the board card and the bottom board generally adopts a stamp hole welding method, an SO-DIMM method and a com express method.
The stamp hole welding method is to manufacture stamp hole welding discs on four sides of the board card, and weld the stamp hole welding discs to the welding discs at corresponding positions on the bottom plate through soldering tin;
the SO-DIMM method is that a golden finger pin is manufactured on one side of a board card, an SO-DIMM slot is arranged on a bottom board, and the installation is carried out in an installation mode similar to that of a memory bar of a notebook computer;
the com express method is that a com express A slot is arranged on the bottom surface of a board card, a com express B slot is arranged on a bottom plate, four positioning through holes are arranged near four right-angle sides of the board card for improving the defect of shock resistance vibration energy, four positioning through holes are also arranged at corresponding positions of the bottom plate, and locking and reinforcing are carried out between the board card and the bottom plate through stud nuts.
However, there are some drawbacks to all three of the above methods:
the stamp hole welding method cannot solve the bus transmission of PCI-E based on the high-speed serial differential signal;
the SO-DIMM method cannot solve the problem of strengthening shock and vibration;
the com express method adopts the com express A/B connector to be in butt joint installation, so that the height of components can be increased, the product application with severe requirements on space installation can not be met, the cost loss of the com express A/B connector is required to be additionally paid for the product application without a PCI-E bus, and in addition, the installation method for reinforcement is complex.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for reinforcing a Feiteng processor board card, which has reasonable design, safety and reliability and can realize reinforcing communication between the board card and a bottom plate.
The technical problems to be solved by the invention are realized by the following technical proposal. The invention relates to a reinforcement method of a Feiteng processor board card, which comprises the following steps of
Installing a processor, DDR RAM, FLASH and a power management module on a board card;
soldering the board card to the base plate;
stamp hole bonding pads and connectors are arranged on the board card to realize communication between the board card and the bottom plate;
the connector and the stamp hole bonding pad are in signal connection with the processor, the DDR RAM, the FLASH and the power management module;
stamp hole pads are arranged at the edges of the periphery of the board card.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and in the reinforcing method of the Feiteng processor board card, the connector comprises a first connector and a second connector, wherein the first connector and the second connector both comprise two rows of pins which are arranged in parallel, and the pins are packaged on the board card through pin pads.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and for the reinforcement method of the Feiteng processor board card, the length of the pin bonding pad is 0.6mm, and the width of the pin bonding pad is 0.3mm.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and the number of pins in each row is 20 for the reinforcement method of the Feiteng processor board card.
The technical problem to be solved by the invention can be further solved by the following technical scheme, in the reinforcing method of the Feiteng processor board card, the stamp hole bonding pad is rectangular, semicircular holes are arranged on the stamp hole bonding pad near the edge side of the board card, the length of the stamp hole bonding pad is 1mm, the width of the stamp hole bonding pad is 0.9mm, the radius of the semicircular holes is 0.3mm, and the middle distance of the stamp hole bonding pad is 1.3mm.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and for the reinforcement method of the Feiteng processor board card, the reinforcement method is characterized in that the processor, the DDR RAM, the FLASH, the power management module and the stamp hole bonding pad are connected by the following signals:
(1) The power supply signal includes +3.3v and +2.5v;
(2) A digital ground signal GND;
(3) Two sets of serial port signals including TX0, RX0, TX1, RX1;
(4) 32 bits of GPIO signals, including PA 0.7, PB 0.7, PC 0.7, PD 0.7;
(5) Two sets of RGMII signals, each set of RGMII signals including GTX_CLK, TXD [0..3], TX_CTL, RX_CLK, RXD [0..3], RX_ CTL, COL, CRS, MDC, MDIO, respectively;
(6) Reset signal SRST.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and for the reinforcement method of the Feiteng processor board card, the reinforcement method is characterized in that the processor, the DDR RAM, the FLASH, the power management module and the connector are connected by the following signals:
(1) The signals to which the first connector is connected include a status signal PRSNT1, a control signal WAKE, a control signal PERST, a digital ground signal GND, a reference clock signal REFCLK+, a reference clock signal REFCLK-and 4 Lane signals of PCI-E X, each Lane signal including two pairs of differential signals OUTx+, OUTx-, INx+, INx-, x being 0 to 3;
(2) The signals connected by the second connector comprise a status signal PRSNT2, a digital ground signal GND and 4 Lane signals of PCI-E X, each Lane signal comprising two pairs of differential signals OUTx+, OUTx-, INx+, INx-, x being 4 to 7.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and the reinforcement method of the Feiteng processor board card is characterized in that two signals plus and minus adjacent wires of the differential signal pair of the first connector and the second connector are digitally isolated from the surrounding.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and the reinforcement method of the Feiteng processor board card is characterized in that the processor arranged on the board card is an FT-2000A processor.
The technical problem to be solved by the invention can be further solved by the following technical scheme, and the method for reinforcing the Feiteng processor board card comprises the following steps of:
(1) The first connector is connected with the corresponding connector of the bottom plate through a cable, and the second connector is not connected with the bottom plate, so that the bus function of PCI-E X4 is provided;
(2) The first connector is connected with the corresponding connector of the bottom plate through a cable, and the second connector is connected with the corresponding connector of the bottom plate through a cable, so that the bus function of PCI-E X is provided;
(3) The first connector is not connected with the bottom plate, the second connector is connected with the corresponding connector of the bottom plate through a cable, and the bus function of the PCI-E is not provided;
(4) The first connector is not connected to the backplane and the second connector is not connected to the backplane and does not provide the bus functionality of the PCI-E.
Compared with the prior art, the invention concentrates the processor, the DDR RAM, the FLASH and the power management module on one board card, and then welds the board card on the bottom plate through soldering tin to realize reinforcement installation; the stamp hole bonding pads are manufactured on the edges around the board card to provide interfaces, the processor, the DDR RAM, the FLASH and the power management module are in signal connection with the stamp hole bonding pads, and the external wiring is connected with the stamp hole bonding pads, so that the core functions of basic processors such as power supply, GPIO, serial interfaces, ethernet interfaces and the like can be realized; the PCI-E bus function can be realized by inserting and pulling the cable by arranging the connector on the board card, thereby ensuring the reinforcement and installation of the board card and the bottom plate and realizing the communication between the board card and the bottom plate. The reinforcing method is reasonable in design, convenient and reliable, and through the arrangement of the stamp hole bonding pad and the connector, not only is reinforcing installation of the board card and the bottom plate realized, but also communication between the board card and the bottom plate is ensured.
Drawings
FIG. 1 is a schematic diagram of a board card according to the present invention;
FIG. 2 is a schematic diagram of a stamp hole pad made in accordance with the present invention;
fig. 3 is a schematic structural view of a connector according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-3, a method of reinforcing a Feiteng processor board card includes
Mounting a processor 2, DDR RAM3, FLASH4 and a power management module 5 on a board card 1;
soldering the board card 1 to the bottom plate by soldering;
stamp hole bonding pads 8 and connectors 6 are arranged on the board card 1 to realize communication between the board card 1 and the bottom plate;
the connector 6 and the stamp hole bonding pad 8 are in signal connection with the processor 2, the DDR RAM3, the FLASH4 and the power management module 5;
stamp hole pads 8 are provided at the periphery of the board 1.
Details of the invention:
1. stamp hole bonding pad 8 is made to four sides of integrated circuit board 1
The core functions of the processor 2 consist of an FT-2000A processor 2, DDR RAM3, FLASH4 and a power management module 5;
stamp hole bonding pads 8 are manufactured on four sides of the PCB board for manufacturing the board card 1, the length of each bonding pad is 1mm, the width of each bonding pad is 0.9mm, the diameter of each drilling hole 9 is 0.6mm, the distance between circle centers of the drilling holes 9 and the center of each bonding pad is 0.5mm, and the center-to-center distance between bonding pads is 1.3mm.
2. The core functions of the processor 2 are connected to the stamp hole pads 8 by the following signals:
2.1, the power supply signal comprises +3.3V and +2.5V;
2.2, digital ground signal GND;
2.3, two sets of serial port signals including TX0, RX0, TX1, RX1;
2.4, 32 bits GPIO signals, including PA 0.7, PB 0.7, PC 0.7, PD 0.7;
2.5, two sets of RGMII signals, each set of RGMII signals comprising GTX_CLK, TXD [0..3], TX_CTL, RX_CLK, RXD [0..3], RX_ CTL, COL, CRS, MDC, MDIO, respectively;
2.6, reset signal SRST.
3. PCI-E bus connector interface
The PCI-E bus connector interface comprises a first connector and a second connector, wherein pins of the first connector and the second connector comprise an A side and a B side, each side is provided with N pins, and N is defined as 20; the connector 6 is packaged by adopting the bonding pads 7, the length and the width of the bonding pads 7 are respectively 0.6mm and 0.3mm, and the interval between the bonding pads 7 is 0.6mm;
3.1, the first connector comprises a status signal (PRSNT 1), a control signal (WAKE, PERST), a digital ground signal (GND), a reference clock signal (REFCLK+, REFCLK-) and a 4 Lane signal of PCI-E X (each Lane comprising two pairs of differential signals OUTx+, OUTx-, INx+, INx-, x being 0 to 3); the pin definition of the first connector is shown in table 1 below;
TABLE 1 Pin definition of first connector
The second connector includes a status signal (PRSNT 2), a digital ground signal (GND), and a 4 Lane signal of PCI-E X4 (each Lane includes two pairs of differential signals OUTx+, OUTx-, INx+, INx-, x being 4-7); the pin definition of the second connector is shown in table 2 below;
TABLE 2 Pin definition of the second connector
3.2, signal function design description of connector 6:
(1) The status signals (PRSNT 1, PRSNT 2) signal level is provided by the bottom board, and a low-level pull-down signal is provided for the board card 1;
when the first connector is connected to the backplane, PRSNT1 is set low, enabling PCI-E X bus functionality;
when the second connector is connected to the backplane, PRSNT2 is set low and when PRSNT1 is set low, PCI-E X bus functionality is enabled.
(2) The control signal (PERST) signal level is provided by the board 1 and resets the PCI-E bus when the PERST signal is high. Defaulting to low;
(3) The control signal (WAKE) signal level is provided by the board 1, and the PCI-E bus is put into sleep mode when the WAKE signal is high. Defaulting to low;
(4) The reference clock signals (REFCLK+, REFCLK-) are provided by the backplane;
(5) The 8 Lane signals of PCI-E X (each Lane comprising two pairs of differential signals OUTx+, OUTx-, INx+, INx-, x being 0 to 7) are provided by the board card 1.
3.3, arrangement design description of signal positions of connector 6:
the two signals (+, -) of the differential signal pair are close to the wiring as much as possible, and the periphery is digitally isolated, so that excellent signal transmission quality can be obtained;
(1) In designing the pin positions of the connector 6, the differential signal pairs outx+, OUTx-and inx+, INx- (x being 0 to 7) signals are arranged together and the surroundings are digitally isolated;
(2) When PCI-E bus functionality is enabled, the PERST, WAKE, WAKE three signals are low. In designing the pin locations of the connector 6, the differential signal pairs refclk+, REFCLK-signals are arranged together and digitally isolated from the surroundings.
3.4 implementing PCI-E bus function by plugging and unplugging cables
(a) When the first connector of the board card 1 is connected with the corresponding connector 6 of the bottom board through a cable, the bottom board provides a pull-down signal of PRSNT1 for the board card 1, and the board card 1 enables the bus function of PCI-E X;
(b) When the second connector of the board card 1 is connected with the corresponding connector 6 of the bottom board through the cable after the step (a), the bottom board provides a pull-down signal of the PRSNT2 for the board card 1, and the board card 1 enables the bus function of the PCI-E X;
(c) The first connector and the second connector of the board card 1 do not provide the bus function of the PCI-E when they are not connected by the cable and the backplane.
The inventive principle of the present application:
(1) The stamp hole bonding pad 8 provides the core functions of the basic processor 2 such as power supply, GPIO, serial interface, ethernet interface and the like, and the board card 1 is welded on the bottom plate through soldering tin to realize reinforcement installation;
(2) The special PCI-E connector 6 interface provides transmission of configurable differential signal pairs to realize PCI-E bus function;
(2.1) the first connector is connected to the corresponding connector 6 of the backplane by a cable, the second connector is not connected to the backplane, and provides the bus function of PCI-E X4;
(2.2) the first connector is connected by a cable to the corresponding connector 6 of the backplane, and the second connector is connected by a cable to the corresponding connector 6 of the backplane, providing the bus function of PCI-E X;
(2.3) the first connector is not connected to the backplane, the second connector is connected to the corresponding connector 6 of the backplane by a cable, and the bus function of the PCI-E is not provided;
(2.4) the first connector is not connected to the backplane, and the second connector is not connected to the backplane, and does not provide the PCI-E bus functionality.
Advantages and technical effects of the present application
(1) The use is more convenient, and the more reliable reinforcement is ensured
The surface mount machine is easier to carry out flow line processing production by adopting the welding mode of the stamp hole bonding pad 8; the test of impact vibration is more easily satisfied through soldering tin welding, and excellent reinforcement guarantee is obtained.
(2) Variable PCI-E bus communication speed
And the variable PCI-E bus communication speed is realized by plugging and unplugging the cable.
(3) Product application meeting space installation requirements
By using the invention, the whole product height is only increased by the thickness of one PCB, and the product application with the space installation requirement is satisfied.
(4) Reduces the design and use cost of the product
For most product applications, PCI-E X4 is used or PCI-E is not used in many cases; if PCI-E bus functions are not used, the first connector, the second connector and the corresponding cables of the board card 1 and the bottom board may not be soldered; if PCI-E X4 is used, only the first connector and cable of the board card 1 and the backplane are needed; by using the invention, the application of variable products can be satisfied by only designing one board card 1, and the design and use cost is reduced.
Claims (7)
1. A method for reinforcing a Feiteng processor board card is characterized by comprising the following steps: the reinforcing method comprises
Installing a processor, DDR RAM, FLASH and a power management module on a board card;
soldering the board card to the base plate;
stamp hole bonding pads and connectors are arranged on the board card to realize communication between the board card and the bottom plate;
the connector and the stamp hole bonding pad are in signal connection with the processor, the DDR RAM, the FLASH and the power management module;
stamp hole bonding pads are arranged at the edges of the periphery of the board card;
in the reinforcing method, the connector comprises a first connector and a second connector, wherein the first connector and the second connector comprise two rows of pins which are arranged in parallel, and the pins are packaged on a board card through pin bonding pads;
in the reinforcing method, a stamp hole welding disc is designed to be rectangular, semicircular holes are formed in the stamp hole welding disc near the edge side of the board card, the length of the stamp hole welding disc is 1mm, the width of the stamp hole welding disc is 0.9mm, the radius of the semicircular holes is 0.3mm, and the middle distance of the stamp hole welding disc is 1.3mm;
in the reinforcing method, the method for realizing the PCI-E bus function by the board card through the first connector and the second connector comprises the following steps:
(1) The first connector is connected with the corresponding connector of the bottom plate through a cable, and the second connector is not connected with the bottom plate, so that the bus function of PCI-E X4 is provided;
(2) The first connector is connected with the corresponding connector of the bottom plate through a cable, and the second connector is connected with the corresponding connector of the bottom plate through a cable, so that the bus function of PCI-E X is provided;
(3) The first connector is not connected with the bottom plate, the second connector is connected with the corresponding connector of the bottom plate through a cable, and the bus function of the PCI-E is not provided;
(4) The first connector is not connected to the backplane and the second connector is not connected to the backplane and does not provide the bus functionality of the PCI-E.
2. A method for reinforcing a Feiteng processor board as defined in claim 1, wherein: the length of the pin bonding pad is 0.6mm, and the width of the pin bonding pad is 0.3mm.
3. A method for reinforcing a Feiteng processor board as defined in claim 1, wherein: the number of pins per row is 20.
4. A method for reinforcing a Feiteng processor board as defined in claim 1, wherein: in the reinforcement method, the processor, the DDR RAM, the FLASH, the power management module and the stamp hole bonding pad are connected by the following signals:
(1) The power supply signal includes +3.3v and +2.5v;
(2) A digital ground signal GND;
(3) Two sets of serial port signals including TX0, RX0, TX1, RX1;
(4) 32 bits of GPIO signals, including PA 0.7, PB 0.7, PC 0.7, PD 0.7;
(5) Two sets of RGMII signals, each set of RGMII signals including GTX_CLK, TXD [0..3], TX_CTL, RX_CLK, RXD [0..3], RX_ CTL, COL, CRS, MDC, MDIO, respectively;
(6) Reset signal SRST.
5. A method for reinforcing a Feiteng processor board as defined in claim 1, wherein: in the reinforcement method, the processor, the DDR RAM, the FLASH, the power management module and the connector are connected by the following signals:
(1) The signals to which the first connector is connected include a status signal PRSNT1, a control signal WAKE, a control signal PERST, a digital ground signal GND, a reference clock signal REFCLK+, a reference clock signal REFCLK-and 4 Lane signals of PCI-E X, each Lane signal including two pairs of differential signals OUTx+, OUTx-, INx+, INx-, x being 0 to 3;
(2) The signals connected by the second connector comprise a status signal PRSNT2, a digital ground signal GND and 4 Lane signals of PCI-E X, each Lane signal comprising two pairs of differential signals OUTx+, OUTx-, INx+, INx-, x being 4 to 7.
6. A method for reinforcing a Feiteng processor board as defined in claim 5, wherein: in the reinforcement method, two signals + -adjacent wires of a differential signal pair of a first connector and a second connector are digitally isolated from each other.
7. A method for reinforcing a Feiteng processor board as defined in claim 1, wherein: in the reinforcement method, the processor mounted on the board card is an FT-2000A processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010513208.9A CN111651401B (en) | 2020-06-08 | 2020-06-08 | Reinforcing method for Feiteng processor board card |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010513208.9A CN111651401B (en) | 2020-06-08 | 2020-06-08 | Reinforcing method for Feiteng processor board card |
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| CN111651401A CN111651401A (en) | 2020-09-11 |
| CN111651401B true CN111651401B (en) | 2023-12-29 |
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| CN203352944U (en) * | 2013-05-30 | 2013-12-18 | 航天科工深圳（集团）有限公司 | PCB with stamp holes |
| CN203480375U (en) * | 2013-09-09 | 2014-03-12 | 杭州启扬智能科技有限公司 | Core board |
| CN105320633A (en) * | 2015-11-20 | 2016-02-10 | 天津光电通信技术有限公司 | Double-channel high-speed analog digital signal collecting and processing board card |
| CN205336260U (en) * | 2015-11-05 | 2016-06-22 | 深圳市布谷鸟科技有限公司 | Car hypersystem nuclear core plate and car hypersystem |
| CN206877227U (en) * | 2017-04-20 | 2018-01-12 | 湖南军威联航科技有限公司 | A kind of antidetonation solid state hard disc mounting structure |
| CN111142630A (en) * | 2019-12-02 | 2020-05-12 | 杭州迪普科技股份有限公司 | Processor board card |
-
2020
- 2020-06-08 CN CN202010513208.9A patent/CN111651401B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203352944U (en) * | 2013-05-30 | 2013-12-18 | 航天科工深圳（集团）有限公司 | PCB with stamp holes |
| CN203480375U (en) * | 2013-09-09 | 2014-03-12 | 杭州启扬智能科技有限公司 | Core board |
| CN205336260U (en) * | 2015-11-05 | 2016-06-22 | 深圳市布谷鸟科技有限公司 | Car hypersystem nuclear core plate and car hypersystem |
| CN105320633A (en) * | 2015-11-20 | 2016-02-10 | 天津光电通信技术有限公司 | Double-channel high-speed analog digital signal collecting and processing board card |
| CN206877227U (en) * | 2017-04-20 | 2018-01-12 | 湖南军威联航科技有限公司 | A kind of antidetonation solid state hard disc mounting structure |
| CN111142630A (en) * | 2019-12-02 | 2020-05-12 | 杭州迪普科技股份有限公司 | Processor board card |
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| CN111651401A (en) | 2020-09-11 |
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Address after: 222000 No.42, Hailian East Road, Haizhou District, Lianyungang City, Jiangsu Province Applicant after: China Shipbuilding Digital Information Technology Co.,Ltd. Address before: 222000 No.42, Hailian East Road, Haizhou District, Lianyungang City, Jiangsu Province Applicant before: CSIC Information Technology Co.,Ltd. |
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