CN206363303U - A kind of CPU module based on VPX structures - Google Patents
A kind of CPU module based on VPX structures Download PDFInfo
- Publication number
- CN206363303U CN206363303U CN201621444921.8U CN201621444921U CN206363303U CN 206363303 U CN206363303 U CN 206363303U CN 201621444921 U CN201621444921 U CN 201621444921U CN 206363303 U CN206363303 U CN 206363303U
- Authority
- CN
- China
- Prior art keywords
- vpx
- pcie
- interfaces
- interface
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Bus Control (AREA)
Abstract
The utility model discloses a kind of CPU module based on VPX structures, including processor platform and VPX buses；The PCIe interface of the processor platform includes the first PCIe interface, the second PCIe interface and the 3rd PCIe interface；First PCIe interface is connected to VPX buses；Second PCIe interface is extended to gigabit ethernet interface and is connected to VPX buses；3rd PCIe interface connects PCIe to SRIO bridging chips；The output interface of PCIe to the SRIO bridging chips is connected to VPX configuration bus.
Description
Technical field
The utility model is related to field of computer technology, particularly a kind of CPU module based on VPX structures.
Background technology
With developing rapidly for information technology and computer technology, future society will be an efficient digital society,
The information such as substantial amounts of voice, data, image, figure need calculating platform to carry out real-time perception and processing.Exist along with computer
The deep utilization of every field, in Aero-Space control, sea floor exploration investigation, the disaster detection in earthquake volcano, extensive guided missile
The high-end measurement and control area such as celestial body scientific investigation outside emission control, detections of radar and electronic countermeasure and ground, user is to high-performance, anti-evil
Bad environment calculating platform it is also proposed higher and higher requirement, and that traditional image is shown and processing module is used is parallel total
Line number is slower according to exchange velocity, can not meet requirement.
Utility model content
The purpose of this utility model is to provide a kind of CPU module based on VPX structures, the data exchange energy with higher speed
Power.
To achieve these goals, a kind of CPU module based on VPX structures that the utility model is provided, including processor
Platform and VPX buses；The PCIe interface of the processor platform includes the first PCIe interface, the second PCIe interface and the 3rd PCIe
Interface；
First PCIe interface is connected to VPX buses；
Second PCIe interface is extended to gigabit ethernet interface and is connected to VPX buses；
3rd PCIe interface connects PCIe to SRIO bridging chips；The output of PCIe to the SRIO bridging chips connects
Mouth is connected to VPX configuration bus.
Alternatively and preferably, the CPU in the processor platform is Core i7-5850EQ processors, with the processing
The chipset that CPU in device platform coordinates is the DH82QM87PCH chips of Intel Company.
Alternatively and preferably, the processor platform has 1 road PCIe x16 interfaces, is separated in the PCIe x16 interfaces
The PEX8734 exchange chips of PCIe x8 interfaces connection PLX companies, and two-way PCIe is picked out from PEX8734 exchange chips all the way
X8 interfaces are used as the first PCIe interface.
Alternatively and preferably, two-way PCIe x4 interfaces are also separated in the PEX8734 exchange chips；The PCIe is arrived
SRIO bridging chips are the TSi721 chips of Integrated Device Technology, Inc., and the input of TSi721 chips connects the two-way PCIex4 interfaces, defeated
Go out end and form two-path SR IO x4 interfaces to be connected to VPX buses.
Alternatively and preferably, the 8 road PCIe2.0x1 interface assignments processor platform carried in itself are into 2 tunnels
PCIe2.0x4 interfaces, by wherein connecting Intel PCI-Express adapter I350-AM4 all the way, are extended to 4 road kilomega networks and connect
Mouthful, wherein two-way is connected to VPX buses, and two-way is connected to the front panel of module in addition.
Alternatively and preferably, in addition to IPMB buses, the IPMB buses pass through controller and the processor platform
Connection.
Alternatively and preferably, in addition to the first FPGA and the 2nd FPGA；The DP interfaces input of first FPGA with
Processor platform is connected, the output end connection VPX buses of DP interfaces；The SRIO interfaces of 2nd FPGA connect the PCIe and arrived
SRIO bridging chips；The DP input interfaces connection VPX buses of 2nd FPGA；The UART of first FPGA and the 2nd FPGA
Interface is all connected with the processor platform；Connected between first FPGA and the 2nd FPGA by LVDS interface.
A kind of CPU module based on VPX structures that the utility model is provided, the first PCIe interface of processor platform is connected
VPX buses are connected to, the second PCIe interface is extended to gigabit ethernet interface and is connected to VPX buses；3rd PCIe interface is connected
PCIe to SRIO bridging chips；The output interface of PCIe to SRIO bridging chips is connected to VPX configuration bus.So not only meet
At present VPX bus Direct Communications can be passed through in the most widely used serial high-speed bus of three classes of backboard, and between each board
Be exchanged with each other data, improve data exchange efficiency.And VPX frameworks are High performance industrial computer architecture, are met severe
Military affairs and aeronautical environment in job requirement.
Brief description of the drawings
The system block diagram for the CPU module based on VPX structures that Fig. 1 is provided by the utility model embodiment；
The board structure schematic diagram for the CPU module based on VPX structures that Fig. 2 is provided by the utility model embodiment；
In figure：
1- processor platforms；2-PCIe to SRIO bridging chips；The FPGA of 3- the first；The FPGA of 4- the 2nd；5-MCU；6- power supplys；
7-VPX buses；The device mounting regions of 8- first；The device mounting regions of 9- second；10- connector installing zones.
Embodiment
In order that those skilled in the art more fully understand the utility model scheme, below in conjunction with the accompanying drawings and specific implementation
The utility model is described in further detail for mode.
Fig. 1 is refer to, a kind of CPU module based on VPX structures that the present embodiment is provided can be specifically based on as one kind
The synthesis display board of VPX structures, for image procossing and data processing, is configured by hardware, the different of logical sum software, can
To meet different images processing or data processing task requirement.
The module can specifically include processor platform 1, and the processor platform 1 includes CPU and matched with CPU
Chipset (Chipset chips).The CPU being preferred to use is the Core i7-5850EQ processors of Intel Company, the processor branch
Hold binary channels DDR3L memory interfaces.CPU two main memory accesses are connected in DDR3 memory chip of the plate labeling not less than 4GB
On.The Chipset chips of processor platform 1 are preferred to use the DH82QM87PCH chips of Intel Company.The chip can be provided
Most 8 road PCIe x1 buses, can be configured to 2 road PCIe x4 buses.QM87 chips can provide six road SATA3.0 interfaces, will
It is connected to all the way at plate SSD chips (i.e. solid state hard disc chip), another road is connected to 2.5 cun of hard-disk interfaces.QM87 chips can also connect
Connecing 4x USB2.0 interfaces and 1x USB interfaces is used for the debugging of computer part to VPX buses 7 (i.e. the bus shown in Fig. 1).
CPU is connected with Chipset chips by DMI buses.In addition processor platform can also pick out RS422 interfaces and all the way DP all the way
It is interfaced to VPX buses 7.
Include PCIe, S-RIO and kilomega network in the most widely used serial high-speed bus of backboard at present, so this secondary design pair
Outer I/O is mainly this three kinds.Specifically technical concept is：The PCIe interface of processor platform 1 includes the first PCIe interface, the
Two PCIe interfaces and the 3rd PCIe interface, the first PCIe interface is directly connected with VPX configuration bus 7.Second PCIe interface expands
Transform into gigabit ethernet interface and be connected to VPX buses 7.3rd PCIe interface connects PCIe to SRIO bridging chips；It is described
The output interface of PCIe to SRIO bridging chips is connected to VPX configuration bus 7.Three of the above interface is carried out furtherly below
It is bright.
Core i7-5850EQ processor platforms support PCIe3.0x16 all the way and 8 road PCIe2.0x1 interfaces in itself, but by
It is required for transferring from PCIe interface in the realization of S-RIO and kilomega network and realizes, so PCIe resources are by anxiety, based on this reason,
The present embodiment has used PCIe Switch to enrich system PCIe interface resource, has specifically selected the PEX8734 of PLX companies to hand over
Chip (not shown) is changed, it supports 32Lane channels, PCIex16 interfaces are separated PCIex8 interfaces access all the way by selection
PEX8734, then picks out 2 road PCIe x8 (as the first PCIe interface) from PEX8734 and is connected to VPX buses 7, realizes pair
Outer PCIe bus I/O resources.
The remaining 8Lane channels of PEX8734 are divided into 2 road PCIex4 interfaces (as the second PCIe interface), use Integrated Device Technology, Inc.
TSi721 chips as PCIe to SRIO bridging chips 2, the input of TSi721 chips connects the two-way PCIex4 interfaces,
The output end formation two-path SR IO x4 interfaces of TSi721 chips are connected to VPX buses 7.There is provided 2 external road SRIOx4 of platform total
Line I/O resources.
The 8 road PCIe2.0x1 interface assignments that processor platform 1 is carried in itself (are used as into 2 road PCIe2.0x4 interfaces
Three PCIe interfaces), by the way that wherein extension Intel PCI-Express adapter I350-AM4 (not shown)s realize 4 tunnels thousand all the way
Million network interfaces, wherein two-way are connected to VPX buses 7 (the 1Gb Ethernets in Fig. 1), realize the external gigabit network interface money of platform
Source, in addition two-way be connected to front panel, for board debugging.In addition, processor platform 1 can also pass through 10GbE Interface Expandings
Two-way 10Gb Ethernets.
In addition to above I/O resource, the CPU module board based on VPX structures also achieves the XMC interfaces of VITA42 standards, will
The remaining interfaces of the PCIe3.0x8 all the way access XMC interface (not shown)s of PCIe3.0x16 interfaces of processor platform, can lead to
The mode for crossing XMC plug-in cards enriches systemic-function, such as can connect me and take charge of video card product, the showing when system that meets carries out image procossing
Card demand.
In order to solve system-level problem of management, the CPU module based on VPX structures also includes IPMB buses, and IPMB buses are led to
Cross controller (i.e. MCU 5) to be connected with the processor platform 1, by gate electricity wherein between processor platform 1 and controller
Road (TTL) is connected.Can be specifically, by the IPMB buses on backboard, a BMC controller to be designed in system groove, other grooves are set
The controller of meter energy compatibility IPMI orders, system groove can be read the state of other frid cards by IPMB, notify manager.
During work, all IPMI functions are all to send commands to complete to BMC controllers, and order is used specified in IPMI specifications
Instruction, BMC is received and event message is recorded in System Event Log, safeguards the device data note of device situation in description system
Record.IPMB systems are independently of operating system, when operating system is not responding to or processor is under off-mode, it remain to by
Main control is accessed, and facilitates management of the system to board to control.Also connected between VPX buses 7 and MCU 5 by GA interfaces.
In the present embodiment, the connector of VPX buses 7 have developed modular VPX RT2 connectors from Tyco companies
(not shown), the connector includes controllable impedance, low insertion loss, under highest 6.25Gbaud, and crosstalk is less than 3%, can
Fully meet high-speed I/O bus interconnecting application demand.
For the data receiver sent to PCIe to SRIO bridging chips 2, parsing, and downstream components are sent to again, this
Module in embodiment also includes the first FPGA3 and the 2nd FPGA 4；(i.e. DisplayPort connects first FPGA3 DP interfaces
Mouthful) 4 road DP output interfaces of input and processor platform connect, the output end connection VPX of the first FPGA 3 DP interfaces is total
Line 7；2nd FPGA 4 SRIO interfaces connection PCIe to SRIO bridging chips；2nd FPGA 4 DP input interfaces connection VPX
Bus；First FPGA 3 and the 2nd FPGA 4 UART interface is all connected with the processor platform；First FPGA 3 and second
Connected between FPGA 4 by LVDSx64 interfaces, to interact with each other data.So, the FPGA system in the present embodiment both can be with
The DP signals from processor platform are received, the signal of SRIO interfaces transmission can also be received, wide usage is higher, in addition, two
FPGA each other can be with interaction data, and therefore, some image processor operations can be completed first in the first FPGA 3, Jin Erzai
The processing that the 2nd FPGA 4 does remainder is sent to, each FPGA live load is reduced, the place of picture signal is improved
Manage efficiency.
The power supply 6 of module can be 12V power supplys and 5V power supplys.
The board structure schematic diagram of the present embodiment CPU module is illustrated in figure 2, wherein, in the first device mounting region 8 and
Two device mounting regions 9 can place VPX buses with the various modules in installation diagram 1 in the connector installing zone 10 of bottom
Connector.
To sum up, this secondary design realizes powerful, the feature-rich high-performance computer of performance of a VPX normal structure and put down
Platform.
A kind of CPU module based on VPX structures provided by the utility model is described in detail above.Herein
Apply specific case to be set forth principle of the present utility model and embodiment, the explanation of above example is only intended to
Help understands core concept of the present utility model.It should be pointed out that for those skilled in the art, not taking off
On the premise of from the utility model principle, some improvement and modification can also be carried out to the utility model, these improve and modified
Also fall into the utility model scope of the claims.
Claims (7)
1. a kind of CPU module based on VPX structures, it is characterised in that including processor platform and VPX buses；The processor
The PCIe interface of platform includes the first PCIe interface, the second PCIe interface and the 3rd PCIe interface；
First PCIe interface is connected to VPX buses；
Second PCIe interface is extended to gigabit ethernet interface and is connected to VPX buses；
3rd PCIe interface connects PCIe to SRIO bridging chips；The output interface of PCIe to the SRIO bridging chips connects
It is connected to VPX configuration bus.
2. the CPU module according to claim 1 based on VPX structures, it is characterised in that in the processor platform
CPU is Core i7-5850EQ processors, and the chipset coordinated with the CPU in the processor platform is Intel Company
DH82QM87PCH chips.
3. the CPU module according to claim 2 based on VPX structures, it is characterised in that the processor platform has 1
Road PCIe x16 interfaces, the PEX8734 for separating PCIe x8 interfaces connection PLX companies all the way in the PCIe x16 interfaces exchanges core
Piece, and two-way PCIe x8 interfaces are picked out as the first PCIe interface from PEX8734 exchange chips.
4. the CPU module according to claim 3 based on VPX structures, it is characterised in that the PEX8734 exchange chips
In also separate two-way PCIe x4 interfaces；PCIe to the SRIO bridging chips are the TSi721 chips of Integrated Device Technology, Inc., TSi721 cores
The input of piece connects the two-way PCIex4 interfaces, and its output end formation two-path SR IO x4 interfaces are connected to VPX buses.
5. the CPU module according to claim 1 based on VPX structures, it is characterised in that by the processor platform in itself
The 8 road PCIe2.0x1 interface assignments carried are into 2 road PCIe2.0x4 interfaces, by the way that wherein connection Intel PCI-Express is fitted all the way
Orchestration I350-AM4, exports 4 tunnel gigabit network interfaces, and wherein two-way is connected to VPX buses, and two-way is connected to CPU module in addition
Front panel.
6. according to any described CPU modules based on VPX structures of claim 1-5, it is characterised in that also total including IPMB
Line, the IPMB buses are connected by controller with the processor platform.
7. the CPU module according to claim 1 based on VPX structures, it is characterised in that also including the first FPGA and second
FPGA；The DP interfaces input of first FPGA is connected with processor platform, the output end connection VPX buses of DP interfaces；Institute
The SRIO interfaces for stating the 2nd FPGA connect PCIe to the SRIO bridging chips；The DP input interfaces connection of 2nd FPGA
VPX buses；The UART interface of first FPGA and the 2nd FPGA is all connected with the processor platform；First FPGA and
Connected between two FPGA by LVDS interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621444921.8U CN206363303U (en) | 2016-12-27 | 2016-12-27 | A kind of CPU module based on VPX structures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621444921.8U CN206363303U (en) | 2016-12-27 | 2016-12-27 | A kind of CPU module based on VPX structures |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206363303U true CN206363303U (en) | 2017-07-28 |
Family
ID=59376906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621444921.8U Active CN206363303U (en) | 2016-12-27 | 2016-12-27 | A kind of CPU module based on VPX structures |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206363303U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108804361A (en) * | 2018-05-22 | 2018-11-13 | 天津市英贝特航天科技有限公司 | A kind of PCIE switches based on VPX bus architectures |
| CN110334045A (en) * | 2017-09-10 | 2019-10-15 | 苏州英贝迪电子科技有限公司 | Expansible multiplex roles industrial control computer mainboard |
-
2016
- 2016-12-27 CN CN201621444921.8U patent/CN206363303U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110334045A (en) * | 2017-09-10 | 2019-10-15 | 苏州英贝迪电子科技有限公司 | Expansible multiplex roles industrial control computer mainboard |
| CN110334045B (en) * | 2017-09-10 | 2021-01-01 | 上海必卓电子科技有限公司 | Extensible multi-interface industrial personal computer mainboard |
| CN108804361A (en) * | 2018-05-22 | 2018-11-13 | 天津市英贝特航天科技有限公司 | A kind of PCIE switches based on VPX bus architectures |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107632953A (en) | A kind of GPU casees PCIE extends interconnection topology device | |
| US9654342B2 (en) | Bandwidth configurable IO connector | |
| CN102880587B (en) | Embedded accelerating core based independent graphics card architecture | |
| CN107704413A (en) | A kind of reinforcement type parallel information processing platform based on VPX frameworks | |
| CN110717853B (en) | Optical image processing system based on embedded GPU | |
| CN103777716A (en) | 3U general substrate based on VPX bus and for FMC structures | |
| CN206363303U (en) | A kind of CPU module based on VPX structures | |
| CN202383569U (en) | Mainboard with multifunctional extensible peripheral component interconnect express (PCIE) interface device | |
| CN110766600B (en) | Image processing system with distributed architecture | |
| CN202026431U (en) | Debugging device and debugging system | |
| CN208538025U (en) | A kind of server for supporting 10 hot-plug hard disks | |
| CN107480085A (en) | Multiplex roles integrated test system | |
| CN210776403U (en) | Server architecture compatible with GPUDirect storage mode | |
| CN205656617U (en) | SoC's peripheral hardware system | |
| CN210466253U (en) | Server with high-density GPU expansion capability | |
| CN103399839B (en) | Media peripheral interface, electronic device and communication means | |
| CN204009971U (en) | A kind of multimedia display and face identification device | |
| CN203561933U (en) | FMC structure 3U universal carrier board based on VPX bus | |
| CN207503207U (en) | For the integrated test system of multiplex roles | |
| CN209086914U (en) | The industrial control mainboard of multi-USB interface and more PCI-E expansion interfaces | |
| CN212569635U (en) | VPX computer motherboard based on processor chip flies to ten | |
| CN211087884U (en) | Image processor suitable for O L ED panel detection | |
| CN105868153A (en) | PCI-E extension mode based on ATCA bus | |
| CN110362433A (en) | The system for being able to carry out multiplex roles test | |
| CN205384545U (en) | Display card accelerator based on vxworks |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |