CN103777716A

CN103777716A - 3U general substrate based on VPX bus and for FMC structures

Info

Publication number: CN103777716A
Application number: CN201310618147.2A
Authority: CN
Inventors: 不公告发明人
Original assignee: BEIJING HUA KEBO BOCHUANG TECHNOLOGY Co Ltd
Current assignee: BEIJING HUA KEBO BOCHUANG TECHNOLOGY Co Ltd
Priority date: 2013-11-29
Filing date: 2013-11-29
Publication date: 2014-05-07

Abstract

The invention provides a 3U general substrate based on a VPX bus and for FPGA mezzanine card (FMC) structures, and belongs to the field of computers. At the present, the field-programmable gate array (FPGA) technology, the digital signal processing (DSP) technology and the CPU technology are continuously developed, and a traditional parallel bus cannot meet the requirements for the large bandwidth and the high rate. The 3U substrate carries an on-board FPGA, meets the VPX standard and belongs to a Virtex6 series, and can be connected with different FMC daughter boards to achieve multiple functions. The 3U general substrate based on the VPX bus and for the FMC structures is based on a VME International trade association 46 (VITA46) standard, and a high-speed peripheral component interconnect express (PCIe) bus serves as an interconnection bus in the 3U general substrate. The 3U general substrate based on the VPX bus and for the FMC structures comprises a power module, a VPX connector, an FMC connector and an FPGA chip, and the effective communication bandwidth is increased; due to the fact that the FMC structural design is adopted, the universality design of the 3U general substrate is improved, the 3U general substrate can carry different daughter boards, and multiple functions are achieved.

Description

A kind of FMC structure 3U general carrier plate based on VPX bus

Technical field

The present invention relates to a kind of FMC structure 3U general carrier plate based on VPX bus, belong to computer realm, a VPX of meeting standard is provided, can connect multiple FMC daughter board, realize the 3U board of several functions.

Background technology

On the one hand, along with the develop rapidly of integrated circuit, computing machine treatment technology and software engineering, the data handling system platform of field of aerospace presents following development trend: communication bandwidth is more and more wider, transfer rate is more and more higher, real-time handling property is also had higher requirement to the performance of processing platform.Therefore, need data processing platform (DPP) to there is higher bus transfer bandwidth, stronger arithmetic capability and data exchange capability more flexibly.And processing platform (as CPCI(Compact Peripheral Component Interconnect), VME(Versa Module Eurocard based on the shared parallel bus of traditional classification) etc. platform), Bus Clock Rate and bus interface width have determined that the key property of processing platform is doomed to meet these new demands.

VPX be organized to set up by VITA in order to meet high reliability under rugged surroundings, the senior computing platform standard of the next generation that high bandwidth requires, intermodule has defined Serial RapidIO, PCI Express, Fibre Channel, InfiniBand, Hyper-transport, the high-speed serial bus such as 10GB Ethernet, transfer rate can be up to 30Gbps, and there are superpower data and go out Ali's ability, can fully solve above new demand, therefore, general ruggedized computer based on VPX bus architecture is the developing direction of following field of aerospace data handling system.

On the other hand, along with the diversification of the market demand, have higher requirement for complicated circuit design, be not difficult to find out many times when variation has occurred in some concrete little functional requirement, a huge circuit version of function has just caused the wasting of resources, and has caused corresponding economic loss.

Summary of the invention

The object of the invention is to, for above demand, a kind of FMC structure 3U general carrier plate based on VPX bus has been proposed, both can meet the demand of two-forty, high band wide data processing, the problem that can solve again the design of board design flexibility, can realize different functions in conjunction with various function daughter boards.

Design proposal of the present invention is as follows: a kind of 3U general carrier plate of the FMC structure based on VPX bus, and this general carrier plate comprises: power module, VPX connector, FMC connector and fpga chip, described fpga chip is selected Virtex-6 HXT FPGA; The plug-in two 256MB DDR2 SDRAM of described fpga chip.

Described fpga chip comprises: front-end interface module, data cache module and back end interface module.

The method for designing of the 3U general carrier plate of the FMC structure based on VPX bus, comprise the signal processing between signal processing and transmission, support plate and backboard in plate and be connected, signal processing between support plate and function daughter board be connected and structural design, it is characterized in that:

It is core that support plate adopts the FPGA of a slice Virtex 6 series, the DDR2 internal memory of plug-in 512M; Support FMC-HPC, gigabit Ethernet, 2 road X4 PCIe, wherein PCIe interface changes sRIO into by revising software, and board provides 5V and 3.3V power supply by VPX interface, and wherein 3.3V is main power supply;

Support plate adopts the PI connector of VPX to be connected with backboard, carries out data transmission by gigabit Ethernet or PCIeX4;

Support plate and function daughter board adopt the connector of FMC structure, complete in the data transmission of each function daughter board;

Carrying board structure meets the design standards of the 3U board of VITA46 completely, can be applicable to the backboard cabinet of any VITA46 of meeting standard.

Based on FMC standard, by daughter board size, connector and the module interface of standard are provided for FPGA on support plate, realize I/O interface and separate with FPGA, simplify I/O Design of Interface Module, maximize the recycling rate of waterused that improves subcard.

The highest support 533MT/s, and support user's secondary development.

The invention has the beneficial effects as follows: based on the design of FMC subcard interconnect architecture, not only can realize the multiple independent individual event function of user's request, but also the restriction of having broken the element area to subcard PCB plate makes design effort more flexible; Particularly, for the daughter board of the interface support plate with CPU, can meet user's different requirements.

Accompanying drawing explanation

Fig. 1 is designed system theory diagram of the present invention.

Fig. 2 is the front elevation of the present invention of design.

Fig. 3 is the vertical view of the present invention of design.

Fig. 4 is the FMC connector that the present invention uses.

Fig. 5 is applicable to 2 road CameraLink I/O daughter boards of a kind of general FMC structure of the present invention.

Specific implementation

Referring to Fig. 1, a kind of system principle diagram of the FMC structure 3U general carrier plate based on VPX bus.Wherein, fpga chip is selected Virtex-6 HXT FPGA, and the highest nearly 64 GTH serial transceivers can provide the bandwidth up to 11.2Gbps; The plug-in two 256MB DDR2 SDRAM of FPGA, 32bit bit wide, the highest support 533MT/s; Can support 1 road gigabit Ethernet or 2 road PCIe X4 with VPX standard P 1 interface, wherein PCIe interface can be revised and change sRIO into; Connector with function daughter board employing FMC structure, completes in the data transmission of each function daughter board, supports the signal transmission rate up to 10 Gb/s, and between daughter board and support plate, potential total bandwidth reaches 40 Gb/s; Board provides 5V and 3.3V power supply by the P1 interface of VPX.Wherein 3.3V is main power supply.

Fpga chip is made up of front-end interface module, data cache module and back end interface module.Front-end interface module mainly completes from FMC interface according to sequential reading out data or signal; Data buffering module mainly completes isolation, the SDRAM(Synchronous Dynamic Random Access Memory in input clock territory, output clock territory) control of sequential control, each input channel, output channel and SDRAM data stream and channel data detects and the function such as interruption status monitoring; Back end interface module is mainly responsible for communicating by letter of PCIe interface (or gigabit Ethernet) and local bus, completes with local bus the coherent signal of writing, address and the data-signal that carry out handshake operation, receive the transmission of local bus end.

The present invention is based on FMC standard, by daughter board size, connector and the module interface of standard are provided for FPGA on support plate, realize I/O interface and separate with FPGA, simplify I/O Design of Interface Module, maximize and improve the recycling rate of waterused of carrying card.

Carrying board structure of the present invention meets the design standards of the 3U board of VITA46 completely, can be applicable to the backboard cabinet of any VITA46 of meeting standard, can be used in conjunction with from different function daughter board (universal goods shelf COTS or meet the function daughter board of VPX standard), realize different functions.

Referring to Fig. 2, it is the pictorial diagram that the present invention designs.

Referring to Fig. 3, it is the FMC connector that the present invention uses.

Fig. 4 is that the 2 road CameraLink I/O daughter boards of a kind of general FMC are applied based on one of the present invention, this CameraLink daughter board is for video signal detection, the application such as analysis, this CameraLink daughter board is directly installed on support plate of the present invention, then support plate is installed to and meets on VPX standard PC case, carry out the acquisition and processing of data.

Claims

1. a 3U general carrier plate for the FMC structure based on VPX bus, this general carrier plate comprises: power module, VPX connector, FMC connector and fpga chip, is characterized in that: described fpga chip is Virtex-6 HXT FPGA; The plug-in two 256MB DDR2 SDRAM of described fpga chip.

2. a kind of 3U general carrier plate of the FMC structure based on VPX bus as described in claim 1, is characterized in that: described fpga chip comprises: front-end interface module, data cache module and back end interface module.

3. the method for designing of the 3U general carrier plate of the FMC structure based on VPX bus as described in claim 1, comprise the signal processing between signal processing and transmission, support plate and backboard in plate and be connected, signal processing between support plate and function daughter board be connected and structural design, it is characterized in that:

(1) FPGA of support plate employing a slice Virtex 6 series is core, the DDR2 internal memory of plug-in 512M; Support FMC-HPC, gigabit Ethernet, 2 road X4 PCIe, wherein PCIe interface changes sRIO into by revising software, and board provides 5V and 3.3V power supply by VPX interface, and wherein 3.3V is main power supply;

(2) support plate adopts the PI connector of VPX to be connected with backboard, carries out data transmission by gigabit Ethernet or PCIeX4;

(3) support plate and function daughter board adopt the connector of FMC structure, complete in the data transmission of each function daughter board;

4. support plate method for designing as claimed in claim 3, it is characterized in that: based on FMC standard, by daughter board size, connector and the module interface of standard are provided for FPGA on support plate, realizing I/O interface separates with FPGA, simplify I/O Design of Interface Module, maximize the recycling rate of waterused that improves subcard.

5. support plate method for designing as claimed in claim 4, is characterized in that: the highest support 533MT/s, and support user's secondary development.