CN111969052A - 一种具有多沟槽的双极结型晶体管 - Google Patents

一种具有多沟槽的双极结型晶体管 Download PDF

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CN111969052A
CN111969052A CN202010887628.3A CN202010887628A CN111969052A CN 111969052 A CN111969052 A CN 111969052A CN 202010887628 A CN202010887628 A CN 202010887628A CN 111969052 A CN111969052 A CN 111969052A
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李泽宏
程然
胡汶金
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

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Abstract

本发明属于功率半导体技术领域，涉及一种具有多沟槽的双极结型晶体管。本发明相比于传统工艺制作的双极结型晶体管，采用沟槽工艺来制作双极结型晶体管的发射区、基区以及集电区，一是沟槽工艺使得每个沟槽区域浓度分布更加均匀更容易控制，导通时的电流路径分布更加均匀，避免电流线集中在某一区域，增加了整个器件的可靠性；二是沟槽工艺可以提高整个器件的过电流能力，可以减小整个器件的面积，增加了其电流泄放能力；最后沟槽工艺可以改善其结形貌，避免提前击穿，从而提高其击穿电压。

Description

一种具有多沟槽的双极结型晶体管
技术领域
本发明属于功率半导体技术领域，具体涉及一种具有多沟槽的双极结型晶体管。
背景技术
功率半导体器件在电力电子应用系统中处于非常重要的地位，是电力电子技术中进行电能变换、功率控制和处理，以及实现能量管理调节的核心器件。功率半导体器件应用非常广泛，从日常生活使用的计算机、汽车、数码相机等消费类电子到电气自动化中的大功率变换设备，以及远距离高压电力传输中用到的设备等。
在功率半导体中，双极结型晶体管能够放大信号，并且具有较好的功率控制、高速工作以及耐久能力，所以它常被用来构成放大器电路，或驱动扬声器、电动机等设备，并被广泛地应用于航空航天工程、医疗器械和机器人等应用产品中，图1为常规双极结型晶体管的结构示意图。虽然在传统的硅材料半导体器件领域，MOSFET等场效应器件己经占有了相当一部分市场份额，但是双极结型晶体管在高功率和高开关速等方面的应用仍然大有作为。
发明内容
本发明就是根据传统的双极结型晶体管结构，对其发射极以及集电极进行优化，提出了一种具有多沟槽的双极结型晶体管结构。
本发明的技术方案是：一种具有多沟槽的双极结型晶体管，如图2所示，包括N型衬底201、位于N型衬底201下表面的集电极208、位于N型衬底201上表面的P型基区202和N型区，在P型基区202上层远离N型区的一端具有N型重掺杂区，在N型重掺杂区上表面具有发射极207，在P型基区202上表面具有基极205，N型区、P型基区202和N型重掺杂区上表面除基极205和发射极207外的部分覆盖有介质层206；所述N型区中具有多个沟槽，形成N型沟槽扩散区203；所述N型重掺杂区中具有多个沟槽，形成N型重掺杂沟槽扩散区204；在基极205下方，P型基区202上层具有多个沟槽，形成与基极205接触的P型多晶硅沟槽区211。
进一步的，所述介质层206采用的材料为二氧化硅。
上述方案中的N型沟槽扩散区203，N型重掺杂沟槽扩散区204，P型多晶硅沟槽区211沟槽的横向宽度和纵向长度，沟槽间的横向间距以及沟槽数量都可以根据实际情况进行变化。
本发明的有益效果为：相比于传统工艺制作的双极结型晶体管，采用沟槽工艺来制作双极结型晶体管的发射区、基区以及集电区，一是沟槽工艺使得每个沟槽区域浓度分布更加均匀更容易控制，导通时的电流路径分布更加均匀，避免电流线集中在某一区域，增加了整个器件的可靠性；二是沟槽工艺可以提高整个器件的过电流能力，可以减小整个器件的面积，增加了其电流泄放能力；最后沟槽工艺可以改善其结形貌，避免提前击穿，从而提高其击穿电压。
附图说明
图1为常规双极结型晶体管的结构示意图；
图2为本发明的一种具有多沟槽的双极结型晶体管的结构示意图；
具体实施方式
下面结合附图，详细描述本发明的技术方案：
如图2所示，本发明的具有多沟槽的双极结型晶体管包括N型衬底201，P型基区202，N型沟槽扩散区203，N型重掺杂沟槽扩散区204，N型多晶硅沟槽区209，N型多晶硅重掺杂沟槽区210，P型多晶硅沟槽区211，基极电极205，发射极电极207，介质层206，集电极电极208。所述的P型基区202形成于N型衬底201之上；所述的N型沟槽扩散区203形成于P型基区202内并且与N型衬底201相通；所述P型多晶硅沟槽区211位于P型基区202表面；所述的N型重掺杂沟槽扩散区204形成于P型基区202内；所述的N型沟槽扩散区203是由N型多晶硅沟槽区209高温退火扩散形成的；所述的N型重掺杂沟槽扩散区204是由N型多晶硅重掺杂沟槽区210高温退火扩散形成的；所述的基极电极205位于P型多晶硅沟槽区211表面并与之相接触；所述的发射极电极207位于N型多晶硅重掺杂沟槽区210上并与之相接触；所述的基极电极205和发射极电极207通过介质层206相隔离；所述的集电极电极208位于N型衬底201的底部并与之相接触。
所述沟槽结构包括N型多晶硅沟槽区209、N型多晶硅重掺杂沟槽区210以及P型多晶硅沟槽区211；所述的N型多晶硅沟槽区209的深度一致，且每个沟槽的间隔均相同；所述的N型沟槽扩散区203是由N型多晶硅沟槽区209高温退火扩散形成；所述的N型多晶硅重掺杂沟槽区210的深度一致，且每个沟槽的间隔均相同；所述P型多晶硅沟槽区211的深度一致，且每个沟槽的间隔均相同；所述的N型重掺杂沟槽扩散区204是由N型多晶硅重掺杂沟槽区210高温退火扩散形成的；所述的N型沟槽扩散区203与P型基区202以及N型重掺杂沟槽扩散区204通过介质层206相隔离。
以NPN型双极结型晶体管为例，说明本发明的工作原理：
本发明提供一种具有多沟槽的双极型晶体管，在P型基区202内通过刻蚀形成N型多晶硅沟槽区209，并通过高温退火扩散形成N型沟槽扩散区203，再通过刻蚀形成N型多晶硅重掺杂沟槽区210，并通过高温退火扩散形成N型沟槽扩散区204，另外刻蚀P型多晶硅沟槽区211。当发射极电极207正偏，集电极208反偏，N型多晶硅重掺杂沟槽区210与P型基区202形成反向偏置的PN结，随着发射极电极207的电压逐渐增大，N型多晶硅重掺杂沟槽区210与P型基区202的PN结耗尽区会随之扩展，直至发生雪崩击穿，当雪崩击穿发生时，形成一条途径P型多晶硅沟槽区211以及N型多晶硅沟槽区209最后流向集电极电极208的电流路径。
相对于传统的双极性晶体管制作，由于N型多晶硅沟槽区209，N型多晶硅重掺杂沟槽区210，P型多晶硅沟槽区211均是由沟槽工艺制作而成，浓度分布更加均匀，导通时电流途径的面积更多，对于电流的泄放能力更强；N型沟槽扩散区203以及N型沟槽扩散区204均是通过深槽注入多晶硅在高温退火扩散形成的，相比于穿通的双极结型晶体管结的形成，减少了横扩；最后沟槽工艺可以改善其结形貌，避免提前击穿，从而提高其击穿电压。

Claims (2)

1.一种具有多沟槽的双极结型晶体管，包括N型衬底(201)、位于N型衬底(201)下表面的集电极(208)、位于N型衬底(201)上表面的P型基区(202)和N型区，在P型基区(202)上层远离N型区的一端具有N型重掺杂区，在N型重掺杂区上表面具有发射极(207)，在P型基区(202)上表面具有基极(205)，N型区、P型基区(202)和N型重掺杂区上表面除基极(205)和发射极(207)外的部分覆盖有介质层(206)；其特征在于，
所述N型区中具有多个沟槽，形成N型沟槽扩散区(203)；所述N型重掺杂区中具有多个沟槽，形成N型重掺杂沟槽扩散区(204)；在基极(205)下方，P型基区(202)上层具有多个沟槽，形成与基极(205)接触的P型多晶硅沟槽区(211)。
2.根据权利要求1所述的一种具有多沟槽的双极结型晶体管，其特征在于，所述介质层采用的材料(206)为二氧化硅。
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