US20010013635A1 - Bipolar transistor with trenched-groove isolation regions - Google Patents
Bipolar transistor with trenched-groove isolation regions Download PDFInfo
- Publication number
- US20010013635A1 US20010013635A1 US09/045,794 US4579498A US2001013635A1 US 20010013635 A1 US20010013635 A1 US 20010013635A1 US 4579498 A US4579498 A US 4579498A US 2001013635 A1 US2001013635 A1 US 2001013635A1
- Authority
- US
- United States
- Prior art keywords
- area
- transistor
- transistor area
- forming
- base electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 239000003989 dielectric material Substances 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 64
- 238000000034 method Methods 0.000 claims description 60
- 238000005530 etching Methods 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 41
- 238000004519 manufacturing process Methods 0.000 claims description 31
- 238000000151 deposition Methods 0.000 claims description 14
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000012535 impurity Substances 0.000 description 15
- 230000003071 parasitic effect Effects 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 210000003323 beak Anatomy 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
Definitions
- the present invention relates to the structures of semiconductor transistors and to fabrication processes therefor, particularly to thoseof bipolar transistors.
- a trenched-groove isolation method in whicn first, grooves such as trenched-grooves are formed, and then embedded using a dielectric material, is effective, since there is no problem due to the birds beak, unlike in the LOCOS process. Therefore, the trenched-groove isolation method is preferable to reduce the minimum transistor size due to the narrower isolation area and due to the possibility of building the isolation area near an active area of the transistor.
- a method using dielectric materials such as BPSG (Boro-Phospho-Silicate-Glass), etc., which can exhibit “re-flow” characteristics at high temperatures, is effective for isolating transistors with reduced parasitic capacitances.
- BPSG Bo-Phospho-Silicate-Glass
- the “re-flow” characteristics means to exhibits a flowability with changing the surrounding condition, that is increasing temperature, for example.
- FIGS. 21 and 16 show a first related art, which are a schematic cross section and a plan view of a conventional bipolar transistor, respectively.
- the schematic cross section is the view from the line CW-CW in FIG. 16.
- a bipolar transistor A is formed on the semiconductor substrate 1 , within the transistor area B in the form of an island.
- this transistor area B a highly-doped n-type semiconductor layer 2 (collector contact layer), lightly-doped n-type semiconductor layer 3 (collector layer), p-type semiconductor layer 12 (intrinsic base layer), and the upper surface, a highly-doped n-type semiconductor layer 15 (emitter layer) is formed; consequently, an npn-type bipolar transistor structure is produced.
- a trenched-isolator 4 On the outside of the npn-type bipolar transistor structure, there exists a trenched-isolator 4 , which electrically isolate between the transistors and other electrical elements from one another.
- the field area is covered with oxide layer 5 .
- the base electrode 9 is formed using a highly-doped p-type poly-silicon (poly-Si), whereas the emitter electrode 16 is formed using a highly-doped n-type poly-Si.
- a silicon-nitride layer 10 and a side wall structure formed using a dielectric layer 14 are inserted therebetween for isolation.
- the base electrode 9 is in contacted with the base layer at each end section of the base layer. On each end section, the doping concentration and the depth of the base layer is greater and thicker than that of the intrinsic base region. This highly-doped and thicker region is the so-called “graft-base layer” 13 .
- FIGS. 17 to 21 explain the fabrication process of the bipolar transistors.
- highly-doped n-type semiconductor layer 2 , and lightly-doped n-type layer 3 were formed on a semiconductor substrate 1 .
- the trenched-groove isolation regions 4 were formed in the outer peripheral region which surround the transistor region.
- oxide layer 5 is formed over the entire surface of the semiconductor substrate 1 , then a base contact region 7 is formed by wet etching of the upper oxide layer at the opening region of the base contact region 7 , by using a photoresist as a mask 6 .
- the remaining oxide layer 5 is then etched using anisotropic dry etching, resulting in a complete opening through the base contact region 7 .
- p-type poly-Si layer 9 After removing the photoresist mask 6 , p-type poly-Si layer 9 , by addition of a p-type impurity, is deposited on the entire substrate.
- the base electrode was formed by etching the poly-Si layer to a predetermined shape.
- a nitride layer 10 was deposited on the whole surface of the substrate 1 (FIG. 19).
- An opening for an emitter contact is then formed by using an anisotropic dry etching of both the nitride layer 10 and a highly-doped p-type poly-Si layer.
- the p-type intrinsic base layer 12 and a side-wall formed by dielectric materials were then formed, resulting in isolation of the highly-doped poly-Si 9 that will from the base electrode.
- a highly-doped graft-base layer 13 is formed by diffusion of the p-type impurity in the highly-doped poly-Si 9 into the semiconductor layer by heat-treatment after deposition of the highly-doped poly-Si 9 .
- an emitter electrode is formed using a highly-doped poly-Si 16 doped with an n-type impurity; a highly-doped n-type emitter layer 16 is then formed by diffusing an n-type impurity into the semiconductor layer originated form the highly-doped n-type poly-Si 16 during this heat treatment.
- a second related art disclosed a structure with a minimized alignment margin region using a self-aligning process. This second process forms the contact region of the base electrode using a self-aligning technique.
- the fabrication process is as follows.
- FIG. 27 and FIG. 22 show a cross section and a plan view of the self-aligned base electrode.
- this structure as the contact region of the base-electrode is determined at the emitter opening region in a self-aligned manner, no shift in alignment during the alignment process of opening the base contact is expected, so there will be no offset of the contact region of the base electrode, resulting in constant contact of the base electrode connected to the base contact region.
- the opening of the emitter region is then formed using anisotropic dry etching of a nitride layer 10 and a highly-doped p-type poly-Si layer, and next, partial wet etching is performed to etch the spacer oxide layer 8 near the openings.
- the substrate is covered with poly-Si which was embedded under the highly-doped poly-Si 9 , under which the spacer oxide layer 8 was side-etched by previous wet etching.
- Poly-Si layer 11 is then etched back using an isotropic dry etching; poly-Si can remain only under the highly-doped poly-Si layer 9 where the spacer oxide layer 8 was side-etched. Then, the p-type intrinsic base layer 12 is formed, and then dielectric side-wall 14 was formed in order to isolate the emitter electrode of the highly-doped p-type poly-Si 9 and a base electrode.
- a highly-doped grafted-base layer 13 is formed by heat treatment after connecting it to the semiconductor area via poly-Si 11 . The heat treatment enhances the diffusion of the p-type impurity originally doped in the highly-doped poly-Si layer 9 , into the semiconductor area via poly-Si 11 .
- an emitter electrode is formed using a highly-doped n-type poly-Si 16 .
- the highly-doped n-type emitter layer 15 is formed by diffusion of the n-type impurity originating from the poly-Si 16 into the semiconductor layer by heat treatment.
- fabricated bipolar transistors can determine the width of the contact area of the base electrode with respect to the emitter opening region by using a self-aligning technique; there will be no shift of alignment when opening the base contact, and there will be no offset of the contact region of the base electrode, resulting in good contact of the base electrode
- Japanese Patent Application, First Publication, No. Sho 63-72159 discloses the third related art, which will be explained using FIGS. 28 and 29 thereof.
- bipolar transistors are isolated using a trenched-groove 4 , and the emitter area 8 and the base contact region 7 was self-aligned with respect to the isolation trench 4 .
- the alignment margin can be reduced, resulting in a reduction of device size, which has a merit of easy fabrication for high-density integrated circuits.
- the photoresist mask 6 for the opening of the base contact 7 should be formed to the inside of the base contact 7 by about 0.3 micron, because the base contact 7 is considered to be generally shifted by about 0.3 microns with respect to the edge of the isolation trench 4 in the conventional alignment process.
- the emitter region when forming the opening of the emitter region, should be formed to the inside of the base contact 7 by about 0.5 microns because the base contact 7 is considered to be generally shifted by about 0.3 microns with respect to the edge of the isolation trench 4 in the conventional alignment process to ensure that the base electrode contact width is larger than 0.2 microns, even if there exists a shift of the base contact region 17 in the same direction of the above shift in alignment.
- the problem is that the alignment margin of the opening for the base contact 7 with respect to the edge of an isolation trench is not much improved. Only a 0.2 micron improvement is achieved over the above first related art because of lack of improvement in the alignment margin of the opening with respect to the edge of the isolation trench 4 .
- the problem remains of the formation of a large parasitic capacitance of poly-Si in the region around the collector region formed by the highly-doped n-type semiconductor layer 2 and the lightly-doped n-type semiconductor layer 3 , because the highly-doped p-type poly-Si base electrode 9 was connected to the poly-Si in the trenched-groove, which will hinder an improvement in the microwave performance of transistors.
- the poly-Si buried in the trenched-groove 4 itself does not exhibit conductivity, it does not function as a base electrode up to the bottom of the trenched-groove 4 .
- the impurities in the highly-doped p-type poly-Si base electrode 9 can easily diffuse into the poly-Si in the trenched-groove 4 , the region functioning as a base electrode is unnecessarily spread over a large area, resulting in increased capacitances between the base and the collector, as well as between the base and the substrate.
- the poly-Si functions as a capacitor between the collector and the substrate, introducing the problem of formation of large capacitance due to the high dielectric constant of poly-Si compared to the dielectric layer.
- the semiconductor device comprises a bipolar transistor formed in the transistor area in the form of an island which is rectangular when viewed from above, in which, the isolation area is formed with dielectric materials around the outside of the transistor area, and the base area is formed around the emitter area which is formed at the central area of the transistor area, in which there is formed a contact groove at the inner interface of the isolation groove which faces the outer surface of the transistor area, and that a dart of the base electrode is embedded in the contact groove and faces at least one of the upper surface of the transistor area and a inner surface of the contact groove.
- the parasitic capacitance with respect to the substrate is reduced, resulting in improved microwave performance compared to that of bipolar transistors in which the isolation region is embedded, not with dielectric material, but with a poly-Si with a high dielectric constant. Furthermore, in the structure of this invention, as a portion of the base electrode is embedded into the contact groove, in which the base contact area is overlapped on the isolation area, which ensures electric contact of the base electrode on the base area both at the upper surface and the inner surface of the contact groove, in spite of any shift caused by alignment.
- the semiconductor devices according to the second aspect of the present invention comprises a bipolar transistor formed in a transistor area in the form of an island which is rectangular when viewed from above, in which the trenched-groove embedded with a dielectric layer as an isolation area formed around the transistor area, and the base area is formed around the emitter area which is formed at the central area of the transistor area, in which there is formed a contact groove at the inner interface of the trenched-groove which faces around the outer surface of the transistor area, and that a part of the base electrode is embedded in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.
- the parasitic capacitance with respect to the substrate is reduced, resulting in improved microwave performance, compared to that of the bipolar transistors in which the trenched-groove of the isolation region is embedded, not with a dielectric material, but with a poly-Si with a high dielectric constant.
- the structure of this invention as a portion of the base electrode is embedded in the contact groove, in which the base contact area overlaps the area of the trenched-groove, ensuring an electric contact of the base electrode to the base area both at the upper surface and the inner surface of the contact groove, in spite of any shift of alignment.
- the fabrication process for semiconductor devices comprises a step for forming a transistor area of a bipolar transistor in the form of an island which is rectangular viewed from above; a step of forming an isolation area by embedding dielectric material around the transistor area, in a manner so that the upper surface is planer on the whole surface of the substrate; a step for forming an opening larger than the transistor area; a step for exposing an upper surface and an upper-outside of the transistor area in the form of an island, by etching the dielectric layer within the openings; a step for forming a contact groove in proximity of the interface between the transistor area and the dielectric area by etching the dielectric layer in the contact groove by a predetermined thickness; a step for depositing the base electrode contact to at least one of the upper surface and the upper-outside of the transistor area in the form of an island, with the contact groove, as well as simultaneously burying a portion of the base electrode into the contact groove.
- the fabrication process for semiconductor devices according to the fourth aspect of the present invention comprises,
- the bipolar transistor according to the fifth aspect of the present invention is formed so that a side-wall using a dielectric material is inserted between the outside of the transistor area and the base electrode in the bipolar transistors.
- the side-wall structure prevents the short-circuiting between the outside of the transistor area and the base electrode.
- the fabrication process for semiconductor devices comprises; a step for forming a transistor area of a bipolar transistor in the form of an island which is rectanglar when viewed from above; a step for forming an isolation area by embedding dielectric material around the transistor area, in a manner so that the upper surface is planer on the whole surface of the substrate; a step for forming an opening larger than the transistor area; a step for exposing an upper surface and an upper-outside of the transistor area by etching the dielectric layer within the opening; a step for forming a contact groove in proximity of the interface between the transistor area and the dielectric area by etching the dielectric layer in the contact groove by a predetermined thickness; a step for depositing an oxide layer selectively at the upper surface and the upper-outside of the transistor area; a step for depositing the base electrode in the contact groove; a step for forming a second opening for the formation of the emitter area within the surface of the base electrode; a step for forming a second opening for the formation of the emitter
- the base electrode does not contact the outside of the transistor area, since the contact width of the base electrode is self-aligned and is determined by the connection with the width of the side-etching of the oxide layer.
- the fabrication process for semiconductor devices comprises a step for forming a transistor area of a bipolar transistor in the form of an island which is rectangular when viewed from above, a step for forming a trenched-groove around the transistor area for isolation by embedding dielectric material around the transistor area, in a manner so that the upper surface is planer on the whole surface of the substrate; a step for forming the openings larger than the transistor area and smaller than the trenched-groove; a step for exposing an upper surface and an upper-outside of the transistor area by etching the dielectric layer within the opening; a step for forming a contact groove in proximity of the interface between the transistor area and the dielectric area within the openings by etching the dielectric layer within the contact groove by a predetermined thickness; a step for depositing a base electrode contact to at least one of the upper surface and the upper-outside of the transistor area in the contact groove as well as embedding a portion of the base electrode into the contact
- the base electrode does not contact the outside of the transistor area, since the contact width of the base electrode is self-aligned and is determined according to the width of the side-etching of the oxide layer.
- the fabrication process according to the eighth aspect of the present invention comprises a step for forming an isolation area by embedding dielectric material which exhibits re-flow characteristics with increasing temperature.
- the fabrication process according to the ninth aspect of the present invention comprises a step for forming an isolation area by embedding dielectric material made of BPSG.
- FIG. 1 is a plan view of a bipolar transistor according to the first embodiment of the present invention
- FIG. 2 is a cross section (along line X-X in FIG. 1) of a bipolar transistor according to the first embodiment of the present invention
- FIGS. 3 to 7 are cross sections showing a fabrication process of the bipolar transistor according to the first embodiment of the present invention.
- FIG. 8 is a plan view of a bipolar transistor according to the second embodiment of the present invention.
- FIG. 9 is a cross section (along line X-X line in FIG. 8) of a bipolar transistor according to the second embodiment of the present invention.
- FIGS. 10 to 14 are cross sections showing a fabrication process of the bipolar transistor according to the first embodiment of the present invention.
- FIG. 15 is a cross section of a bipolar transistor according to the third embodiment of the present invention.
- FIG. 16 is a plan view of a bipolar transistor according to the first related art
- FIGS. 17 to 21 are cross sections showing the bipolar transistor fabricated according to the first related art
- FIG. 22 is a plan view of a bipolar transistor according to the second related art
- FIGS. 23 to 27 are cross sections showing a bipolar transistor fabricated according to the second related art
- FIG. 28 is a plan view of a bipolar transistor according to the third related art.
- FIG. 29 is a cross section of a bipolar transistor according to the third related art.
- FIGS. 1 to 7 a first embodiment of the bipolar transistor of the present invention will be explained.
- FIG. 1 is a plan view and FIG. 2 is a cross section of the transistor according to the first embodiment of the invention, in which is provided a semiconductor substrate 1 .
- a transistor area B in the form of the island which is rectangular when viewed from above is disposed.
- a bipolar transistor A is formed within the transistor area B.
- An isolation area 4 is formed of a first dielectric layer 4 a formed with SiO2.
- abase layer 12 is formed surrounding the emitter layer 15 formed on the upper surface B 2 .
- the transistor A is one in which contact groove 31 is formed within the isolation region 4 at around the contacting interface 4 b contacting the outside B 1 of the transistor area B.
- the base electrode 9 is then embedded in the contact groove 31 , in a manner so as to contact the upper surface B 2 and outside B 1 , in the vicinity of the corner 33 formed by the upper surface B 2 and outside B 1 .
- transistor area B for bipolar transistor A in the form of an island which is rectangular when viewed from above, is formed.
- the stacked layer of a highly-doped n-type semiconductor layer 2 and a lightly-doped n-type semiconductor layer 3 is formed by using a epitaxial growth technique of lightly-doped n-type semiconductor layer 3 on the whole area of the substrate, after forming a highly-doped n-type semiconductor layer 2 , by adding selectively, an n-type impurity on the predetermined area on the p-type semiconductor substrate 1 .
- the isolation trench 4 is then formed at the outside of the transistor area B, up to the level of the substrate 1 .
- the isolation trench 4 is formed by selective etching of Si through the lightly-doped n-type semiconductor layer 3 and to reach the upper surface of the p-type semiconductor substrate 1 , in order to form a groove to be embedded in a dielectric layer.
- the depth of the groove is approximately 5 microns, the width is 1 micron.
- the dielectric layer used is, for example, BPSG which exhibits so called “re-flow” characteristics with increased temperature.
- the gap between the dielectric surface of the dielectric layers grown from each side of the groove is closed by the re-flow of BPSG.
- BPSG contains both highly-doped boron and phosphorus, they will act as a diffusion source when directly grown on the semiconductor.
- a device such as one concerned on the inner surface of the contact groove by a thermally-grown oxide layer or nitride layer, as the BPSG, will not contact the semiconductor layer directly.
- an opening larger than the transistor area B is formed for the base contact 7 using a photoresist as a mask 6 .
- the photoresist mask 6 for use in the opening of the base contact is formed within the area where at least three edges of the rectangular semiconductor area, which has four edges surrounded by the isolation trench 4 , are in the opening, by approximately 0.3 microns (denoted by reference numeral 7 ).
- the oxide layer 5 is sufficiently thick enough to etch the oxide layer 5 to a depth of more than half the entire thickness.
- the opening is then formed by etching off the remaining oxide layer 5 using an anisotropic dry etching.
- the groove in the dielectric layer is formed with a depth of around 0.2 microns at the inside of the isolation trench, as well as exposing the edge of the semiconductor area A as shown in FIG. 4.
- the upper surface B 2 and the upper outside B 1 of the transistor area B is exposed.
- the dielectric layer 4 a of the predetermined thickness which is embedded into the gap formed between the opening and the edge of transistor area B, is etched off, forming a contact groove 31 at the area near to the interface of the transistor area B and the dielectric layer 4 a.
- the intrinsic base area 12 is formed by diffusing a dopant, and after depositing the third dielectric layer 14 (not shown), a side-wall 14 a of a dielectric layer was formed using an anisotropic dry-etching method.
- the graft base layer 13 with a first conductive type (p-type in this case), is connected to the first conductive type poly-Si 9 as a base electrode and the first conductive type intrinsic base layer 12 by diffusing the first conductive-type impurity originated from the first conductive-type poly-Si 9 into the lightly-doped semiconductor layer 3 with a second conductive-type impurity (n-type in this case) by heat treatment after the growth of the first conductive-type poly-Si 9 .
- the emitter electrode was formed using a highly-doped impurity of the second conductive type poly-Si 16 , then the second conductive-type emitter layer 15 was formed by diffusing the impurity of the second conductive-type from the poly-Si 16 into the intrinsic base layer 12 by heat treatment.
- the parasitic capacitance relative to the substrate was reduced, compared to the conventional structure with an isolation trench groove buried with a poly-Si which exhibits a high dielectric constant. Since the dielectric layer with a lower dielectric constant was embedded in that groove, which improved the microwave performance of the transistor. This improvement in microwave performance is more pronounced as the transistor size is reduced.
- the bottom area of the transistor for this invention is reduced by about 40%, and the total length around the transistor for this invention is reduced by about 20%, and therefore, the parasitic capacitance between the collector and the substrate is reduced by about 25%.
- the margin of the contact area of the base electrode is designed in the direction of the depth of the contact groove. Therefore, if an alignment shift in the direction parallel to the surface of the substrate occurs in the formation process of the base electrode, good contact will be ensured since the base electrode contacts both the upper surface and the outside of the semiconductor area. Thus, the necessary contact area will be satisfactory, since the contact at the side makes up for the loss of the contact area at the upper surface due to any shift of alignment.
- the shift of alignment in the formation process of the opening affects the width of the highly-doped p type poly-Si 9 embedded in the contact groove of the isolation trench 4 .
- the depth of the contact groove is defined as the amount of over etching which was done in the process of the opening of the base contact area, so the contact area of the base electrode to the base layer is essentially constant, even if the shift of the alignment occurs.
- This constant contact area introduces a stable extracting of the base electrode from the stand-point of providing a constant contact resistance of the base electrode.
- FIG. 8 is a plan view of the semiconductor device 1 of this invention, and FIG. 9 is cross section of the device.
- the second embodiment differs from the first embodiment in that the semiconductor device has a side-wall of dielectric 8 between the outside B 1 of the transistor area B and the base electrode 9 .
- the semiconductor area within the base contact was covered with a spacer oxide 8 having a thickness of 20 nanometers to 100 nanometers by thermal oxidation of the entire surface of the substrate.
- the poly-Si 9 of a first conductive-type which will be a base electrode, is deposited on the entire surface of the substrate, etched to form a desired shape, and then covered with a dielectric nitride layer 10 over the entire surface of the substrate.
- the dielectric oxide of the side-wall 8 is etched by the isotropic etching method. This isotropic etching is performed until the edge surface in the isolation trench of the side of the transistor area is exposed by side-etching of the oxide layer 8 under the poly-Si of the first conductive-type.
- a poly-Si 11 is deposited over the entire surface of the substrate, the poly-Si 11 is embedded under the side-etched space 51 , which is formed under the first conductive-type poly-Si 9 by side-etching of the oxide layer 8 under the poly-Si 9 . After that, the poly-Si 11 remains only at the side-etched space 51 by using a etch-back method for poly-Si 11 using an isotropic etching method.
- a first conductive intrinsic base 12 is formed, and then side-wall 14 of dielectric material is formed, which isolates the first conductive poly-Si 9 so as to be a base electrode.
- the first conductive graft-base layer 13 is then formed by diffusing the first conductive impurity originating from the first conductive poly-Si 9 into the semiconductor layer, caused by a heat treatment after the connection of the first conductive poly-Si 9 (to be a base electrode) and semiconductor area via poly-Si 11 .
- the emitter electrode is formed using a highly-doped poly-Si (to be an emitter electrode) of the second conductive impurity. Then, the second conductive emitter layer 15 is formed by diffusing the second conductive impurity originated from poly-Si 16 into the semiconductor area by heat treatment.
- the side-wall dielectric layer is inserted between the outside and the base electrode, it is possible to prevent contact with the outer side and the base electrode.
- FIG. 9 shows a the cross section in the second embodiment shown in FIG. 14 assuming the occurrence of a shift in alignment in the process of an emitter opening, shown in FIG. 12, on the left side.
- the shift of alignment of an opening process for an emitter affects the variation of the distance between the location of the emitter opening and the isolation trench 4 .
- the contacting width of the poly-Si 11 and the transistor area B is determined as a function of the amount of side-etching measured from the opening edge of the emitter area.
- said space oxide layer 8 is also formed at the side of the contact groove 31 in the isolation trench 4 .
- the etching of the spacer oxide 8 of the isolation trench 4 After the etching of the spacer oxide 8 of the isolation trench 4 , the etching proceeded in the direction of the depth of the layer, along the contact groove 31 , by etching the highly-doped p-type poly-Si 9 embedded in the contact groove 31 . Therefore, the amount of side-etching of the spacer oxide layer 8 is not restricted by the existence of the shift of distance between the location of the emitter opening and the isolation trench 4 .
- poly-Si 11 is connected to both the side and the upper surface of the transistor area B on the left, and is connected to only the upper surface on the right of the transistor area B, the contact width which is proportional to the contact area of the base electrode to the base area, which is the sum of the upper surface and the side areas, will not be affected by the shift of alignment of the surface of the substrate, and a desired contact width of the base electrode both the on left and the right of the base electrode can be ensured.
- the contact width of the base electrode can be determined by the self-alignment, no shift of the contact area of the base electrode will occur due to the shift of alignment in the opening process for the base contact. Furthermore, the contact width of the base electrode is determined in a self-aligning manner due to the amount of side-etching of the oxide layer 8 , and it is therefore possible to precisely control the contact width of the base electrode, since it is possible to contact both the semiconductor surface and the side of the transistor in a self-aligned manner like the structures explained in the first embodiment.
- the contact area of the base electrode does not vary due to the shift in alignment in the process for the opening of the base contact; however, there occurs an shift (imbalance) of the connection area of the base electrode due to the shift of alignment, toward the direction of the shift of alignment.
- the shift (imbalance) of the contacting area of the base electrode due to the shift of alignment in the process of the opening for the emitter can be prevented by embedding a part of the base electrode 19 into the contact groove 31 formed in the isolation trench 4 and by forming a spacer oxide 8 to cover the side of the semiconductor area.
- isolation between the devices was accomplished by using an isolation trench 4 , whereas the isolation area in the third and the fourth embodiments, which is surrounding the transistor area A (that is, the so-called “field area”), is embedded in the dielectric layer 20 and leveled.
- a lightly-doped n-type semiconductor layer 3 , a highly-doped n-type semiconductor layer 2 , and the upper surface of the p-type semiconductor substrate 1 of the area other than the transistor area B are selectively etched, forming a transistor area in the form of an island, and then the dielectric material is embedded in the field area using a dielectric layer 20 around the transistor area.
- the height of this so-called “island” is ordinarily about 3 to 5 microns, so the BPSG, etc., exhibiting the above reflow characteristics at high temperature is effective, in the view of the embedding of the isolation area with such a large step.
- the process is, after embedding the recessed part using low-pressure CVD, the sharp step formed by the dielectric materials deposited on the island structure will be smoothed, and the depth of the step will be decreased. After that, perfect planarization is performed using a decreased mechanical polishing method. In this process, it is necessary to cover the side of the transistor area using a thermally grown oxide or nitride layer in order to prevent the direct contact of the BPSG and the semiconductor surface.
- the above isolation structure can also be adopted if the interface between the dielectric layer and the transistor area is approximately perpendicular without a birds beak.
- the isolation area it is not necessary for the isolation area to use a trenched groove, which can be embedded by using a dielectric layer grown by a CVD method; it can instead be isolated by growing a dielectric layer on the area other than the transistor area, which is an island-form semiconductor area.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
- This application is based on Patent Application No. Hei 8-278321, filed in Japan, the contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to the structures of semiconductor transistors and to fabrication processes therefor, particularly to thoseof bipolar transistors.
- 2. Related Art
- As is well known, reduction of transistor size in bipolar transistors is very effective for reducing parasitic capacitance from the standpoint of improving microwave performance thereof.
- For reducing parasitic capacitance, it is very important to isolate transistors from one another.
- Generally, in the case of fabrication of Si bipolar transistors on a Si substrate, local oxidation of Si (LOCOS) processes are used for isolation. However, this is not satisfactory due to problems related to the reduction of effective transistor areas and that of the open leads caused by the birds beak.
- Here, another method for isolation, a trenched-groove isolation method, in whicn first, grooves such as trenched-grooves are formed, and then embedded using a dielectric material, is effective, since there is no problem due to the birds beak, unlike in the LOCOS process. Therefore, the trenched-groove isolation method is preferable to reduce the minimum transistor size due to the narrower isolation area and due to the possibility of building the isolation area near an active area of the transistor.
- In particular, a method using dielectric materials such as BPSG (Boro-Phospho-Silicate-Glass), etc., which can exhibit “re-flow” characteristics at high temperatures, is effective for isolating transistors with reduced parasitic capacitances. In this description, the “re-flow” characteristics means to exhibits a flowability with changing the surrounding condition, that is increasing temperature, for example.
- FIGS. 21 and 16 show a first related art, which are a schematic cross section and a plan view of a conventional bipolar transistor, respectively. The schematic cross section is the view from the line CW-CW in FIG. 16.
- As shown in these figures, a bipolar transistor A is formed on the semiconductor substrate1, within the transistor area B in the form of an island.
- In this transistor area B, a highly-doped n-type semiconductor layer2 (collector contact layer), lightly-doped n-type semiconductor layer 3 (collector layer), p-type semiconductor layer 12 (intrinsic base layer), and the upper surface, a highly-doped n-type semiconductor layer 15 (emitter layer) is formed; consequently, an npn-type bipolar transistor structure is produced. On the outside of the npn-type bipolar transistor structure, there exists a trenched-
isolator 4, which electrically isolate between the transistors and other electrical elements from one another. - In addition, the field area is covered with
oxide layer 5. On the upper oxide layer of thecollector leading section 19, thebase leading section 18, and the opening (contact hole) of the emitter leading section, there are through holes, each for respectively contacting these electrodes and the upper lead line. Here, thebase electrode 9 is formed using a highly-doped p-type poly-silicon (poly-Si), whereas theemitter electrode 16 is formed using a highly-doped n-type poly-Si. As shown in this figure, a silicon-nitride layer 10 and a side wall structure formed using adielectric layer 14 are inserted therebetween for isolation. In addition, thebase electrode 9 is in contacted with the base layer at each end section of the base layer. On each end section, the doping concentration and the depth of the base layer is greater and thicker than that of the intrinsic base region. This highly-doped and thicker region is the so-called “graft-base layer” 13. - FIGS.17 to 21 explain the fabrication process of the bipolar transistors. First, highly-doped n-
type semiconductor layer 2, and lightly-doped n-type layer 3 were formed on a semiconductor substrate 1. Then, the trenched-groove isolation regions 4 were formed in the outer peripheral region which surround the transistor region. Next,oxide layer 5 is formed over the entire surface of the semiconductor substrate 1, then abase contact region 7 is formed by wet etching of the upper oxide layer at the opening region of thebase contact region 7, by using a photoresist as amask 6. Theremaining oxide layer 5 is then etched using anisotropic dry etching, resulting in a complete opening through thebase contact region 7. - After removing the
photoresist mask 6, p-type poly-Si layer 9, by addition of a p-type impurity, is deposited on the entire substrate. The base electrode was formed by etching the poly-Si layer to a predetermined shape. - Next, a
nitride layer 10 was deposited on the whole surface of the substrate 1 (FIG. 19). An opening for an emitter contact is then formed by using an anisotropic dry etching of both thenitride layer 10 and a highly-doped p-type poly-Si layer. The p-typeintrinsic base layer 12 and a side-wall formed by dielectric materials were then formed, resulting in isolation of the highly-doped poly-Si 9 that will from the base electrode. A highly-doped graft-base layer 13 is formed by diffusion of the p-type impurity in the highly-doped poly-Si 9 into the semiconductor layer by heat-treatment after deposition of the highly-doped poly-Si 9. - Finally, an emitter electrode is formed using a highly-doped poly-
Si 16 doped with an n-type impurity; a highly-doped n-type emitter layer 16 is then formed by diffusing an n-type impurity into the semiconductor layer originated form the highly-doped n-type poly-Si 16 during this heat treatment. - A second related art disclosed a structure with a minimized alignment margin region using a self-aligning process. This second process forms the contact region of the base electrode using a self-aligning technique. The fabrication process is as follows.
- FIG. 27 and FIG. 22 show a cross section and a plan view of the self-aligned base electrode. In this structure, as the contact region of the base-electrode is determined at the emitter opening region in a self-aligned manner, no shift in alignment during the alignment process of opening the base contact is expected, so there will be no offset of the contact region of the base electrode, resulting in constant contact of the base electrode connected to the base contact region.
- The fabrication process for the above self-aligned bipolar transistors will be explained with reference to FIGS.23 to 27. In this self-aligned transistor, as in the conventional fabrication process as explained in the first related art, after completing the opening through the
base contact region 7 and removing the photoresist mask, the base contact region is covered by about a 50-nm-thickspacer oxide layer 8 grown using a thermal oxidation method. Next, p-type poly-Si is grown over the entire surface, followed by the processes to form a desired shape and covering the whole surface withnitride 10. - The opening of the emitter region is then formed using anisotropic dry etching of a
nitride layer 10 and a highly-doped p-type poly-Si layer, and next, partial wet etching is performed to etch thespacer oxide layer 8 near the openings. After this, the substrate is covered with poly-Si which was embedded under the highly-doped poly-Si 9, under which thespacer oxide layer 8 was side-etched by previous wet etching. - Poly-
Si layer 11 is then etched back using an isotropic dry etching; poly-Si can remain only under the highly-doped poly-Si layer 9 where thespacer oxide layer 8 was side-etched. Then, the p-typeintrinsic base layer 12 is formed, and then dielectric side-wall 14 was formed in order to isolate the emitter electrode of the highly-doped p-type poly-Si 9 and a base electrode. A highly-doped grafted-base layer 13 is formed by heat treatment after connecting it to the semiconductor area via poly-Si 11. The heat treatment enhances the diffusion of the p-type impurity originally doped in the highly-doped poly-Si layer 9, into the semiconductor area via poly-Si 11. - Finally, an emitter electrode is formed using a highly-doped n-type poly-
Si 16. The highly-doped n-type emitter layer 15 is formed by diffusion of the n-type impurity originating from the poly-Si 16 into the semiconductor layer by heat treatment. - Therefore, fabricated bipolar transistors can determine the width of the contact area of the base electrode with respect to the emitter opening region by using a self-aligning technique; there will be no shift of alignment when opening the base contact, and there will be no offset of the contact region of the base electrode, resulting in good contact of the base electrode
- Japanese Patent Application, First Publication, No. Sho 63-72159 discloses the third related art, which will be explained using FIGS. 28 and 29 thereof. In this structure, bipolar transistors are isolated using a trenched-
groove 4, and theemitter area 8 and thebase contact region 7 was self-aligned with respect to theisolation trench 4. As a result, the alignment margin can be reduced, resulting in a reduction of device size, which has a merit of easy fabrication for high-density integrated circuits. - However, in the above three related arts, there are some problems to be solved.
- In the first related art, the
photoresist mask 6 for the opening of thebase contact 7 should be formed to the inside of thebase contact 7 by about 0.3 micron, because thebase contact 7 is considered to be generally shifted by about 0.3 microns with respect to the edge of theisolation trench 4 in the conventional alignment process. - In addition, when forming the opening of the emitter region, the emitter region should be formed to the inside of the
base contact 7 by about 0.5 microns because thebase contact 7 is considered to be generally shifted by about 0.3 microns with respect to the edge of theisolation trench 4 in the conventional alignment process to ensure that the base electrode contact width is larger than 0.2 microns, even if there exists a shift of thebase contact region 17 in the same direction of the above shift in alignment. - These problems presented a more difficult hurdle in reducing the transistor size, as the alignment margin area took up a larger proportion relative to the whole transistor area, thereby hindering further progress in device miniaturization.
- In the second related art, the problem is that the alignment margin of the opening for the
base contact 7 with respect to the edge of an isolation trench is not much improved. Only a 0.2 micron improvement is achieved over the above first related art because of lack of improvement in the alignment margin of the opening with respect to the edge of theisolation trench 4. - Furthermore, in the third related art, the problem remains of the formation of a large parasitic capacitance of poly-Si in the region around the collector region formed by the highly-doped n-
type semiconductor layer 2 and the lightly-doped n-type semiconductor layer 3, because the highly-doped p-type poly-Si base electrode 9 was connected to the poly-Si in the trenched-groove, which will hinder an improvement in the microwave performance of transistors. As the poly-Si buried in the trenched-groove 4 itself does not exhibit conductivity, it does not function as a base electrode up to the bottom of the trenched-groove 4. - However, as the impurities in the highly-doped p-type poly-
Si base electrode 9 can easily diffuse into the poly-Si in the trenched-groove 4, the region functioning as a base electrode is unnecessarily spread over a large area, resulting in increased capacitances between the base and the collector, as well as between the base and the substrate. Moreover, in the bottom portion of the trenched-groove 4, which does not function as a base electrode, the poly-Si functions as a capacitor between the collector and the substrate, introducing the problem of formation of large capacitance due to the high dielectric constant of poly-Si compared to the dielectric layer. - It is an object of the present invention to provide a structure and a fabrication process for the bipolar transistors with trenched-groove isolation regions, which can reduce the transistor area and parasitic capacitances to improve the microwave performance of the transistors, as well as the formation of the stable and reliable extraction of the base when the isolation region is formed at the location of contact region of the base electrode.
- In order to achieve this object, the semiconductor device according to a first aspect of the present invention comprises a bipolar transistor formed in the transistor area in the form of an island which is rectangular when viewed from above, in which, the isolation area is formed with dielectric materials around the outside of the transistor area, and the base area is formed around the emitter area which is formed at the central area of the transistor area, in which there is formed a contact groove at the inner interface of the isolation groove which faces the outer surface of the transistor area, and that a dart of the base electrode is embedded in the contact groove and faces at least one of the upper surface of the transistor area and a inner surface of the contact groove.
- In this bipolar transistor, the parasitic capacitance with respect to the substrate is reduced, resulting in improved microwave performance compared to that of bipolar transistors in which the isolation region is embedded, not with dielectric material, but with a poly-Si with a high dielectric constant. Furthermore, in the structure of this invention, as a portion of the base electrode is embedded into the contact groove, in which the base contact area is overlapped on the isolation area, which ensures electric contact of the base electrode on the base area both at the upper surface and the inner surface of the contact groove, in spite of any shift caused by alignment.
- The semiconductor devices according to the second aspect of the present invention comprises a bipolar transistor formed in a transistor area in the form of an island which is rectangular when viewed from above, in which the trenched-groove embedded with a dielectric layer as an isolation area formed around the transistor area, and the base area is formed around the emitter area which is formed at the central area of the transistor area, in which there is formed a contact groove at the inner interface of the trenched-groove which faces around the outer surface of the transistor area, and that a part of the base electrode is embedded in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.
- In this bipolar transistor, the parasitic capacitance with respect to the substrate is reduced, resulting in improved microwave performance, compared to that of the bipolar transistors in which the trenched-groove of the isolation region is embedded, not with a dielectric material, but with a poly-Si with a high dielectric constant. Furthermore, in the structure of this invention, as a portion of the base electrode is embedded in the contact groove, in which the base contact area overlaps the area of the trenched-groove, ensuring an electric contact of the base electrode to the base area both at the upper surface and the inner surface of the contact groove, in spite of any shift of alignment.
- The fabrication process for semiconductor devices according to the third aspect of the present invention comprises a step for forming a transistor area of a bipolar transistor in the form of an island which is rectangular viewed from above; a step of forming an isolation area by embedding dielectric material around the transistor area, in a manner so that the upper surface is planer on the whole surface of the substrate; a step for forming an opening larger than the transistor area; a step for exposing an upper surface and an upper-outside of the transistor area in the form of an island, by etching the dielectric layer within the openings; a step for forming a contact groove in proximity of the interface between the transistor area and the dielectric area by etching the dielectric layer in the contact groove by a predetermined thickness; a step for depositing the base electrode contact to at least one of the upper surface and the upper-outside of the transistor area in the form of an island, with the contact groove, as well as simultaneously burying a portion of the base electrode into the contact groove.
- It is easy to fabricate the bipolar transistor of the invention using this fabrication process.
- The fabrication process for semiconductor devices according to the fourth aspect of the present invention comprises,
- a step for forming a transistor area of a bipolar transistor in the form of an island and which is rectanglar when viewed from above; a step for forming trenched-groove around the transistor area for isolation by embedding dielectric material around the transistor area, in a manner so that the upper surface is planer on the whole surface of the substrate; a step for forming openings larger than the transistor area and smaller than the outside edge of the trenched-groove; a step for exposing an upper surface and an upper outside of the transistor area by etching the dielectric layer within the openings;
- a step for forming a contact groove in proximity to the interface between the transistor area and the dielectric area within the openings by etching the dielectric layer in the contact groove by a predetermined thickness; a step for depositing a base electrode contact with at least one of the upper surface and the upper-outside of the transistor area in the contact groove, as well as embedding a portion of the base electrode into the contact groove.
- It is easy to fabricate the bipolar transistor of the invention using this fabrication process.
- The bipolar transistor according to the fifth aspect of the present invention is formed so that a side-wall using a dielectric material is inserted between the outside of the transistor area and the base electrode in the bipolar transistors.
- The side-wall structure prevents the short-circuiting between the outside of the transistor area and the base electrode.
- The fabrication process for semiconductor devices according to the sixth aspect of the present invention comprises; a step for forming a transistor area of a bipolar transistor in the form of an island which is rectanglar when viewed from above; a step for forming an isolation area by embedding dielectric material around the transistor area, in a manner so that the upper surface is planer on the whole surface of the substrate; a step for forming an opening larger than the transistor area; a step for exposing an upper surface and an upper-outside of the transistor area by etching the dielectric layer within the opening; a step for forming a contact groove in proximity of the interface between the transistor area and the dielectric area by etching the dielectric layer in the contact groove by a predetermined thickness; a step for depositing an oxide layer selectively at the upper surface and the upper-outside of the transistor area; a step for depositing the base electrode in the contact groove; a step for forming a second opening for the formation of the emitter area within the surface of the base electrode; a step for forming the second gap between the base electrode and the transistor area by etching the oxide layer isotopically, which is deposited on the upper surface and the upper outside of the transistor area; and a step for embedding the said second gap in a poly-Si layer so as to electrically contact the base electrode and the transistor area.
- In the structure formed using this fabrication process, the base electrode does not contact the outside of the transistor area, since the contact width of the base electrode is self-aligned and is determined by the connection with the width of the side-etching of the oxide layer.
- The fabrication process for semiconductor devices according to the seventh aspect of the present invention comprises a step for forming a transistor area of a bipolar transistor in the form of an island which is rectangular when viewed from above, a step for forming a trenched-groove around the transistor area for isolation by embedding dielectric material around the transistor area, in a manner so that the upper surface is planer on the whole surface of the substrate; a step for forming the openings larger than the transistor area and smaller than the trenched-groove; a step for exposing an upper surface and an upper-outside of the transistor area by etching the dielectric layer within the opening; a step for forming a contact groove in proximity of the interface between the transistor area and the dielectric area within the openings by etching the dielectric layer within the contact groove by a predetermined thickness; a step for depositing a base electrode contact to at least one of the upper surface and the upper-outside of the transistor area in the contact groove as well as embedding a portion of the base electrode into the contact groove; a step for depositing the base electrode in the contact groove; a step for forming a second opening for the formation of the emitter area within the surface of the base electrode; a step for forming the second gap between the base electrode and the transistor area by etching the oxide layer isotropically, which is deposited on the upper surface and the upper outside of the transistor area; and a step for burying the second gap by a poly-Si layer to contact to the base electrode and the transistor area electrically.
- In the structure formed using this fabrication process, the base electrode does not contact the outside of the transistor area, since the contact width of the base electrode is self-aligned and is determined according to the width of the side-etching of the oxide layer.
- The fabrication process according to the eighth aspect of the present invention comprises a step for forming an isolation area by embedding dielectric material which exhibits re-flow characteristics with increasing temperature.
- The fabrication process according to the ninth aspect of the present invention comprises a step for forming an isolation area by embedding dielectric material made of BPSG.
- The above two fabrication processes enable smoothing of the sharp step formed at the edge of the isolation area.
- FIG. 1 is a plan view of a bipolar transistor according to the first embodiment of the present invention;
- FIG. 2 is a cross section (along line X-X in FIG. 1) of a bipolar transistor according to the first embodiment of the present invention;
- FIGS.3 to 7 are cross sections showing a fabrication process of the bipolar transistor according to the first embodiment of the present invention;
- FIG. 8 is a plan view of a bipolar transistor according to the second embodiment of the present invention;
- FIG. 9 is a cross section (along line X-X line in FIG. 8) of a bipolar transistor according to the second embodiment of the present invention;
- FIGS.10 to 14 are cross sections showing a fabrication process of the bipolar transistor according to the first embodiment of the present invention;
- FIG. 15 is a cross section of a bipolar transistor according to the third embodiment of the present invention;
- FIG. 16 is a plan view of a bipolar transistor according to the first related art;
- FIGS.17 to 21 are cross sections showing the bipolar transistor fabricated according to the first related art;
- FIG. 22 is a plan view of a bipolar transistor according to the second related art;
- FIGS.23 to 27 are cross sections showing a bipolar transistor fabricated according to the second related art;
- FIG. 28 is a plan view of a bipolar transistor according to the third related art; and
- FIG. 29 is a cross section of a bipolar transistor according to the third related art.
- Referring now to FIGS.1 to 7, a first embodiment of the bipolar transistor of the present invention will be explained.
- FIG. 1 is a plan view and FIG. 2 is a cross section of the transistor according to the first embodiment of the invention, in which is provided a semiconductor substrate1. On the substrate, a transistor area B in the form of the island which is rectangular when viewed from above is disposed. Within the transistor area B, a bipolar transistor A is formed. An
isolation area 4 is formed of a firstdielectric layer 4 a formed with SiO2. Furthermore, in the peripheral region B3 of the upper surface B2 of the transistor area B, abaselayer 12 is formed surrounding theemitter layer 15 formed on the upper surface B2. - In addition to the above mentioned conventional-type transistor structure, the transistor A, according to the invention, is one in which
contact groove 31 is formed within theisolation region 4 at around the contacting interface 4 b contacting the outside B1 of the transistor area B. Thebase electrode 9 is then embedded in thecontact groove 31, in a manner so as to contact the upper surface B2 and outside B1, in the vicinity of thecorner 33 formed by the upper surface B2 and outside B1. - Next, the fabrication process for the above-mentioned bipolar transistor is explained referring to FIGS.3 to 7.
- As is shown in FIG. 3, transistor area B for bipolar transistor A, in the form of an island which is rectangular when viewed from above, is formed. Here, the stacked layer of a highly-doped n-
type semiconductor layer 2 and a lightly-doped n-type semiconductor layer 3, is formed by using a epitaxial growth technique of lightly-doped n-type semiconductor layer 3 on the whole area of the substrate, after forming a highly-doped n-type semiconductor layer 2, by adding selectively, an n-type impurity on the predetermined area on the p-type semiconductor substrate 1. - The
isolation trench 4 is then formed at the outside of the transistor area B, up to the level of the substrate 1. Theisolation trench 4 is formed by selective etching of Si through the lightly-doped n-type semiconductor layer 3 and to reach the upper surface of the p-type semiconductor substrate 1, in order to form a groove to be embedded in a dielectric layer. For example, the depth of the groove is approximately 5 microns, the width is 1 micron. The dielectric layer used is, for example, BPSG which exhibits so called “re-flow” characteristics with increased temperature. - Thus, after the simultaneous growth of the dielectric layer using a low pressure CVD from both sides of the groove, the gap between the dielectric surface of the dielectric layers grown from each side of the groove is closed by the re-flow of BPSG. As the BPSG contains both highly-doped boron and phosphorus, they will act as a diffusion source when directly grown on the semiconductor. It should be noted that a device such as one concerned on the inner surface of the contact groove by a thermally-grown oxide layer or nitride layer, as the BPSG, will not contact the semiconductor layer directly.
- Furthermore, as shown in FIG. 4, after forming the
second dielectric layer 5 over the entire surface of the semiconductor substrate 1, an opening larger than the transistor area B is formed for thebase contact 7 using a photoresist as amask 6. Then, the upper part of the transistor area B is exposed by eliminating thesecond dielectric layer 5 within the opening. Here, thephotoresist mask 6 for use in the opening of the base contact is formed within the area where at least three edges of the rectangular semiconductor area, which has four edges surrounded by theisolation trench 4, are in the opening, by approximately 0.3 microns (denoted by reference numeral 7). The process for wet etching of theoxide layer 5 using a photoresist as amask 6 for the purpose of slowing the edge of the opening of the base contact for easiness and ensure the following process. Therefore, theoxide layer 5 is sufficiently thick enough to etch theoxide layer 5 to a depth of more than half the entire thickness. - The opening is then formed by etching off the remaining
oxide layer 5 using an anisotropic dry etching. At that time, the groove in the dielectric layer is formed with a depth of around 0.2 microns at the inside of the isolation trench, as well as exposing the edge of the semiconductor area A as shown in FIG. 4. In doing so, the upper surface B2 and the upper outside B1 of the transistor area B is exposed. Furthermore, thedielectric layer 4 a of the predetermined thickness, which is embedded into the gap formed between the opening and the edge of transistor area B, is etched off, forming acontact groove 31 at the area near to the interface of the transistor area B and thedielectric layer 4 a. - Next, as shown in FIG. 5, after etching the
photoresist mask 6, highly-doped p-type poly-Si base electrode 9 was deposited over the entire surface of the substrate for simultaneously embedding the groove. After etching thebase electrode 9 into a desired form, asilicon nitride layer 10 is deposited over the entire surface of the substrate. - Next, as shown in FIG. 6, after etching the
nitride layer 10 and thebase electrode 9 within an opening for the formation of an emitter, theintrinsic base area 12 is formed by diffusing a dopant, and after depositing the third dielectric layer 14 (not shown), a side-wall 14 a of a dielectric layer was formed using an anisotropic dry-etching method. - Here, the
graft base layer 13 with a first conductive type (p-type in this case), is connected to the first conductive type poly-Si 9 as a base electrode and the first conductive typeintrinsic base layer 12 by diffusing the first conductive-type impurity originated from the first conductive-type poly-Si 9 into the lightly-dopedsemiconductor layer 3 with a second conductive-type impurity (n-type in this case) by heat treatment after the growth of the first conductive-type poly-Si 9. - Lastly, as shown in FIG. 7, the emitter electrode was formed using a highly-doped impurity of the second conductive type poly-
Si 16, then the second conductive-type emitter layer 15 was formed by diffusing the impurity of the second conductive-type from the poly-Si 16 into theintrinsic base layer 12 by heat treatment. - In this semiconductor device, the parasitic capacitance relative to the substrate was reduced, compared to the conventional structure with an isolation trench groove buried with a poly-Si which exhibits a high dielectric constant. Since the dielectric layer with a lower dielectric constant was embedded in that groove, which improved the microwave performance of the transistor. This improvement in microwave performance is more pronounced as the transistor size is reduced. Compared to that of the first related art, for example, the bottom area of the transistor for this invention is reduced by about 40%, and the total length around the transistor for this invention is reduced by about 20%, and therefore, the parasitic capacitance between the collector and the substrate is reduced by about 25%.
- Furthermore, for the structure of this invention, as the base contact area was overlapped on the isolation trench and the contact groove was formed at the overlapping area within the groove of the isolation trench, the margin of the contact area of the base electrode is designed in the direction of the depth of the contact groove. Therefore, if an alignment shift in the direction parallel to the surface of the substrate occurs in the formation process of the base electrode, good contact will be ensured since the base electrode contacts both the upper surface and the outside of the semiconductor area. Thus, the necessary contact area will be satisfactory, since the contact at the side makes up for the loss of the contact area at the upper surface due to any shift of alignment.
- Thus, the shift of alignment in the formation process of the opening affects the width of the highly-doped p type poly-
Si 9 embedded in the contact groove of theisolation trench 4. However, as the depth of the contact groove is defined as the amount of over etching which was done in the process of the opening of the base contact area, so the contact area of the base electrode to the base layer is essentially constant, even if the shift of the alignment occurs. This constant contact area introduces a stable extracting of the base electrode from the stand-point of providing a constant contact resistance of the base electrode. - Next, the second embodiment of the present invention is explained with reference to FIGS.8 to 14.
- FIG. 8 is a plan view of the semiconductor device1 of this invention, and FIG. 9 is cross section of the device.
- The second embodiment differs from the first embodiment in that the semiconductor device has a side-wall of
dielectric 8 between the outside B1 of the transistor area B and thebase electrode 9. - The fabrication process of the above semiconductor device is explained with reference to FIGS.10 to 14.
- As in the fabrication process of the semiconductor device in the first embodiment, after opening for the
base contact 7, the remaining photoresist is removed, and as shown in FIG. 10, the semiconductor area within the base contact was covered with aspacer oxide 8 having a thickness of 20 nanometers to 100 nanometers by thermal oxidation of the entire surface of the substrate. - Then, as shown in FIG. 11, the poly-
Si 9 of a first conductive-type, which will be a base electrode, is deposited on the entire surface of the substrate, etched to form a desired shape, and then covered with adielectric nitride layer 10 over the entire surface of the substrate. - Next, after anisotropic etching of the
dielectric layer 10 and a highly-doped p-type poly-Si 9 at the area for forming the emitter electrode, the dielectric oxide of the side-wall 8 is etched by the isotropic etching method. This isotropic etching is performed until the edge surface in the isolation trench of the side of the transistor area is exposed by side-etching of theoxide layer 8 under the poly-Si of the first conductive-type. - Next, as shown in FIG. 12, a poly-
Si 11 is deposited over the entire surface of the substrate, the poly-Si 11 is embedded under the side-etchedspace 51, which is formed under the first conductive-type poly-Si 9 by side-etching of theoxide layer 8 under the poly-Si 9. After that, the poly-Si 11 remains only at the side-etchedspace 51 by using a etch-back method for poly-Si 11 using an isotropic etching method. - Next, as shown in FIG. 13, a first conductive
intrinsic base 12 is formed, and then side-wall 14 of dielectric material is formed, which isolates the first conductive poly-Si 9 so as to be a base electrode. The first conductive graft-base layer 13 is then formed by diffusing the first conductive impurity originating from the first conductive poly-Si 9 into the semiconductor layer, caused by a heat treatment after the connection of the first conductive poly-Si 9 (to be a base electrode) and semiconductor area via poly-Si 11. - Lastly, as shown in FIG. 14, the emitter electrode is formed using a highly-doped poly-Si (to be an emitter electrode) of the second conductive impurity. Then, the second
conductive emitter layer 15 is formed by diffusing the second conductive impurity originated from poly-Si 16 into the semiconductor area by heat treatment. In these semiconductor devices, as the side-wall dielectric layer is inserted between the outside and the base electrode, it is possible to prevent contact with the outer side and the base electrode. - FIG. 9 shows a the cross section in the second embodiment shown in FIG. 14 assuming the occurrence of a shift in alignment in the process of an emitter opening, shown in FIG. 12, on the left side. Here, the shift of alignment of an opening process for an emitter affects the variation of the distance between the location of the emitter opening and the
isolation trench 4. In the bipolar transistor according to the invention, the contacting width of the poly-Si 11 and the transistor area B is determined as a function of the amount of side-etching measured from the opening edge of the emitter area. Furthermore, saidspace oxide layer 8 is also formed at the side of thecontact groove 31 in theisolation trench 4. After the etching of thespacer oxide 8 of theisolation trench 4, the etching proceeded in the direction of the depth of the layer, along thecontact groove 31, by etching the highly-doped p-type poly-Si 9 embedded in thecontact groove 31. Therefore, the amount of side-etching of thespacer oxide layer 8 is not restricted by the existence of the shift of distance between the location of the emitter opening and theisolation trench 4. - Therefore, in the embodiment shown in FIG. 9, poly-
Si 11 is connected to both the side and the upper surface of the transistor area B on the left, and is connected to only the upper surface on the right of the transistor area B, the contact width which is proportional to the contact area of the base electrode to the base area, which is the sum of the upper surface and the side areas, will not be affected by the shift of alignment of the surface of the substrate, and a desired contact width of the base electrode both the on left and the right of the base electrode can be ensured. - In the bipolar transistor A formed in the above fabrication process, as the contact width of the base electrode can be determined by the self-alignment, no shift of the contact area of the base electrode will occur due to the shift of alignment in the opening process for the base contact. Furthermore, the contact width of the base electrode is determined in a self-aligning manner due to the amount of side-etching of the
oxide layer 8, and it is therefore possible to precisely control the contact width of the base electrode, since it is possible to contact both the semiconductor surface and the side of the transistor in a self-aligned manner like the structures explained in the first embodiment. - In the first embodiment, the contact area of the base electrode does not vary due to the shift in alignment in the process for the opening of the base contact; however, there occurs an shift (imbalance) of the connection area of the base electrode due to the shift of alignment, toward the direction of the shift of alignment. In a different manner, in the transistor according to the second embodiment, the shift (imbalance) of the contacting area of the base electrode due to the shift of alignment in the process of the opening for the emitter can be prevented by embedding a part of the
base electrode 19 into thecontact groove 31 formed in theisolation trench 4 and by forming aspacer oxide 8 to cover the side of the semiconductor area. - Next, the third and the fourth embodiments of the invention will be explained with reference to FIG. 15. In the first and the second embodiments explained above, isolation between the devices was accomplished by using an
isolation trench 4, whereas the isolation area in the third and the fourth embodiments, which is surrounding the transistor area A (that is, the so-called “field area”), is embedded in thedielectric layer 20 and leveled. - In this isolated structure, a lightly-doped n-
type semiconductor layer 3, a highly-doped n-type semiconductor layer 2, and the upper surface of the p-type semiconductor substrate 1 of the area other than the transistor area B are selectively etched, forming a transistor area in the form of an island, and then the dielectric material is embedded in the field area using adielectric layer 20 around the transistor area. The height of this so-called “island” is ordinarily about 3 to 5 microns, so the BPSG, etc., exhibiting the above reflow characteristics at high temperature is effective, in the view of the embedding of the isolation area with such a large step. The process is, after embedding the recessed part using low-pressure CVD, the sharp step formed by the dielectric materials deposited on the island structure will be smoothed, and the depth of the step will be decreased. After that, perfect planarization is performed using a decreased mechanical polishing method. In this process, it is necessary to cover the side of the transistor area using a thermally grown oxide or nitride layer in order to prevent the direct contact of the BPSG and the semiconductor surface. The above isolation structure can also be adopted if the interface between the dielectric layer and the transistor area is approximately perpendicular without a birds beak. Therefore, it is not necessary for the isolation area to use a trenched groove, which can be embedded by using a dielectric layer grown by a CVD method; it can instead be isolated by growing a dielectric layer on the area other than the transistor area, which is an island-form semiconductor area. - In this isolation structure, the same functions and the same effects as those in the first and second embodiments of the invention are expected as well. This is because parasitic capacitance can be further reduced due to the reduced dielectric constant around the area of the transistor area. Furthermore, as the thickness of the dielectric layer will be increased in the area under lines connecting between the transistors, the reduction of parasitic capacitance between lines and the substrate is possible. Thus, it is possible to realize a semiconductor device with improved MICROWAVE performance.
Claims (9)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8278321A JP2959491B2 (en) | 1996-10-21 | 1996-10-21 | Semiconductor device and manufacturing method thereof |
US09/045,794 US6329699B2 (en) | 1996-10-21 | 1998-03-23 | Bipolar transistor with trenched-groove isolation regions |
US09/987,043 US20020048892A1 (en) | 1998-03-23 | 2001-11-13 | Bipolar transistor with trenched-groove isolation regions |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8278321A JP2959491B2 (en) | 1996-10-21 | 1996-10-21 | Semiconductor device and manufacturing method thereof |
US09/045,794 US6329699B2 (en) | 1996-10-21 | 1998-03-23 | Bipolar transistor with trenched-groove isolation regions |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/987,043 Division US20020048892A1 (en) | 1998-03-23 | 2001-11-13 | Bipolar transistor with trenched-groove isolation regions |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010013635A1 true US20010013635A1 (en) | 2001-08-16 |
US6329699B2 US6329699B2 (en) | 2001-12-11 |
Family
ID=26552810
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/045,794 Expired - Fee Related US6329699B2 (en) | 1996-10-21 | 1998-03-23 | Bipolar transistor with trenched-groove isolation regions |
Country Status (2)
Country | Link |
---|---|
US (1) | US6329699B2 (en) |
JP (1) | JP2959491B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020192916A1 (en) * | 2001-06-15 | 2002-12-19 | Naem Abdalla Aly | Bipolar transistor with ultra small polysilicon emitter and method of fabricating the transistor |
US20060131694A1 (en) * | 2003-06-21 | 2006-06-22 | Thomas Bottner | Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method |
US7067898B1 (en) * | 2004-05-25 | 2006-06-27 | Hrl Laboratories, Llc | Semiconductor device having a self-aligned base contact and narrow emitter |
US7368764B1 (en) | 2005-04-18 | 2008-05-06 | Hrl Laboratories, Llc | Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor |
CN111969052A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | Bipolar junction transistor with multiple grooves |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6211562B1 (en) * | 1999-02-24 | 2001-04-03 | Micron Technology, Inc. | Homojunction semiconductor devices with low barrier tunnel oxide contacts |
JP2000252294A (en) | 1999-03-01 | 2000-09-14 | Nec Corp | Semiconductor device and its manufacture |
JP5641383B2 (en) * | 2008-11-07 | 2014-12-17 | セイコーNpc株式会社 | Vertical bipolar transistor and manufacturing method thereof |
US10593771B2 (en) * | 2017-12-11 | 2020-03-17 | International Business Machines Corporation | Vertical fin-type bipolar junction transistor with self-aligned base contact |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59215741A (en) | 1983-05-24 | 1984-12-05 | Mitsubishi Electric Corp | Manufacture of semiconductor integrated circuit device |
JPS6089969A (en) | 1983-10-24 | 1985-05-20 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
JPH0691098B2 (en) * | 1985-04-08 | 1994-11-14 | 株式会社日立製作所 | Semiconductor device |
JPS6372159A (en) | 1986-09-16 | 1988-04-01 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS63258067A (en) | 1987-04-15 | 1988-10-25 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JPS63266877A (en) | 1987-04-24 | 1988-11-02 | Hitachi Ltd | Semiconductor integrated circuit |
JPS63302559A (en) | 1987-06-02 | 1988-12-09 | Hitachi Ltd | Bipolar transistor device |
JPH01232738A (en) | 1988-03-14 | 1989-09-18 | Hitachi Ltd | Semiconductor device and manufacture thereof |
JPH01251658A (en) | 1988-03-31 | 1989-10-06 | Fujitsu Ltd | Manufacture of semiconductor device |
JP2666384B2 (en) | 1988-06-30 | 1997-10-22 | ソニー株式会社 | Method for manufacturing semiconductor device |
US5128740A (en) | 1988-11-17 | 1992-07-07 | Hitachi, Ltd. | Semiconductor integrated circuit device with isolation grooves and protruding portions |
JPH02137233A (en) | 1988-11-17 | 1990-05-25 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
JPH03155638A (en) | 1989-11-14 | 1991-07-03 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JPH05235012A (en) | 1992-02-24 | 1993-09-10 | Nec Corp | Semiconductor integrated circuit device |
JPH06318602A (en) | 1993-05-10 | 1994-11-15 | Toshiba Corp | Semiconductor device and its manufacture |
-
1996
- 1996-10-21 JP JP8278321A patent/JP2959491B2/en not_active Expired - Lifetime
-
1998
- 1998-03-23 US US09/045,794 patent/US6329699B2/en not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020192916A1 (en) * | 2001-06-15 | 2002-12-19 | Naem Abdalla Aly | Bipolar transistor with ultra small polysilicon emitter and method of fabricating the transistor |
US6853017B2 (en) * | 2001-06-15 | 2005-02-08 | National Semiconductor Corporation | Bipolar transistor structure with ultra small polysilicon emitter |
US20060131694A1 (en) * | 2003-06-21 | 2006-06-22 | Thomas Bottner | Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method |
US7592648B2 (en) * | 2003-06-21 | 2009-09-22 | Infineon Technologies Ag | Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method |
US7067898B1 (en) * | 2004-05-25 | 2006-06-27 | Hrl Laboratories, Llc | Semiconductor device having a self-aligned base contact and narrow emitter |
US7368764B1 (en) | 2005-04-18 | 2008-05-06 | Hrl Laboratories, Llc | Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor |
CN111969052A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | Bipolar junction transistor with multiple grooves |
Also Published As
Publication number | Publication date |
---|---|
JP2959491B2 (en) | 1999-10-06 |
US6329699B2 (en) | 2001-12-11 |
JPH10125694A (en) | 1998-05-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6121102A (en) | Method of electrical connection through an isolation trench to form trench-isolated bipolar devices | |
KR100270965B1 (en) | High-speed bipolar transistor and method for fabricating the same | |
US10475916B2 (en) | Semiconductor device and manufacturing method thereof | |
US6218725B1 (en) | Bipolar transistors with isolation trenches to reduce collector resistance | |
US4980748A (en) | Semiconductor device made with a trenching process | |
US6329699B2 (en) | Bipolar transistor with trenched-groove isolation regions | |
US20020060339A1 (en) | Semiconductor device having field effect transistor with buried gate electrode surely overlapped with source region and process for fabrication thereof | |
US5486481A (en) | Method for forming a lateral bipolar transistor | |
EP0281235B1 (en) | Bipolar transistor fabrication utilizing cmos techniques | |
US5591651A (en) | Method of making a bipolar stripe transistor structure | |
US5574306A (en) | Lateral bipolar transistor and FET | |
JP2628988B2 (en) | Semiconductor device and manufacturing method thereof | |
US5763931A (en) | Semiconductor device with SOI structure and fabrication method thereof | |
US20020048892A1 (en) | Bipolar transistor with trenched-groove isolation regions | |
US5744855A (en) | Single-poly-type bipolar transistor | |
EP0724298B1 (en) | Semiconductor device with bipolar transistor and fabrication method thereof | |
JP2809025B2 (en) | Bipolar transistor | |
US6818492B2 (en) | Semiconductor device and manufacturing method thereof | |
KR100761561B1 (en) | Method of manufacturing a bipolar transistor semiconductor device | |
US6064106A (en) | Bipolar transistor having isolation regions | |
JP3207561B2 (en) | Semiconductor integrated circuit and method of manufacturing the same | |
JP3373995B2 (en) | High frequency semiconductor device and manufacturing method thereof | |
JP3152290B2 (en) | Method for manufacturing semiconductor device including capacitive element | |
KR19980063791A (en) | Well isolated bipolar transistor | |
JPH05218319A (en) | Manufacture of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KITAHATA, HIDEKI;REEL/FRAME:009059/0234 Effective date: 19980316 |
|
AS | Assignment |
Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013774/0295 Effective date: 20021101 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Expired due to failure to pay maintenance fee |
Effective date: 20051211 |