JPS63266877A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the irregularity in a base contact width and to achieve a high integration density by a method wherein a microscopic opening with a prescribed width is made at the upper part of a single-crystal protruding region, a base electrode is pulled out from this opening and a microscopic groove whose cross section is U-shaped is formed in the circumference of an active region. CONSTITUTION:Firstly, a method to form a base contact part is explained. The surface of a P-type silicon substrate 1 is oxidized and an oxide film 17 is formed; furthermore, a silicon nitride film 18 and an oxide film 19 are deposited. Then, after the silicon nitride film 18 has been side-etched, polycrystalline Si 23 is deposited; lastly, an emitter region and a base region are formed; a structure which makes use of the polycrystalline Si film 23 as a base extraction electrode is completed. In the next step, a method to form a microscopic U-shaped groove is explained. As follows: the surface of a silicon substrate 1 is oxidized; an oxide film 25 is formed; silicon nitride 26 is deposited. After that, the microscopic U-shaped groove is formed in the semiconductor substrate by using a dry etching technique. Then, the oxide film 25 is formed inside said groove. By this setup, it is made possible to control a contact width of a base extraction part microscopically and with good accuracy; in addition, an integration density is more than doubled thanks to the microscopic U-shaped groove.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a self-aligned, high-performance, highly integrated bipolar semiconductor integrated circuit with excellent α-ray resistance.

[Conventional technology]

Conventional bipolar semiconductor devices are known, for example, from Japanese Patent Application Laid-open No. 56
-001556, and as shown in FIG.
The base electrode was taken out by connecting polycrystalline Si. Further, isolation between elements has been achieved using a PN junction between the substrate and the buried layer.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology has the disadvantage that the width of the connecting portion between the single crystal convex region and the polycrystalline Si film varies, and the transistor characteristics are unstable. Further, in order to suppress the resistance of the buried layer below a certain value, it has been impossible to further reduce the distance between elements using the PN junction isolation method.

SUMMARY OF THE INVENTION An object of the present invention is to provide a self-aligned, high-performance, highly integrated α-ray-resistant bipolar device structure that can eliminate the drawbacks of the prior art and reduce variations in base contact width.

[Means for solving problems]

The above object can be achieved by providing a fine opening with a constant width in the upper part of the single crystal convex region and taking out the base electrode from the opening using polycrystalline Si. In addition, by forming a fine groove with a U-shaped cross section around the active area,
High integration of elements can be achieved.

[Effect]

The width of the connection between the single crystal convex region and the polycrystalline Si is determined by wet etching of the oxide film provided on the side wall of the convex region, and therefore precise control is difficult. Therefore, by forming the connection portion using dry etching technology, uniformity and controllability can be improved.

Furthermore, by forming a fine groove with a U-shaped cross section through the buried layer around the active region, the separation distance between elements can be reduced and the degree of integration can be improved. Furthermore, since there is no need to consider the lateral inward expansion of the buried layer, it is possible to reduce the resistance of the buried layer.

〔Example〕

Hereinafter, the present invention will be explained separately into a method for forming a base contact portion (FIGS. 3 to 8, FIGS. 9 to 13) and a method for forming a fine U-groove (FIGS. 14 to 16). do. FIG. 1 is a cross-sectional view of the completed bipolar transistor.
Further, FIG. 2 is a cross-sectional view of a conventional transistor structure.

First, a method for forming the base contact portion will be described.

The surface of p-type silicon substrate 1 is oxidized to form oxide film 17, and silicon nitride 18 and oxide film 19 are further deposited using vapor phase growth (CVD).

Thereafter, a desired region of the silicon substrate 1 is exposed using a conventional selective dry etching technique (FIG. 3). Next, the silicon substrate 1 is etched using anisotropic etching technology.
A thermal oxide film 20 is provided on this surface (FIG. 4).

Subsequently, silicon nitride 21 is deposited using CVD technology, and silicon nitride 21 is left only on the side walls using anisotropic etching technology. Thereafter, the surface of the silicon 1 is isotropically etched using the silicon nitride 21 and the underlying 5iOz film 20 as a mask by a well-known wet etching technique (FIG. 5).

Next, the exposed portion of the Si substrate 1 is oxidized to form an oxide film 22, and the silicon nitride film 21 on the sidewalls is removed (FIG. 6). Thereafter, the oxide film 20 in the base opening is removed, and the silicon nitride film 18 is side-etched to form an eaves structure, and then polycrystalline 8i 23 is deposited and using a well-known planarization technique, as shown in FIG. As shown in polycrystalline Si2
Embed 3. Finally, form the emitter and base regions.

A base electrode structure using the polycrystalline Si film 8 as a base lead electrode as shown in FIG. 8 can be realized.

Next, another example of a method for forming a base contact portion will be described using FIGS. 9 to 13. In this example, following FIG. 3, the exposed silicon substrate is etched by a wet etching technique, and the surface is oxidized to form an oxide film 20 (FIG. 9). Next, silicon nitride 21 is deposited, side spacers r,1= are left, and the silicon substrate is isotropically etched by wet etching (FIG. 10). Thereafter, an oxide film 22 is provided, and the sidewall silicon nitride 21 is removed (FIG. 11). Further, the oxide film 20 in the base opening is removed, the silicon nitride 18 is side-etched, and then polycrystalline Si 23 is flattened (FIG. 12). Thereafter, by forming an emitter and a base region, a base electrode structure as shown in FIG. 13 can be realized.

Next, a method for forming the fine U-groove will be explained. First, the surface of the silicon substrate 1 is oxidized to form an oxide film 25, and then CVD
Deposit silicon nitride 26 using a technique. Thereafter, a fine U-groove is formed in the silicon substrate using conventional photo-etching and dry etching techniques (FIG. 14). Thereafter, thermal oxidation is performed to form an oxide film 25 inside the trench. Furthermore, polycrystalline 5i27 is deposited, as shown in FIG.
Fill the inside of the fine U-groove flatly. Of course, other insulators such as oxide films can be used as this material. Next, the surface of the polycrystalline Si is oxidized to form an oxide film 28, and after removing the silicon nitride 26, an element isolation groove structure as shown in FIG. 16 can be realized. The bipolar transistor structure shown in FIG. 1 can be realized by combining the method for forming the base contact portion and the method for forming the fine UN described above.

〔Effect of the invention〕

In the bipolar transistor according to the present invention, the contact width between polycrystalline silicon and single crystal silicon in the base extraction part can be controlled finely and precisely, and furthermore, in order to perform isolation between elements using a fine U-groove, conventional methods can be used. Compared to transistors, the variation in current amplification factor and rise voltage (VBE) has been reduced to about 1/2, and the degree of integration has been increased by more than twice.

Therefore, the operating speed of the circuit is improved, and for example, the delay speed of the ECL circuit is approximately 4. Q ps / goo 1-
The following values were obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of a conventional bipolar transistor. In addition, Fig. 3 to Fig. 8, Fig. 9 to Fig. 13, Fig. 14 to
FIG. 16 is a diagram illustrating a method for manufacturing the main parts of the present invention. DESCRIPTION OF SYMBOLS 1...P-type silicon substrate, 2...N-type buried layer, 3...N-type epitaxial layer, 4,17,20°22.24,25...Thermal oxide film (silicon) ,5゜6
．． 28...Thermal oxide film (poly-loss crystal silicon), 7°1B,
21. ．． 26...Silicon nitride, 8...P multiplied crystalline silicon, 9...P ten type diffusion layer, 10...P type diffusion layer, 11.12...n ten type diffusion layer, 13. ...n-type multi-Ju+ silicon, 14...emitter electrode, 15...
・Base electrode, 16...Collector electrode, 19...C
VD oxide film, 23.27... polycrystalline silicon.

Claims (1)

[Claims] 1. A convex portion provided on a single crystal substrate having a first conductivity type, a low resistance region having a second conductivity type provided within a side surface of the convex portion, and An insulating film that is in contact with a side surface and extends onto the main surface of the semiconductor substrate is in contact with the low resistance region at an upper part of the side surface of the convex portion in an area smaller than the area of the low resistance region, and the surface of the insulating film Stretching the second
A semiconductor integrated circuit comprising at least a conductive polycrystalline silicon film. 2. Claim 1 further comprising a groove provided in the semiconductor substrate, an insulating film formed to cover the surface of the groove, and an element isolation region having polycrystalline silicon filling the groove. The semiconductor integrated circuit described.