CN111968967A - 一种封装结构及封装方法 - Google Patents

一种封装结构及封装方法 Download PDF

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CN111968967A
CN111968967A CN202010818981.6A CN202010818981A CN111968967A CN 111968967 A CN111968967 A CN 111968967A CN 202010818981 A CN202010818981 A CN 202010818981A CN 111968967 A CN111968967 A CN 111968967A
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chip
lead frame
transistor
packaging
transistor chip
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赵承贤
李鑫
颜志进
刘浩
周新龙
盘伶子
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Gree Xinyuan Electronics Co Ltd
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Gree Xinyuan Electronics Co Ltd
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/73265—Layer and wire connectors

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Abstract

本发明提供了封装结构及封装方法，涉及芯片封装技术领域，解决了现有IPM智能功率模块采用二维封装结构导致产品体积较大的技术问题。该封装结构包括引线框架、晶体管芯片和驱动芯片，所述晶体管芯片安装于所述引线框架，所述驱动芯片在垂直于所述引线框架的Z方向上设置于所述晶体管芯片的上方形成三维堆叠结构。驱动芯片在垂直于引线框架的Z方向上设置于晶体管芯片的上方而形成三维堆叠结构，与传统的晶体管芯片与驱动芯片均设置于引线框架的结构相比，取消了引线框架上驱动芯片的固晶部位，大大节省了空间，实现了产品体积的小型化；而且驱动芯片在晶体管芯片上进行堆叠固晶，缩小了驱动芯片与晶体管芯片的距离，过温保护更加精确可靠。

Description

一种封装结构及封装方法
技术领域
本发明涉及芯片封装技术领域，尤其是涉及一种封装结构及封装方法。
背景技术
现有传统型IPM智能功率模块封装结构采用二维封装结构，如图1所示。驱动芯片MIC与IGBT芯片分别在引线框架上特定的PAD位上进行固晶，两个芯片固晶位置在沿引线框架宽度的Y方向上均占用了产品1/3的空间，导致产品体积相对较大，并且此封装结构限制了产品体积的小型化。
另外，此封装结构驱动芯片MIC与IGBT芯片之间的空间距离较大，IGBT芯片在应用端使用时会产生热量，而驱动芯片MIC与IGBT芯片的空间距离较大，就会导致驱动芯片MIC检测到的温度与IGBT芯片实际的温度有段差，导致驱动芯片MIC未及时进行保护而致使IGBT芯片过温击穿损坏。
发明内容
本发明的目的在于提供一种封装结构及封装方法，以解决现有技术中存在的IPM智能功率模块采用二维封装结构导致产品体积较大的技术问题。本发明提供的诸多技术方案中的优选技术方案所能产生的诸多技术效果详见下文阐述。
为实现上述目的，本发明提供了以下技术方案：
本发明提供的一种封装结构，其应用于IPM智能功率模块的封装，包括引线框架、晶体管芯片和驱动芯片，所述晶体管芯片安装于所述引线框架，所述驱动芯片在垂直于所述引线框架的Z方向上设置于所述晶体管芯片的上方形成三维堆叠结构。
可选地，所述驱动芯片固接于所述晶体管芯片的焊点处。
可选地，所述驱动芯片通过绝缘胶粘接于所述晶体管芯片的焊点处。
可选地，所述晶体管芯片焊接于所述引线框架。
可选地，所述三维堆叠结构包括依次设置的所述引线框架、焊锡层或银浆层、所述晶体管芯片、铝线焊点层、绝缘胶层和所述驱动芯片。
可选地，所述IPM智能功率模块的FRD芯片安装于所述引线框架。
可选地，所述引线框架具有下沉结构，所述晶体管芯片与所述FRD芯片均安装于所述下沉结构。
可选地，所述引线框架具有下沉结构，所述晶体管芯片安装于所述下沉结构。
可选地，所述晶体管芯片为IGBT芯片或MOSFET芯片。
本发明提供的一种封装方法，采用其封装形成以上任一所述的封装结构，所述封装方法包括以下步骤：
A、将晶体管芯片固定于引线框架；
B、将驱动芯片堆叠固定于所述晶体管芯片的上方；
C、完成所述晶体管芯片的铝线焊接。
本发明提供的一种封装结构及封装方法，封装结构包括引线框架、晶体管芯片和驱动芯片，晶体管芯片安装于引线框架，驱动芯片在垂直于引线框架的Z方向上设置于晶体管芯片的上方而形成三维堆叠结构，与传统的晶体管芯片与驱动芯片均设置于引线框架的结构相比，大大节省了空间，实现了产品体积的小型化；而且驱动芯片在晶体管芯片上进行堆叠固晶，缩小了驱动芯片与晶体管芯片的距离，过温保护更加精确可靠。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术IPM智能功率模块封装结构的俯视结构示意图；
图2是本发明具体实施方式提供的一种IPM智能功率模块的封装结构的俯视结构示意图；
图3是三维堆叠结构的正视结构示意图；
图4是引线框架的俯视结构示意图；
图5是引线框架的侧视结构示意图；
图6是IPM智能功率模块MCP封装结构的内部结构示意图；
图7是本发明具体实施方式提供的一种IPM智能功率模块MCP封装的工艺流程图；
图8是铝线焊接用楔嘴结构的正视结构示意图。
图中1、金线或铜线；2、驱动芯片；3、绝缘胶；4、铝线焊点；5、IGBT芯片；6、焊锡或银浆；7、引线框架；71、逆变部基岛；72、驱动部引脚；73、下沉结构；8、FRD芯片；9、铝线；10、自举二极管芯片BDi；11、楔嘴梯形结构。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将对本发明的技术方案进行详细的描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所得到的所有其它实施方式，都属于本发明所保护的范围。
如图2和图3所示，本发明提供了一种封装结构，其应用于IPM智能功率模块的封装，包括引线框架、晶体管芯片和驱动芯片，晶体管芯片安装于引线框架，驱动芯片在垂直于引线框架的Z方向上设置于晶体管芯片的上方形成三维堆叠结构。
驱动芯片在垂直于引线框架的Z方向上设置于晶体管芯片的上方而形成三维堆叠结构，与传统的晶体管芯片与驱动芯片均设置于引线框架的结构相比，取消了引线框架上驱动芯片的固晶部位，大大节省了空间，实现了产品体积的小型化；而且驱动芯片在晶体管芯片上进行堆叠固晶，缩小了驱动芯片与晶体管芯片的距离，过温保护更加精确可靠。
在本实施方式中，晶体管芯片为IGBT芯片或MOSFET芯片。引线框架的俯视结构参见图4。
作为可选地实施方式，驱动芯片固接于晶体管芯片的焊点处，由于目前IPM模块晶体管芯片与FRD表面均有电极，为铝线焊线位置，在铝线焊点处粘驱动芯片，保证产品的电气回路。
作为可选地实施方式，驱动芯片通过绝缘胶粘接于晶体管芯片的焊点处。
采用绝缘胶粘接，工艺简单，且提高了绝缘性能。
作为可选地实施方式，晶体管芯片通过焊锡或银浆焊接于引线框架。
作为可选地实施方式，如图3所示，三维堆叠结构包括依次设置的引线框架、焊锡层或银浆层、晶体管芯片、铝线焊点层、绝缘胶层和驱动芯片。
作为可选地实施方式，IPM智能功率模块的FRD芯片安装于引线框架。FRD芯片也可堆叠安装，不过需要改变FRD的电极，现有FRD正面是正极，背面是负极，需要改为正面是负极，背面是正极；而且FRD是大功率芯片，在应用过程中产生较多热量，如果FRD芯片也同样采用堆叠安装，Z方向上堆叠的芯片过多，会影响晶体管芯片的使用。
作为可选地实施方式，如图5和图6所示，引线框架具有下沉结构，晶体管芯片与FRD芯片均安装于下沉结构，有效利用空间。
作为可选地实施方式，引线框架具有下沉结构，晶体管芯片安装于下沉结构。
如图2与图6所示，新型IPM智能功率模块封装结构将多芯片封装技术(MCP)应用到IPM智能功率模块的封装中，即采用三维堆叠封装结构，实现驱动芯片MIC在IGBT芯片上进行堆叠固晶，形成一种新型IPM智能功率模块MCP封装结构，并采用新的封装工艺予以实现，提高产品过温保护精确度与实现产品体积的小型化。
产品电气结构设计：该结构由6个IGBT或者MOSFET、6个续流二极管FRD、3个自举二极管BDi、3个驱动芯片MIC组成，采用点焊锡丝或者刷锡膏或者点银浆将芯片焊接在引线框架PAD部位，并采用不导电胶在IGBT芯片上进行驱动芯片MIC进行堆叠固晶，引线框架作为部分电气导线、结构支撑以及散热载体的作用，并使用铝线焊接与铜线焊接的方式实现芯片电极之间以及与引线框架之间的电气连接。
框架设计：引线框架采用逆变部PAD位为下沉结构，并取消掉驱动芯片MIC的固晶PAD位，缩小了引线框架宽度方向(Y方向)的尺寸。
本发明提供了一种封装方法，采用其封装形成以上任一的封装结构，封装方法包括以下步骤：
A、将晶体管芯片固定于引线框架；
B、将驱动芯片堆叠固定于晶体管芯片的上方；
C、完成晶体管芯片的铝线焊接。
更具体地，封装方法工艺流程如图7所示，先采用点银浆工艺进行BDi固晶，再进行点焊锡丝工艺进行FRD及IGBT固晶，然后进行三维堆叠MCP封装技术的实现过程，采用梯形楔嘴代替V型楔嘴进行铝线焊接(梯形楔嘴的结构参见图8)，在IGBT芯片上形成平面型的铝线焊点，接着采用点绝缘胶工艺将驱动芯片MIC在IGBT芯片上方进行固晶，然后进行固化，最后进行后段的铜线焊接与封装测试。
图中DB是指将芯片通过点焊锡丝或者刷锡膏或者点银浆的方式固定在引线框架上；DM是指将芯片通过点不导电胶的方式固定在另外一个芯片上方(堆叠方式)；IGBT是指IGBT或者MOSFET；FRD是指续流二极管；BDi是指自举二极管；MIC是指驱动芯片；Al WB是指铝线焊接；固化是指对DB或者DM后的产品进行加热固化；Au WB是指金线或者铜线焊接；内观检查是指对产品进行内部结构检查；散热片贴附是指采用热压合方式将高导热绝缘铜基树脂散热片与引线框架进行贴合；树脂模封是指使用环氧树脂采用注塑的方式将产品进行包封；后固化是指对塑封后的产品进行完全固化；切筋浸锡是指将产品引脚进行分离，并将焊锡用热浸焊工艺附着在产品引脚上；测试是指对产品进行电性能测试；成型印字是指将产品引脚进行成型，并对产品型号及批次号等信息进行标识；外观检查是指对测试后的良品进行外观检查。
采用三维堆叠封装结构解决了二维封装结构封装严重受限，无法满足芯片尺寸日益增长的封装需求问题；采用三维堆叠封装结构取消了引线框架上驱动芯片的固晶PAD位置，缩小了产品的体积；采用三维堆叠封装结构，实现驱动芯片MIC在IGBT芯片上进行堆叠固晶，缩小了驱动芯片MIC与IGBT芯片的距离，过温保护更加精确可靠；在空间占比较高的IGBT芯片铝线焊点，在其表面二次粘片，即采用芯片三维堆叠的方式使用绝缘胶将驱动芯片MIC粘附在IGBT芯片上方，并采用新的封装工艺予以实现，提高产品过温保护精确度与实现产品体积的小型化。
在发明的描述中，需要说明的是，除非另有说明，″多个″的含义是两个或两个以上；术语″上″、″下″、″左″、″右″、″内″、″外″、″前端″、″后端″、″头部″、″尾部″等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语″第一″、″第二″、″第三″等仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本发明的描述中，还需要说明的是，除非另有明确的规定和限定，术语″安装″、″相连″、″连接″应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可视具体情况理解上述术语在本发明中的具体含义。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (10)

1.一种封装结构，其应用于IPM智能功率模块的封装，其特征在于，包括引线框架、晶体管芯片和驱动芯片，所述晶体管芯片安装于所述引线框架，所述驱动芯片在垂直于所述引线框架的Z方向上设置于所述晶体管芯片的上方形成三维堆叠结构。
2.根据权利要求1所述的封装结构，其特征在于，所述驱动芯片固接于所述晶体管芯片的焊点处。
3.根据权利要求2所述的封装结构，其特征在于，所述驱动芯片通过绝缘胶粘接于所述晶体管芯片的焊点处。
4.根据权利要求1所述的封装结构，其特征在于，所述晶体管芯片焊接于所述引线框架。
5.根据权利要求1所述的封装结构，其特征在于，所述三维堆叠结构包括依次设置的所述引线框架、焊锡层或银浆层、所述晶体管芯片、铝线焊点层、绝缘胶层和所述驱动芯片。
6.根据权利要求1所述的封装结构，其特征在于，所述IPM智能功率模块的FRD芯片安装于所述引线框架。
7.根据权利要求6所述的封装结构，其特征在于，所述引线框架具有下沉结构，所述晶体管芯片与所述FRD芯片均安装于所述下沉结构。
8.根据权利要求1所述的封装结构，其特征在于，所述引线框架具有下沉结构，所述晶体管芯片安装于所述下沉结构。
9.根据权利要求1所述的封装结构，其特征在于，所述晶体管芯片为IGBT芯片或MOSFET芯片。
10.一种封装方法，其特征在于，采用其封装形成权利要求1-9任一所述的封装结构，所述封装方法包括以下步骤：
A、将晶体管芯片固定于引线框架；
B、将驱动芯片堆叠固定于所述晶体管芯片的上方；
C、完成所述晶体管芯片的铝线焊接。
CN202010818981.6A 2020-08-14 2020-08-14 一种封装结构及封装方法 Pending CN111968967A (zh)

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