CN111863626A - 支撑框架结构及其制作方法 - Google Patents
支撑框架结构及其制作方法 Download PDFInfo
- Publication number
- CN111863626A CN111863626A CN202010599238.6A CN202010599238A CN111863626A CN 111863626 A CN111863626 A CN 111863626A CN 202010599238 A CN202010599238 A CN 202010599238A CN 111863626 A CN111863626 A CN 111863626A
- Authority
- CN
- China
- Prior art keywords
- metal
- opening
- dielectric layer
- frame structure
- metal plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 201
- 239000002184 metal Substances 0.000 claims abstract description 201
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000010030 laminating Methods 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 238000000227 grinding Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 80
- 229920005989 resin Polymers 0.000 claims description 21
- 239000011347 resin Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000009713 electroplating Methods 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000004698 Polyethylene Substances 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- -1 polyethylene Polymers 0.000 claims description 7
- 229920000573 polyethylene Polymers 0.000 claims description 7
- 229920001169 thermoplastic Polymers 0.000 claims description 7
- 229920001187 thermosetting polymer Polymers 0.000 claims description 7
- 239000004416 thermosoftening plastic Substances 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 5
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 19
- 230000017525 heat dissipation Effects 0.000 abstract description 8
- 239000010408 film Substances 0.000 description 29
- 238000011161 development Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003814 drug Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007494 plate polishing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001502 supplementing effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0158—Polyalkene or polyolefin, e.g. polyethylene [PE], polypropylene [PP]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Geometry (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
本申请公开了一种支撑框架结构制作方法和支撑框架结构,该方法包括步骤:提供包括支撑区和开口区的金属板;在支撑区的上下表面分别光刻形成上介质开孔和下介质开孔,上介质开孔和下介质开孔之间连接有金属间隔;在金属板上表面形成上金属柱,并层压上介质层,上介质层覆盖上金属柱和上介质开孔;刻蚀金属间隔,在金属板下表面形成下金属柱,并层压下介质层,下介质层覆盖下金属柱和下介质开孔;对上表面和下表面对应的上介质层、下介质层以及上金属柱、下金属柱进行磨平并贴附感光干膜,光刻感光干膜在开口区形成至少一个图案窗口;对图案窗口处进行刻蚀形成埋芯口框。本申请制作方法简单,能够提高芯片散热效率,改善封装翘曲。
Description
技术领域
本申请涉及半导体封装技术领域,尤其涉及一种支撑框架结构及其制作方法。
技术背景
随着电子产业的蓬勃发展,电子产品体积日趋轻薄,集成度日益提高,利用支撑框架实现嵌埋式芯片的封装方法得以大力发展。支撑框架结构的总体要求是可靠性和适当的电气性能、薄度、刚度、平坦度、良好的散热性和有竞争力的单价。
目前,市面上用于嵌埋封装的框架多采用介质材料作为支撑框架主体,并在介质材料中制作大批量的金属通孔柱阵列,通过调整金属通孔柱高度实现框架与埋入芯片的高度匹配,并且支撑框架封装后主要通过介质以及芯片背面开窗实现散热,而介质材料的散热率较低,无法适用于大功率器件的嵌埋封装需求。
申请内容
本申请旨在至少在一定程度上解决相关技术中的技术问题之一。为此,本申请提出一种支撑框架结构制作方法和支撑框架结构,以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。所述技术方案如下:
第一方面,本申请实施例提供了一种支撑框架结构制作方法,包括以下步骤:
提供金属板,所述金属板包括支撑区和开口区;
在所述支撑区的上表面和下表面分别光刻形成至少一个上介质开孔和至少一个下介质开孔,所述上介质开孔和所述下介质开孔之间连接有金属间隔;
在所述金属板上表面电镀形成至少一个上金属柱,并层压上介质层,所述上介质层覆盖所述上金属柱和所述上介质开孔;
刻蚀所述金属间隔,在所述金属板下表面电镀形成至少一个下金属柱,并层压下介质层,所述下介质层覆盖所述下金属柱和所述下介质开孔,所述上金属柱与所述下金属柱相对于所述金属板对称设置;
对上表面和下表面对应的所述上介质层、所述下介质层以及所述上金属柱、所述下金属柱进行磨平并贴附感光干膜,光刻所述感光干膜在所述开口区形成至少一个图案窗口,对所述图案窗口处进行刻蚀形成埋芯口框。
根据本申请第一方面实施例的支撑框架结构制作方法,至少具有以下有益效果:第一方面,该框架采用金属作为支撑基材,金属具有良好的导热性,可以将芯片工作时产生的热量通过框架中的金属层进行热传导,降低芯片温度,无须在芯片背面进行开窗散热或者利用高成本的高散热介质材料;第二方面,金属具有一定的刚性和良好的延展性以金属板作为核心,加以生成金属柱和覆盖有机介质层,有利于改善封装翘曲度;第三方面,可以通过增加核心金属板的厚度增加框架厚度,从而减少电镀金属柱的高度,降低电镀工艺不稳定风险,同时降低了减薄和平坦化过程中金属柱未磨出的风险,保证制作框架都在设计规格要求之内;第四方面,该支撑框架制作方法简单且成本低廉。
可选地,在本申请的一个实施例中,所述上介质开孔与所述下介质开孔在垂直方向上对齐设置。
可选地,在本申请的一个实施例中,所述上金属柱和所述下金属柱分别包括支撑金属柱和开口金属柱,所述开口金属柱被所述图案窗口覆盖。
可选地,在本申请的一个实施例中,所述上介质层和所述下介质层包括半固化片或薄膜型树脂热固性有机树脂或者聚乙烯热塑性有机树脂。
可选地,在本申请的一个实施例中还包括,在所述上介质层表面依次形成导电层和保护层。
可选地,在本申请的一个实施例中,所述导电层为钛或铜金属。
可选地,在本申请的一个实施例中,所述保护层为感光光膜或者液态光阻材料。
第二方面,本申请实施例提供一种支撑框架结构,用于嵌埋封装,包括:
金属板,所述金属板包括支撑区和开口区,在所述支撑区的上表面和下表面分别设置有至少一个上介质开孔和至少一个下介质开孔,所述上介质开孔和所述下介质开孔连通;
至少一组金属柱,所述金属柱包括上金属柱和下金属柱,所述上金属柱和所述下金属柱分别垂直连接于所述金属板的上表面和下表面;
介质层,包括上介质层和下介质层,所述上介质层和所述下介质层分别对应设置在所述金属板的上表面以及上介质开孔和下表面以及下介质开孔;
至少一个埋芯口框,设置于所述开口区,贯穿所述介质层和所述金属板,与所述上介质开孔和所述下介质开孔通过介质层间隔。
根据本申请第二方面实施例的支撑框架结构,至少具有以下有益效果:第一方面,该框架采用金属作为支撑基材,金属具有良好的导热性,可以将芯片工作时产生的热量通过框架中的金属层进行热传导,降低芯片温度,无须在芯片背面进行开窗散热或者利用高成本的高散热介质材料;第二方面,金属具有一定的刚性和良好的延展性以金属板作为核心,加以生成金属柱和覆盖有机介质层,有利于改善封装翘曲度;第三方面可以通过增加核心金属板的厚度增加框架厚度,从而减少电镀金属柱的高度,降低电镀工艺不稳定风险,同时降低了减薄和平坦化过程中金属柱未磨出的风险,保证制作框架都在设计规格要求之内;第四方面,该支撑框架制作方法简单且成本低廉。
可选地,在本申请的一个实施例中,介质包括半固化片或薄膜型树脂热固性有机树脂或者聚乙烯热塑性有机树脂。
可选地,在本申请的一个实施例中,所述金属板或所述金属柱包括导电金属或金属合金。
本申请的其它特征和优点将在随后的说明书中阐述,并且,部分地从说明书中变得显而易见,或者通过实施本申请而了解。本申请的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案的进一步理解,并且构成说明书的一部分,与本申请的实施例一起用于解释本申请的技术方案,并不构成对本申请技术方案的限制。
图1是本申请一个实施例提供的支撑框架结构制作方法的步骤流程图;
图2至图10是本申请另一个实施例提供的支撑框架结构制作方法中间状态的截面图;
图11是本申请另一个实施例提供的支撑框架结构的截面图。
金属板100、支撑区110、开口区120、上介质开孔130、上介质开孔窗口130a、下介质开孔140、下介质开孔窗口140a、下介质开孔窗口140b、感光干膜170、金属间隔150、上金属柱600a、下金属柱600b、上介质层210、下介质层220、图案窗口300、埋芯口框400、导电层500、保护层700
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本申请进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本申请,并不用于限定本申请,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本申请所能产生的功效及所能达成的目的下,均应仍落在本申请所揭示的技术内容得能涵盖的范围内。
本部分将详细描述本申请的具体实施例,本申请之较佳实施例在附图中示出,附图的作用在于用图形补充说明书文字部分的描述,使人能够直观地、形象地理解本申请的每个技术特征和整体技术方案,但其不能理解为对本申请保护范围的限制。
在申请的描述中,若干的含义是一个或者多个,多个的含义是两个及两个以上,大于、小于、超过等理解为不包括本数,以上、以下、以内等理解为包括本数。如果有描述到第一、第二只是用于区分技术特征为目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量或者隐含指明所指示的技术特征的先后关系。
参照图1,本申请的一个实施例提供的一种支撑框架结构制作方法包括以下步骤:
S100,如图2所示,提供金属板100,具体地,准备一块预制金属板100,金属板100在垂直方向上包括两个表面,其中一面为上表面,相对一面为下表面,在水平方向上包括支撑区110和开口区120,支撑区110和开口区120根据不同的功能进行划分,金属板100的厚度和尺寸根据不同的需求具体定制,金属板100材料可以为铜、铝、铜铝合金等金属或者金属合金中的一种,优选的,本申请中金属板100材料为铜金属。
S200,在支撑区110的上表面和下表面分别光刻形成至少一个上介质开孔130和至少一个下介质开孔140,上介质开孔130和下介质开孔140之间连接有金属间隔150,具体地,如图3所示,分别在金属板100的上表面和下表面贴附PCB光刻胶170,并对PCB光刻胶170通过曝光、显影的方式形成上介质开孔窗口130a和下介质开孔窗口140b。
参照图4,利用蚀刻工艺,通过控制蚀刻深度对金属板100进行蚀刻,在金属板100上表面和下表面形成特定深度的上介质开孔130和下介质开孔140,以及介于上介质开孔130和下介质开孔140之间的金属间隔150,再将PCB光刻胶170去除。需要说明的是,在刻蚀金属板100上表面和下表面介质开孔时需要控制刻蚀深度,预留金属间隔150,防止金属板100断开,方便后续步骤执行。
可选的,PCB光刻胶170包括感光干膜或者液态光阻,PCB光刻胶170亦称为光阻或光阻剂,通过紫外光、深紫外光、电子束、离子束、X射线等光照或辐射后变化成耐蚀刻薄膜材料,优选的,本申请中PCB光刻胶170为感光干膜,对上介质开孔130和下上介质开孔130以外的感光干膜170区域进行光照曝光,在经过显影露出上介质开孔窗口130a和下介质开孔窗口140b。
S300,在金属板100上表面电镀形成至少一个上金属柱600a,并层压上介质层210,上介质层210覆盖上金属柱600a和上介质开孔130,具体地,如图5所示,在金属板100上表面和下表面贴附感光干膜170,首先对上表面感光干膜170通过光刻显影的方式形成金属柱通孔,对下表面感光干膜170直接整板曝光,进行上金属柱通孔电镀,形成导通上金属柱600a,需要说明的是,感光干膜170经过曝光后具有耐腐蚀性,因此可以保护金属板100下表面不被蚀刻,如图6所示,将感光干膜170退除,在上表面层压有机介质材料形成上介质层210,有机介质材料填充金属板100上表面和上介质开孔130,在金属板100下表面进一步贴附感光干膜170,使用曝光显影的方式在金属板100下表面对应下介质开孔140位置再一次形成下介质开孔窗口140b。说要说明的是,有机介质材料包括半固化片、薄膜型树脂等热固性有机树脂或者聚乙烯等热塑性有机树脂,优选的,本申请中有机介质材料使用半固化片。
S400,刻蚀金属间隔150,在金属板100下表面电镀形成至少一个下金属柱600b,并层压下介质层220,下介质层220覆盖下金属柱600b和下介质开孔140,上金属柱600a与下金属柱600b相对于金属板100对称设置,具体地,如图7所示,蚀刻掉上介质开孔130和下介质开孔140之间的金属间隔150,使上介质开孔130和下介质开孔140相通,再将金属板100下表面感光干膜170使用退膜药水去除,露出金属板100下表面,使用磨板工艺对上表面进行磨平,将被上介质层210层压在内的上金属柱600a磨出,露出上金属柱600a表面,使上金属柱600a表面和上介质层210表面位于同一平面,如图8所示,在上介质层210表面和下金属板100下表面压合感光干膜170,对上表面感光干膜170一面整板曝光,形成保护层700,用于保护上层线路,再对下表面感光干膜170通过曝光显影的方式形成下金属柱600b通孔,再通过电镀的方式形成下金属柱600b柱,如图9所示,将下表面感光干膜170用退膜药水去除,露出下金属柱600b表面和金属板100下表面,在金属板100下表面压合有机介质材料形成下介质层220,有机介质材料填充金属板100下表面和下介质开孔140并将金属柱覆盖其中,再使用磨板工艺对下表面进行磨平,将被下介质层220层压在内的下金属柱600b磨出,露出下金属柱600b表面,使下金属柱600b表面和下介质层220表面位于同一平面。
需要说明的是,上介质开孔130与下介质开孔140在垂直方向上对齐设置,最终进行连通,目的是为了使金属板100断开形成独立的支撑金属,上金属柱600a与下金属柱600b中心在垂直方向上处于同一垂直线上,并且与金属板100垂直连接,分别用于从上下两个表面对金属板100进行支撑,通过上介质开孔130与下介质开孔140的连通最终使支撑金属、上金属柱600a(支撑金属柱)和下金属柱600b(支撑金属柱)连通形成独立的金属支撑架,形成单独的线路连接通路,方便与框架外部的电子元器件或其他框架进行电气连通。
在步骤S400中还包括步骤S410,在上介质层210表面依次形成导电层500和保护层700,具体地,上介质层210经过减薄和平坦化处理后,露出所有上金属柱600a的上表面,并且上金属柱600a上表面与上介质层210表面位于同一平面,进一步在磨平后的同一平面表面溅镀一层金属种子层用于形成导电层500,如图8所示,S420再在导电层500上表面贴附感光干膜170形成保护层700,形成导电层500的目的在于通过化学电镀的方法在化学反应池中提供电极从而电镀形成下金属柱600b,优选的,金属种子层由钛、铜等金属材料组成。
S500,对上表面和下表面对应的上介质层210、下介质层220以及上金属柱600a、下金属柱600b进行磨平并贴附感光干膜170,光刻感光干膜170在开口区120形成至少一个图案窗口300,对图案窗口300处进行刻蚀形成埋芯口框400,具体地,如图10所示,对步骤S400形成的框架上下表面进一步磨平处理,并贴附感光干膜170,通过曝光显影的方式形成至少一个图案窗口300,在金属板100开口区120中露出上下表面对应的金属柱(开口金属柱)表面和介质层表面,如图11所示,利用蚀刻的方法将露出金属柱蚀刻,介于开口金属柱中间的介质层由于没有金属柱的支撑在显影过程中会同时去掉,形成埋芯口框400,再将感光干膜170用退膜药水去除,形成支撑框架。
需要说明的是,埋芯口框400用于嵌埋电子元件,电子元件包括但不限于器件、芯片,可以是有源器件也可以是无源器件,按用途分类可以是的大功率器件,还可以是射频或逻辑芯片,埋芯口框400的尺寸和数量可根据实际需求进行设计。
基于上述支撑框架结构制作方法,提出本申请的支撑框架结构的各个实施例。
参照图11,本申请的另一个实施例还提供了一种支撑框架结构,用于嵌埋封装,包括金属板100,金属板100包括支撑区110和开口区120,在支撑区110的上表面和下表面分别设置有至少一个上介质开孔130和至少一个下介质开孔140,上介质开孔130和下介质开孔140连通;至少一组金属柱,金属柱包括上金属柱600a和下金属柱600b,上金属柱600a和下金属柱600b分别垂直连接于金属板100的上表面和下表面;介质层,包括上介质层210和下介质层220,上介质层210和下介质层220分别对应设置在金属板100的上表面以及上介质开孔130和下表面以及下介质开孔140;至少一个埋芯口框400,设置于开口区,贯穿介质层和金属板,与上介质开孔130和下介质开孔140通过介质层间隔。
在一实施例中,一组金属柱包括上金属柱600a和下金属柱600b,上金属柱600a与下金属柱600b的中心在垂直方向上处于同一垂直线上,并且与支撑金属垂直连接组成金属支撑架,形成单独的线路连接通路,方便与框架外部的电子元器件或其他框架进行电气连通;多个金属支撑架通过介质层隔离,并且在金属支撑架还设置有埋芯口框400,埋芯口框400用于嵌埋电子元件,电子元件包括但不限于器件、芯片,可以是有源器件也可以是无源器件,按用途分类可以是的大功率器件,还可以是射频或逻辑芯片,埋芯口框400的尺寸和数量可根据实际需求进行设计。需要说明的是,埋芯口框400的侧面可以包括金属边缘也可以不包括金属边缘,包括金属边缘的埋芯口框400可以进一步提高电子元件的散热效率,在进行多芯片或者多器件电子元件封装时,金属边缘除了具有散热功能外还具有一定的屏蔽效果,降低电子元件之间的电磁干扰。
本申请的一个实施例提供的一种支撑框架结构,用于嵌埋封装,介质层包括半固化片或薄膜型树脂热固性有机树脂或者聚乙烯热塑性有机树脂。
在一实施例中,介质层为有机材料,包括半固化片、薄膜型树脂等热固性有机树脂或者聚乙烯等热塑性有机树脂,优选的,本申请中有机介质材料使用半固化片介质层。
本申请的一个实施例提供的一种支撑框架结构,用于嵌埋封装,金属板100或金属柱包括导电金属或金属合金。
在一实施例中,支撑金属材料可以为铜、铝、铜铝合金等金属或者金属合金中的一种,优选的,本申请中金属板100材料为铜金属。
以上是对本申请的较佳实施进行了具体说明,但本申请并不局限于上述实施方式,熟悉本领域的技术人员在不违背本申请精神的前提下还可作出种种的等同变形或替换,这些等同的变形或替换均包含在本申请权利要求所限定的范围内。
Claims (10)
1.一种支撑框架结构制作方法,其特征在于,包括以下步骤:
提供金属板,所述金属板包括支撑区和开口区;
在所述支撑区的上表面和下表面分别光刻形成至少一个上介质开孔和至少一个下介质开孔,所述上介质开孔和所述下介质开孔之间连接有金属间隔;
在所述金属板上表面电镀形成至少一个上金属柱,并层压上介质层,所述上介质层覆盖所述上金属柱和所述上介质开孔;
刻蚀所述金属间隔,在所述金属板下表面电镀形成至少一个下金属柱,并层压下介质层,所述下介质层覆盖所述下金属柱和所述下介质开孔,所述上金属柱与所述下金属柱相对于所述金属板对称设置;
对上表面和下表面对应的所述上介质层、下介质层以及所述上金属柱、下金属柱进行磨平并贴附感光干膜,光刻所述感光干膜在所述开口区形成至少一个图案窗口,对所述图案窗口处进行刻蚀形成埋芯口框。
2.根据权利要求1所述的支撑框架结构制作方法,其特征在于,所述上介质开孔与所述下介质开孔在垂直方向上对齐设置。
3.根据权利要求1所述的支撑框架结构制作方法,其特征在于:所述上金属柱和所述下金属柱分别包括支撑金属柱和开口金属柱,所述开口金属柱被所述图案窗口覆盖。
4.根据权利要求1所述的支撑框架结构制作方法,其特征在于:所述上介质层和下介质层包括半固化片或薄膜型树脂热固性有机树脂或者聚乙烯热塑性有机树脂。
5.根据权利要求1所述的支撑框架结构制作方法,其特征在于:还包括,在所述上介质层表面依次形成导电层和保护层。
6.根据权利要求5所述的支撑框架结构制作方法,其特征在于:所述导电层为钛或铜金属。
7.根据权利要求5所述的支撑框架结构制作方法,其特征在于:所述保护层为感光光膜或者液态光阻材料。
8.一种支撑框架结构,用于嵌埋封装,其特征在于,包括:
金属板,所述金属板包括支撑区和开口区,在所述支撑区的上表面和下表面分别设置有至少一个上介质开孔和至少一个下介质开孔,所述上介质开孔和所述下介质开孔连通;
至少一组金属柱,所述金属柱包括上金属柱和下金属柱,所述上金属柱和所述下金属柱分别垂直连接于所述金属板的上表面和下表面;
介质层,包括上介质层和下介质层,所述上介质层和所述下介质层分别对应设置在所述金属板的上表面以及上介质开孔和下表面以及下介质开孔;
至少一个埋芯口框,设置于所述开口区,贯穿所述介质层和所述金属板,与所述上介质开孔和所述下介质开孔通过介质层间隔。
9.根据权利要求8所述的支撑框架结构,用于嵌埋封装,其特征在于,介质层包括半固化片或薄膜型树脂热固性有机树脂或者聚乙烯热塑性有机树脂。
10.根据权利要求8所述的金属支撑框架结构,用于嵌埋封装,其特征在于,所述金属板或所述金属柱包括导电金属或金属合金。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010599238.6A CN111863626B (zh) | 2020-06-28 | 2020-06-28 | 支撑框架结构及其制作方法 |
JP2020151945A JP7105284B2 (ja) | 2020-06-28 | 2020-09-10 | 支持フレーム構造およびその製造方法 |
US16/948,518 US11569177B2 (en) | 2020-06-28 | 2020-09-22 | Support frame structure and manufacturing method thereof |
TW109133191A TWI749784B (zh) | 2020-06-28 | 2020-09-25 | 支撐框架結構及其製作方法 |
KR1020210073622A KR102566362B1 (ko) | 2020-06-28 | 2021-06-07 | 지지 프레임 구조 및 그 제작 방법 |
US18/099,107 US20230154859A1 (en) | 2020-06-28 | 2023-01-19 | Support frame structure and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010599238.6A CN111863626B (zh) | 2020-06-28 | 2020-06-28 | 支撑框架结构及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111863626A true CN111863626A (zh) | 2020-10-30 |
CN111863626B CN111863626B (zh) | 2021-12-07 |
Family
ID=72988634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010599238.6A Active CN111863626B (zh) | 2020-06-28 | 2020-06-28 | 支撑框架结构及其制作方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US11569177B2 (zh) |
JP (1) | JP7105284B2 (zh) |
KR (1) | KR102566362B1 (zh) |
CN (1) | CN111863626B (zh) |
TW (1) | TWI749784B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI836979B (zh) * | 2023-05-05 | 2024-03-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060267163A1 (en) * | 2004-07-21 | 2006-11-30 | Linear Technology Corporation | Flashless lead frame with horizontal singulation |
CN101364581A (zh) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | 嵌埋有芯片的承载板结构及其制作方法 |
CN201936875U (zh) * | 2010-09-04 | 2011-08-17 | 江苏长电科技股份有限公司 | 双面图形芯片正装模组封装结构 |
CN103596366A (zh) * | 2012-08-16 | 2014-02-19 | 安捷利电子科技(苏州)有限公司 | 一种高密度线路板的制造工艺 |
CN105307382A (zh) * | 2014-07-28 | 2016-02-03 | 三星电机株式会社 | 印刷电路板及其制造方法 |
CN106997870A (zh) * | 2016-01-26 | 2017-08-01 | 珠海越亚封装基板技术股份有限公司 | 新型嵌入式封装 |
CN108347838A (zh) * | 2018-02-07 | 2018-07-31 | 维沃移动通信有限公司 | 一种电路板的制作方法、电路板及移动终端 |
US20180240783A1 (en) * | 2017-02-23 | 2018-08-23 | International Business Machines Corporation | Microstructure modulation for metal wafer-wafer bonding |
CN111146091A (zh) * | 2019-12-26 | 2020-05-12 | 中芯集成电路(宁波)有限公司 | 一种散热封装结构的制造方法及散热结构 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3888943B2 (ja) | 2002-04-12 | 2007-03-07 | イビデン株式会社 | 多層プリント配線板及び多層プリント配線板の製造方法 |
US6787896B1 (en) * | 2003-05-15 | 2004-09-07 | Skyworks Solutions, Inc. | Semiconductor die package with increased thermal conduction |
US8049114B2 (en) * | 2009-03-22 | 2011-11-01 | Unimicron Technology Corp. | Package substrate with a cavity, semiconductor package and fabrication method thereof |
JP5617846B2 (ja) * | 2009-11-12 | 2014-11-05 | 日本電気株式会社 | 機能素子内蔵基板、機能素子内蔵基板の製造方法、及び、配線基板 |
US8320134B2 (en) * | 2010-02-05 | 2012-11-27 | Advanced Semiconductor Engineering, Inc. | Embedded component substrate and manufacturing methods thereof |
US8884443B2 (en) * | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
KR20140048564A (ko) * | 2012-10-16 | 2014-04-24 | 삼성전기주식회사 | 코어기판, 그의 제조방법 및 메탈 비아용 구조체 |
US9876169B2 (en) * | 2015-06-12 | 2018-01-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM devices and methods |
CN106356351B (zh) * | 2015-07-15 | 2019-02-01 | 凤凰先驱股份有限公司 | 基板结构及其制作方法 |
KR102554017B1 (ko) * | 2018-10-02 | 2023-07-11 | 삼성전자주식회사 | 반도체 패키지 |
-
2020
- 2020-06-28 CN CN202010599238.6A patent/CN111863626B/zh active Active
- 2020-09-10 JP JP2020151945A patent/JP7105284B2/ja active Active
- 2020-09-22 US US16/948,518 patent/US11569177B2/en active Active
- 2020-09-25 TW TW109133191A patent/TWI749784B/zh active
-
2021
- 2021-06-07 KR KR1020210073622A patent/KR102566362B1/ko active IP Right Grant
-
2023
- 2023-01-19 US US18/099,107 patent/US20230154859A1/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060267163A1 (en) * | 2004-07-21 | 2006-11-30 | Linear Technology Corporation | Flashless lead frame with horizontal singulation |
CN101364581A (zh) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | 嵌埋有芯片的承载板结构及其制作方法 |
CN201936875U (zh) * | 2010-09-04 | 2011-08-17 | 江苏长电科技股份有限公司 | 双面图形芯片正装模组封装结构 |
CN103596366A (zh) * | 2012-08-16 | 2014-02-19 | 安捷利电子科技(苏州)有限公司 | 一种高密度线路板的制造工艺 |
CN105307382A (zh) * | 2014-07-28 | 2016-02-03 | 三星电机株式会社 | 印刷电路板及其制造方法 |
CN106997870A (zh) * | 2016-01-26 | 2017-08-01 | 珠海越亚封装基板技术股份有限公司 | 新型嵌入式封装 |
US20180240783A1 (en) * | 2017-02-23 | 2018-08-23 | International Business Machines Corporation | Microstructure modulation for metal wafer-wafer bonding |
CN108347838A (zh) * | 2018-02-07 | 2018-07-31 | 维沃移动通信有限公司 | 一种电路板的制作方法、电路板及移动终端 |
CN111146091A (zh) * | 2019-12-26 | 2020-05-12 | 中芯集成电路(宁波)有限公司 | 一种散热封装结构的制造方法及散热结构 |
Also Published As
Publication number | Publication date |
---|---|
US20230154859A1 (en) | 2023-05-18 |
KR102566362B1 (ko) | 2023-08-10 |
US11569177B2 (en) | 2023-01-31 |
US20210407921A1 (en) | 2021-12-30 |
JP2022008780A (ja) | 2022-01-14 |
KR20220001011A (ko) | 2022-01-04 |
TW202202018A (zh) | 2022-01-01 |
JP7105284B2 (ja) | 2022-07-22 |
TWI749784B (zh) | 2021-12-11 |
CN111863626B (zh) | 2021-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8338921B2 (en) | Wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield and a method for fabricating the same | |
TWI723936B (zh) | 散熱兼電磁屏蔽嵌埋封裝結構、製作方法和基板 | |
CN109494202B (zh) | 一种半导体芯片封装方法及封装结构 | |
CN107195618A (zh) | 重布线路结构 | |
TW201041103A (en) | Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package | |
TW201703212A (zh) | 晶片封裝 | |
CN112310003A (zh) | 具有天线和emi隔离屏蔽件的半导体封装和相关联方法 | |
CN111863626B (zh) | 支撑框架结构及其制作方法 | |
CN111146091B (zh) | 一种散热封装结构的制造方法及散热结构 | |
KR102623492B1 (ko) | 입체 패키징을 구현하는 기판 제작 방법 | |
CN215342506U (zh) | 晶圆级asic 3d集成基板及封装器件 | |
US12074115B2 (en) | Heat dissipation-electromagnetic shielding embedded packaging structure, manufacturing method thereof, and substrate | |
CN103456715B (zh) | 中介基材及其制作方法 | |
JP2006186038A (ja) | 抵抗体チップ及びその実装方法 | |
CN215342505U (zh) | 晶圆级asic 3d集成基板及封装器件 | |
CN115116997A (zh) | 一种液体循环冷却封装基板及其制作方法 | |
CN115189116B (zh) | 水平垂直双辐射方向的天线封装结构及制备方法 | |
US12009312B2 (en) | Semiconductor device package | |
CN113540028B (zh) | 具有硅穿孔结构的半导体组件及其制作方法 | |
US20220319870A1 (en) | Packaging structure radiating electromagnetic waves in horizontal direction and method making the same | |
CN214588742U (zh) | 水平辐射方向的天线封装结构 | |
CN210668359U (zh) | 一种无基板集成天线封装结构 | |
CN214336904U (zh) | 水平垂直双辐射方向的天线封装结构 | |
US20240030121A1 (en) | Package structure and manufacturing method thereof | |
WO2022012523A1 (zh) | 半导体封装方法及半导体封装结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |