CN111785624A - 形成浅沟渠结构的方法 - Google Patents
形成浅沟渠结构的方法 Download PDFInfo
- Publication number
- CN111785624A CN111785624A CN201910397224.3A CN201910397224A CN111785624A CN 111785624 A CN111785624 A CN 111785624A CN 201910397224 A CN201910397224 A CN 201910397224A CN 111785624 A CN111785624 A CN 111785624A
- Authority
- CN
- China
- Prior art keywords
- shallow trench
- trench structure
- substrate
- forming
- aspect ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 12
- 239000001301 oxygen Substances 0.000 claims abstract description 12
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000009832 plasma treatment Methods 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims abstract description 9
- 238000001020 plasma etching Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
本发明提供一种形成浅沟渠结构的方法,该方法包含:提供一基板;形成一图案化光阻层于所述基板上;以所述图案化光阻层为罩幕,进行蚀刻,形成浅沟渠结构于所述基板;及进行电浆处理,将四氟化碳及氧气的混合气体产生的电浆施加在具有所述浅沟渠结构的所述基板。所述方法还包含交替重复上述蚀刻与电浆处理的步骤,直到在基板形成具有预定深宽比的所述浅沟渠结构。上述方法可以使得堵塞于浅沟渠结构中的高分子残留物被移除,从而获得具有预定深宽比的浅沟渠结构。
Description
技术领域
本发明是有关于一种半导体工艺中形成浅沟渠的方法,特别是涉及一种形成具有预定深宽比(aspect ratio)的浅沟渠结构的方法。
背景技术
在半导体组件制造的工艺中,为了使基板上的主动区域组件例如晶体管和晶体管之间的操作不会互相干扰,需要将每个集成电路上的晶体管与其他晶体管互相隔离,避免短路的情形发生,浅沟渠隔离(shallow trench isolation,STI)工艺因而产生。
在半导体基板上进行图案化蚀刻工艺以形成浅沟渠结构的过程中,图案化光阻层的碳会转化成高分子并与蚀刻气体及蚀刻工艺副产物结合而形成高分子残留物,这些高分子残留物会堆积在浅沟渠的壁面,甚至造成对半导体基板实施的蚀刻工艺停止。在过去曾经使用含氧电浆移除这些高分子残留物,但并无法从浅沟渠的壁面完全移除这些高分子残留物,以致仍然会发生蚀刻停止的情况。随着半导体组件尺寸缩小和组件密度的增加,沟渠的深宽比(aspect ratio)也随之增加,这些高分子残留物更容易堵塞于浅沟渠中,使得蚀刻停止(etching stop)的问题更加严重,导致无法蚀刻浅沟渠至一定深度。
发明内容
本发明于是提供一种经过改良的浅沟渠工艺,以克服上述浅沟渠工艺所面临的问题。
根据本发明提供的一实施方式,本发明的一种浅沟渠工艺包含:提供一基板;形成一图案化光阻层于所述基板上;以所述图案化光阻层为罩幕,进行蚀刻,形成浅沟渠结构于所述基板;及进行电浆处理,其中,所述电浆处理是施加四氟化碳及氧气的混合气体产生的电浆于具有所述浅沟渠结构的所述基板。
在一实施例中,所述浅沟渠工艺还包含交替重复上述形成所述浅沟渠结构的步骤及电浆处理的步骤,直到在所述基板形成具有预定深宽比(aspect ratio)的所述浅沟渠结构。
在一实施例中,所述浅沟渠结构的预定深宽比在6:1到20:1之间。
在一实施例中,所述四氟化碳及氧气的混合气体中四氟化碳与氧气的体积比例为1:3-1:30。
在一实施例中,形成所述浅沟渠结构的步骤包含进行非等向性蚀刻工艺。根据本发明的一实施方式,所述非等向性蚀刻工艺包含反应性离子蚀刻工艺。
在本发明提供的上述实施例中,对具有浅沟渠结构的基板施加四氟化碳及氧气的混合气体产生的电浆的电浆处理,可以使得堵塞于浅沟渠结构中的高分子残留物被移除,而可获得具有预定深宽比的浅沟渠结构。
对于本领域一般技术人员而言这些与其他的观点与实施例在参考后续详细描述与附图之后将变得容易明白。
附图说明
图式所示的结构大小比例并不限制本发明的实际实施。
图1为一种根据本发明的一实施例形成浅沟渠结构的方法步骤流程图;及
图2-图7显示图1形成浅沟渠结构的方法中各步骤形成的半导体结构的剖面图。
符号说明
102、104、106、108、110、112 步骤
20 基板
22a 光阻层
22b 图案化光阻层
241、242 浅沟渠结构
261、262 高分子残留物
具体实施方式
本发明提供一种应用于半导体工艺中的浅沟渠工艺,以形成具有预定深宽比(aspect ratio)的浅沟渠结构。
现在将参考本发明的附图详细描述实施例。在所述附图中,相同和/或对应组件是以相同参考符号表示。
在此将提供各种实施例;然而,要了解到所提供的实施例只用于作为可体现各种形式的例证。此外,连接各种实施例所给予的每一范例都预期作为例示,而非用于限制。进一步的,所述图式并不一定符合尺寸比例,一些特征是被放大以显示特定组件的细节(且所述附图中所示的任何尺寸、材料与类似细节都将仅为例示而非限制)。因此,在此提供的特定结构与功能细节并不被理解为限制,而只是用于教导本领域一般技术人员实际操作所提供的实施例的基础。
图1显示本发明一种形成浅沟渠结构的方法的步骤流程图,而图2至图7显示图1形成浅沟渠结构的方法的各步骤形成的半导体结构的剖面图。以下将配合图1至图7详细说明本发明形成浅沟渠结构的方法。首先,在步骤102,提供一基板20,例如硅基板或其他适合的半导体基板,在基板20上形成一光阻层22a,如图2所示。需注意的是,基板20上可以已经具备前段工艺的基本组件,本发明为了简化图形结构,位于基板20上例如金属氧化物半导体场效晶体管等基础组件,暂时忽略不予表示。
接着,在步骤104,利用显影蚀刻技术形成一图案化光阻层22b于基板20上,如图3所示。
接着,在步骤106,以图案化光阻层22b为罩幕,进行干蚀刻,例如非等向性蚀刻,形成浅沟渠结构241于基板20。在本发明的一实施方式中,非等向性蚀刻可以反应性离子蚀刻(RIE)工艺来执行。在步骤106的浅沟渠蚀刻过程中,图案化光阻层22b的碳会转化成高分子并与蚀刻气体及蚀刻的副产物结合形成高分子残留物261,而这些高分子残留物261会堆积在浅沟渠结构241的壁面,如图4所示。
接着,在步骤108,对具有浅沟渠结构241的基板20进行电浆处理。所述电浆处理是施加四氟化碳(CF4)及氧气(O2)的混合气体产生的电浆于具有浅沟渠结构241的基板20,以移除堆积在浅沟渠壁面的高分子残留物261,如图5所示。在本发明的一实施方式中,本发明使用的四氟化碳及氧气的混合气体中四氟化碳与氧气的体积比例为1:3-1:30。在步骤108,对基板20实施电浆处理后,如果基板20上的浅沟渠结构241已经具有预定的深宽比(步骤110),接下来,进行步骤112,从基板20移除图案化光阻层22b。如果基板20上的浅沟渠结构241未达到预定的深宽比,则回到步骤106,继续进行浅沟渠蚀刻工艺。
请参见图6,在继续进行步骤106过程中,基板20上形成浅沟渠结构242,并且图案化光阻层22b的碳会转化成高分子并与蚀刻气体及蚀刻的副产物结合形成高分子残留物262,而这些高分子残留物262会堆积在浅沟渠结构242的壁面。因此,接下来对基板20进行步骤108的电浆处理,以移除堆积在浅沟渠壁面的高分子残留物262,如图7所示。如此一来,本发明通过交替重复步骤106及步骤108,可获得具有预定深宽比的浅沟渠结构(步骤110)。当获得具有预定深宽比的浅沟渠结构时,即进行步骤112,从基板20移除图案化光阻层22b。在本发明的实施例中,本发明的浅沟渠结构具有6:1的深宽比,亦可具有10:1的深宽比,亦可以具有20:1的深宽比。
在一实施例中,浅沟渠结构可以是垂直侧壁或非垂直侧壁的浅沟渠结构,然而,上述的实施例并不用以限本制发明。
虽然已经以一或多个实施例描述本发明浅沟渠的制造方法,但要了解到本发明提供内容并不限制于所提供的实施例。本发明涵盖在权利要求的精神与观点中所包含的各种修改与类似配置,应给予最广泛的诠释,以包含所有的修改与类似结构。本发明提供内容也包含权利要求中的所有任何实施例。
Claims (8)
1.一种形成浅沟渠结构的方法,该方法包含:
提供一基板;
形成一图案化光阻层于所述基板上;
以所述图案化光阻层为罩幕,进行蚀刻,形成浅沟渠结构于所述基板;及
进行电浆处理,其中,所述电浆处理是施加四氟化碳及氧气的混合气体产生的电浆于具有所述浅沟渠结构的所述基板。
2.如权利要求1所述的形成浅沟渠结构的方法,其中,所述方法还包含交替重复上述形成所述浅沟渠结构的步骤及电浆处理的步骤,直到在所述基板形成具有预定深宽比的所述浅沟渠结构。
3.如权利要求2所述的形成浅沟渠结构的方法,其中,所述浅沟渠结构的预定深宽比为6:1-20:1。
4.如权利要求1所述的形成浅沟渠结构的方法,其中,所述四氟化碳及氧气的混合气体中四氟化碳与氧气的体积比例为1:3-1:30。
5.如权利要求1所述的形成浅沟渠结构的方法,其中,上述形成所述浅沟渠结构的步骤包含进行非等向性蚀刻工艺。
6.如权利要求5所述的形成浅沟渠结构的方法,其中,所述非等向性蚀刻工艺包含反应性离子蚀刻工艺。
7.如权利要求1所述的形成浅沟渠结构的方法,其中,所述基板包含硅底材。
8.如权利要求2所述的形成浅沟渠结构的方法,其中,所述方法还包含移除所述图案化光阻层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/375,264 | 2019-04-04 | ||
US16/375,264 US20200321240A1 (en) | 2019-04-04 | 2019-04-04 | Method for forming a shallow trench structure |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111785624A true CN111785624A (zh) | 2020-10-16 |
Family
ID=72661954
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910397224.3A Pending CN111785624A (zh) | 2019-04-04 | 2019-05-14 | 形成浅沟渠结构的方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20200321240A1 (zh) |
CN (1) | CN111785624A (zh) |
TW (1) | TW202038329A (zh) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1717787A (zh) * | 2000-09-15 | 2006-01-04 | 应用材料有限公司 | 硅蚀刻和腔室清洁工艺的集成 |
CN1801474A (zh) * | 2005-01-07 | 2006-07-12 | 联华电子股份有限公司 | 制作双镶嵌结构以及清除其残余聚合物的方法 |
US20070202700A1 (en) * | 2006-02-27 | 2007-08-30 | Applied Materials, Inc. | Etch methods to form anisotropic features for high aspect ratio applications |
CN102810472A (zh) * | 2011-05-31 | 2012-12-05 | 南亚科技股份有限公司 | 降低凹槽侧壁上的条痕的方法 |
US20130213931A1 (en) * | 2010-09-27 | 2013-08-22 | Fujifilm Corporation | Method for forming a pattern, method for producing a substrate, and method for producing a mold |
-
2019
- 2019-04-04 US US16/375,264 patent/US20200321240A1/en not_active Abandoned
- 2019-04-09 TW TW108112278A patent/TW202038329A/zh unknown
- 2019-05-14 CN CN201910397224.3A patent/CN111785624A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1717787A (zh) * | 2000-09-15 | 2006-01-04 | 应用材料有限公司 | 硅蚀刻和腔室清洁工艺的集成 |
CN1801474A (zh) * | 2005-01-07 | 2006-07-12 | 联华电子股份有限公司 | 制作双镶嵌结构以及清除其残余聚合物的方法 |
US20070202700A1 (en) * | 2006-02-27 | 2007-08-30 | Applied Materials, Inc. | Etch methods to form anisotropic features for high aspect ratio applications |
US20130213931A1 (en) * | 2010-09-27 | 2013-08-22 | Fujifilm Corporation | Method for forming a pattern, method for producing a substrate, and method for producing a mold |
CN102810472A (zh) * | 2011-05-31 | 2012-12-05 | 南亚科技股份有限公司 | 降低凹槽侧壁上的条痕的方法 |
US20120305525A1 (en) * | 2011-05-31 | 2012-12-06 | Hsiu-Chun Lee | Method of reducing striation on a sidewall of a recess |
Non-Patent Citations (1)
Title |
---|
F. D. EGITTO,ET AL: "Plasma etching of organic materials. I. Polyimide in O2–CF4", 《JOURNAL OF VACUUM SCIENCE & TECHNOLOGY》 * |
Also Published As
Publication number | Publication date |
---|---|
US20200321240A1 (en) | 2020-10-08 |
TW202038329A (zh) | 2020-10-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20160064240A1 (en) | Method for Integrated Circuit Patterning | |
US8901004B2 (en) | Plasma etch method to reduce micro-loading | |
CN110211919B (zh) | 浅沟槽隔离结构的形成方法及半导体器件的形成方法 | |
JP3950446B2 (ja) | 異方性エッチング方法 | |
KR100796509B1 (ko) | 반도체 소자의 제조방법 | |
CN111785624A (zh) | 形成浅沟渠结构的方法 | |
KR101042253B1 (ko) | 반도체 소자의 소자분리막 형성 방법 | |
CN111312587B (zh) | 刻蚀方法、半导体器件及其制造方法 | |
US6924217B2 (en) | Method of forming trench in semiconductor device | |
KR100772709B1 (ko) | 반도체 소자의 소자분리막 제조방법 | |
KR100417461B1 (ko) | 반도체 소자의 제조 방법 | |
KR19990055775A (ko) | 트랜치를 이용한 반도체 소자의 소자분리 방법 | |
KR100831671B1 (ko) | 반도체 소자의 소자 분리막 형성 방법 | |
KR100419026B1 (ko) | 반도체소자의소자분리방법 | |
US7309641B2 (en) | Method for rounding bottom corners of trench and shallow trench isolation process | |
KR100688777B1 (ko) | 반도체 소자의 제조 방법 | |
KR100243012B1 (ko) | 반도체 소자의 트랜치구조 형성방법 | |
JP2006032801A (ja) | 半導体装置の製造方法 | |
KR100195245B1 (ko) | 반도체 장치의 콘택홀 형성방법 | |
KR100511929B1 (ko) | 반도체 장치의 콘택홀 형성방법_ | |
KR100800868B1 (ko) | 반도체 소자의 제조 방법 | |
KR20060078705A (ko) | 반도체 소자의 제조 방법 | |
KR20040001786A (ko) | 반도체 소자의 제조 방법 | |
KR20100021758A (ko) | 인덕터의 금속 배선 형성 방법 | |
KR20090068588A (ko) | 반도체 소자의 패턴 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20201016 |