CN111508831A - 蚀刻方法、等离子体处理装置和处理系统 - Google Patents
蚀刻方法、等离子体处理装置和处理系统 Download PDFInfo
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- CN111508831A CN111508831A CN202010045816.1A CN202010045816A CN111508831A CN 111508831 A CN111508831 A CN 111508831A CN 202010045816 A CN202010045816 A CN 202010045816A CN 111508831 A CN111508831 A CN 111508831A
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- silicon
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- gas
- plasma processing
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- 238000000034 method Methods 0.000 title claims abstract description 98
- 238000005530 etching Methods 0.000 title claims abstract description 45
- 238000012545 processing Methods 0.000 title claims description 155
- 239000007789 gas Substances 0.000 claims abstract description 208
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 129
- 239000010703 silicon Substances 0.000 claims abstract description 129
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 127
- 239000000758 substrate Substances 0.000 claims abstract description 127
- 238000001020 plasma etching Methods 0.000 claims abstract description 46
- 239000002243 precursor Substances 0.000 claims abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 35
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 24
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 15
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 12
- 238000009832 plasma treatment Methods 0.000 claims abstract description 12
- 238000012546 transfer Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- FZHAPNGMFPVSLP-UHFFFAOYSA-N silanamine Chemical compound [SiH3]N FZHAPNGMFPVSLP-UHFFFAOYSA-N 0.000 claims description 7
- 238000007865 diluting Methods 0.000 claims description 5
- 238000002474 experimental method Methods 0.000 description 20
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000001228 spectrum Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 230000003667 anti-reflective effect Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 5
- 239000013626 chemical specie Substances 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000003085 diluting agent Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 3
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- 238000010494 dissociation reaction Methods 0.000 description 2
- 230000005593 dissociations Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- -1 silicon halide Chemical class 0.000 description 2
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000003507 refrigerant Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32899—Multiple chambers, e.g. cluster tools
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/02—Details
- H01J37/18—Vacuum locks ; Means for obtaining or maintaining the desired pressure within the vessel
- H01J37/185—Means for transferring objects between different enclosures of different pressure or atmosphere
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/36—Carbonitrides
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
- C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
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- H—ELECTRICITY
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- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
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- H—ELECTRICITY
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- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32174—Circuits specially adapted for controlling the RF discharge
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- H—ELECTRICITY
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- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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Abstract
本发明提供一种膜的蚀刻方法。一个实施方式的蚀刻方法包括在基片上形成含硅层的步骤。基片具有膜和掩模。含硅层由使用含有硅的前体气体的等离子体处理形成。含硅层包括硅、碳和氮。蚀刻方法还包括进行膜的等离子体蚀刻的步骤。从在基片上形成含硅层的步骤的开始时刻到进行膜的等离子体蚀刻的步骤的结束时刻的期间中,基片配置在减压了的环境下。由此,能够在掩模上形成与硅氧化层不同的层来对膜进行蚀刻。
Description
技术领域
本发明例示的实施方式涉及蚀刻方法、等离子体处理装置和处理系统。
背景技术
在电子器件的制造中,为了将掩模的图案转印至基片的膜而进行等离子体蚀刻。在等离子体蚀刻执行前为了使掩模的开口宽幅变窄,有时在基片上形成硅氧化层。基片的膜中,利用等离子体蚀刻对硅氧化层有选择地进行蚀刻。这样的技术记载于专利文献1。
现有技术文献
专利文献
专利文献1:日本特开2016-76621号公报。
发明内容
发明要解决的技术问题
要求在掩模上形成与硅氧化层不同的层来对膜进行蚀刻。
用于解决问题的技术手段
在一个例示的实施方式中,提供一种对膜进行的蚀刻方法。蚀刻方法包括在基片上形成含硅层的步骤。基片具有膜和掩模。掩模设置在膜上并被图案化。含硅层通过使用了含硅的前体气体的等离子体处理而形成。含硅层包括硅、碳和氮。含硅层的材料与膜的材料不同。蚀刻方法还包括进行膜的等离子体蚀刻的步骤。从在基片上形成含硅层的步骤的开始时刻到进行膜的等离子体蚀刻的步骤的结束时刻为止的期间中,基片配置在被减压了的环境下。
发明效果
根据一个例示的实施方式,能够在掩模上形成与硅氧化层不同的层来对膜进行蚀刻。
附图说明
图1是一个例示的实施方式的蚀刻方法的流程图。
图2中,图2的(a)是掩模的形成前的一个状态下的一例的基片的局部放大截面图,图2的(b)是掩模的形成前的另一状态下的一例的基片的局部放大截面图,图2的(c)是一例的基片的局部放大截面图。
图3是概略表示能够在图1所示的蚀刻方法的执行中使用的一例的等离子体处理装置的图。
图4中,图4的(a)是方法MT的步骤ST1执行后的状态下的一例的基片的局部放大截面图,图4的(b)是进行了含硅层的回蚀后的状态下的一例的基片的局部放大截面图。
图5中,图5的(a)是方法MT的步骤ST2执行后的状态下的一例的基片的局部放大截面图,图5的(b)是掩模除去后的状态下的一例的基片的局部放大截面图。
图6是图1所示的蚀刻方法的步骤ST1的一例的时序图。
图7是概要表示能够在图1所示的蚀刻方法的执行中使用的一例的处理系统的图。
图8中,图8的(a)是处理前的样品的图像,图8的(b)是比较实验的步骤ST2应用后的样品的图像,图8的(c)是实验的步骤ST2应用后的样品的图像。
图9是表示另一实验中制作出的含硅层的X射线光电子分光法得到的Si-2p谱的图。
附图标记说明
1……等离子体处理装置,10……腔室,GS……气体供给部,62……第一高频电源,64……第二高频电源,MC……控制部,MT……方法,W……基片。
具体实施方式
以下说明各种例示的实施方式。
在一个例示的实施方式中提供膜的蚀刻方法。蚀刻方法包括在基片上形成含硅层的步骤。基片具有膜和掩模。掩模设置在膜上并被图案化。含硅层通过使用了含硅的前体气体的等离子体处理而形成。含硅层包括硅、碳和氮。含硅层的材料与膜的材料不同。蚀刻方法还包括进行膜的等离子体蚀刻的步骤。从在基片上形成含硅层的步骤的开始时刻到进行膜的等离子体蚀刻的步骤的结束时刻为止的期间中,基片配置在被减压了的环境下。
上述实施方式的蚀刻方法中,形成在掩模上的含硅层包含硅、碳和氮。由此,能够在掩模上形成与硅氧化层不同的层而蚀刻膜。
在一个例示的实施方式中可以是,前体气体可以是氨基硅烷类气体。
在一个例示的实施方式中可以是,形成含硅层的步骤包括使用了含有前体气体和稀释该前体气体的气体的混合气体的等离子体处理。
在一个例示的实施方式中,形成含硅层的步骤反复执行流程。该流程中包括在第一期间、接续该第一期间的第二期间、接续该第二期间的第三期间中,将稀释前体气体的气体向基片供给的步骤。流程中包括在第一期间和第二期间中,将前体气体向基片供给的步骤。流程中包括为了在第二期间中由前体气体和稀释前体气体的气体形成等离子体、在第三期间中由稀释前体气体的气体生成等离子体,在第二期间和第三期间中供给高频电功率的步骤。
在一个例示的实施方式中可以是,形成含硅层的步骤和进行膜的等离子体蚀刻的步骤,使用单一的等离子体处理装置执行。从形成含硅层的步骤的开始时刻到进行膜的等离子体蚀刻的步骤的结束时刻为止的期间中,基片能够配置在单一的等离子体处理装置的腔室内。
在一个例示的实施方式中可以是,形成含硅层的步骤中使用的第一等离子体处理装置与在进行膜的等离子体蚀刻的步骤中使用的第二等离子体处理装置经由真空输送系统连接。形成含硅层的步骤的执行中,基片配置在第一等离子体处理装置的腔室内。形成含硅层的步骤执行后,在进行膜的等离子体蚀刻的步骤执行前,基片仅经由真空输送系统从第一等离子体处理装置被输送至第二等离子体处理装置。在进行膜的等离子体蚀刻的步骤的执行中,基片配置在第二等离子体处理装置的腔室内。
在一个例示的实施方式中,在形成含硅层的步骤中,基片的温度能够设定为150℃以下的温度。根据该实施方式,能够减少含硅层形成时的基片的温度与膜蚀刻时的基片的温度的差。
在一个例示的实施方式中可以是,含硅层可以在其骨架中不具有硅和氧的键。在一个例示的实施方式中,膜可以是硅氧化膜。含硅层的形成不暴露于大气地进行,因此含硅层的氧化得到抑制。在膜为硅氧化膜时,膜的等离子体蚀刻时的含硅层的蚀刻得到抑制。
在另一例示的实施方式中,提供在膜的蚀刻中使用的等离子体处理装置。等离子体处理装置包括腔室、气体供给部、高频电源和控制部。气体供给部与腔室连接。高频电源为了从腔室内的气体形成等离子体而供给高频电功率。控制部控制气体供给部和高频电源。控制部为了在基片上形成含硅层,以将含有硅的前体气体向腔室内供给的方式控制气体供给部,以供给高频电功率的方式控制高频电源。基片具有膜和掩模。掩模设置在膜上,被图案化。含硅层包含硅、碳和氮,由与膜的材料不同的材料形成。控制部为了进行膜的等离子体蚀刻,以将处理气体向腔室内供给的方式控制气体供给部,以供给高频电功率的方式控制高频电源。
在又一例示的实施方式中,提供在膜的蚀刻中使用的处理系统。处理系统包括第一等离子体处理装置、第二等离子体处理装置、真空输送系统和控制部。真空输送系统以在第一等离子体处理装置与第二等离子体处理装置之间输送基片的方式构成。控制部以控制第一等离子体处理装置、第二等离子体处理装置和真空输送系统的方式构成。第一等离子体处理装置和第二等离子体处理装置各自具有腔室、气体供给部和高频电源。气体供给部与腔室连接。高频电源为了从腔室内的气体形成等离子体以供给高频电功率的方式构成。控制部为了在基片上形成含硅层,以将含有硅的前体气体向第一等离子体处理装置的腔室内供给的方式控制第一等离子体处理装置的气体供给部,以供给高频电功率的方式控制第一等离子体处理装置的高频电源。基片具有膜和掩模。掩模设置在膜上,被图案化。含硅层包含硅、碳和氮,由与膜的材料不同的材料形成。控制部为了进行膜的等离子体蚀刻,以将处理气体向第二等离子体处理装置的腔室内供给的方式控制第二等离子体处理装置的气体供给部,以供给高频电功率的方式控制第二等离子体处理装置的高频电源。
以下,参照附图详细说明各种例示的实施方式。另外,在各图中对相同或相应的部分标注相同的附图标记。
图1是一个例示的实施方式的蚀刻方法的流程图。图1所示的蚀刻方法(以下称为“方法MT”)为了进行基片的膜的蚀刻而执行。方法MT中被蚀刻的基片的膜由与后述的含硅层的材料不同的材料形成。方法MT中被蚀刻的基片的膜只要是能够对含硅层有选择地进行蚀刻,则能够由任意的材料形成。方法MT中被蚀刻的基片的膜例如是硅氧化膜、多晶硅膜、硅氮化膜、或碳膜。
图2的(c)是一例的基片的局部放大截面图。图2的(c)所示的基片W具有硅氧化膜OSF和掩模MK。基片W可以还具有基底区域UR。硅氧化膜OSF是方法MT中被蚀刻的膜的一例。硅氧化膜OSF设置在基底区域UR上。掩模MK设置在硅氧化膜OSF上。掩模MK被图案化。即,掩模MK提供一个以上的开口。掩模MK的一个以上的开口使硅氧化膜OSF露出。掩模MK只要由与硅氧化膜不同的材料形成,则能够由一个以上的任意材料形成。此外,掩模MK能够由单一的膜或多层膜形成。
在一实施方式中,方法MT使用单一的等离子体处理装置执行。图3是概略表示图1所示的蚀刻方法的执行中能够使用的一例的等离子体处理装置的图。图3所示的等离子体处理装置1是容量耦合型的等离子体处理装置。等离子体处理装置1具有腔室10。腔室10在其中提供内部空间10s。
腔室10含有腔室主体12。腔室主体12具有大致圆筒形状。内部空间10s在腔室主体12的内侧被提供。腔室主体12由铝等导体形成。腔室主体12接地。对腔室主体12的内壁面施加了具有耐腐蚀性的膜。具有耐腐蚀性的膜能够是由氧化铝、氧化钇等陶瓷形成的膜。
在腔室主体12的侧壁形成有通路12p。基片W在内部空间10s与腔室10的外部之间输送时,通过通路12p。通路12p能够由闸阀12g开闭。闸阀12g沿腔室主体12的侧壁设置。
在腔室主体12的底部上设置有支承部13。支承部13由绝缘材料形成。支承部13具有大致圆筒形状。支承部13在内部空间10s中从腔室主体12的底部向上方延伸。支承部13支承基片支承器14。基片支承器14构成为在腔室10内、即在内部空间10s中,支承基片W。
基片支承器14具有下部电极18和静电吸盘20。下部电极18和静电吸盘20设置在腔室10内。基片支承器14还能够具有电极板16。电极板16由例如铝等导体形成,具有大致圆盘形状。下部电极18设置在电极板16上。下部电极18由例如铝等导体形成,具有大致圆盘形状。下部电极18与电极板16电连接。
静电吸盘20设置在下部电极18上。在静电吸盘20的上表面之上载置基片W。静电吸盘20具有主体和电极。静电吸盘20的主体由电介质形成。静电吸盘20的电极是膜状的电极,设置在静电吸盘20的主体内。静电吸盘20的电极经由开关20s与直流电源20p连接。对静电吸盘20的电极施加来自直流电源20p的电压时,在静电吸盘20与基片W之间产生静电引力。利用产生的静电引力,基片W被吸附至静电吸盘20,由静电吸盘20保持。
在基片支承器14上配置边缘环FR。边缘环FR没有限定,但能够由硅、碳化硅或石英形成。在腔室10内中进行基片W的处理时,基片W配置在静电吸盘20上且由边缘环FR包围的区域内。
在下部电极18的内部设置有流路18f。从冷却单元22经由配管22a对流路18f供给热交换介质(例如致冷剂)。冷却单元22设置在腔室10的外部。供给至流路18f的热交换介质经由配管22b回到冷却单元22。在等离子体处理装置1中,载置在静电吸盘20上的基片W的温度通过热交换介质与下部电极18的热交换被调节。
等离子体处理装置1还能够具有气体供给线24。气体供给线24将传热气体(例如He气体)供给到静电吸盘20的上表面与基片W的背面之间。传热气体从传热气体供给机构供给到气体供给线24。
等离子体处理装置1还具有上部电极30。上部电极30设置在基片支承器14的上方。上部电极30经由部件32支承在腔室主体12的上部。部件32由具有绝缘性的材料形成。上部电极30和部件32关闭腔室主体12的上部开口。
上部电极30能够包括顶板34和支承体36。顶板34的下表面是内部空间10s侧的下表面,界定内部空间10s。顶板34由含硅材料形成。顶板34由例如硅或碳化硅形成。在顶板34形成有多个气体排出孔34a。多个气体排出孔34a将顶板34在其板厚方向上贯通。
支承体36可拆装地支承于顶板34。支承体36由铝等导电性材料形成。在支承体36的内部设置有气体扩散室36a。在支承体36形成有多个气体孔36b。多个气体孔36b从气体扩散室36a向下方延伸。多个气体孔36b与多个气体排出孔34a分别连通。在支承体36形成有气体导入口36c。气体导入口36c与气体扩散室36a连接。在气体导入口36c连接有气体供给管38。
在气体供给管38经由阀组41、流量控制器组42和阀组43连接有气源组40。气源组40、阀组41、流量控制器组42和阀组43构成气体供给部GS。气源组40具有多个气源。气源组40的多个气源包括在方法MT中利用的多个气体的源。阀组41和阀组43分别包含多个开闭阀。流量控制器组42包含多个流量控制器。流量控制器组42的多个流量控制器分别是质量流量控制器或压力控制式的流量控制器。气源组40的多个气源分别经由阀组41的对应的开闭阀、流量控制器组42的对应的流量控制器和阀组43的对应的开闭阀与气体供给管38连接。
在等离子体处理装置1中,沿着腔室主体12的内壁面可拆装地设置有屏蔽件46。屏蔽件46也设置在支承部13的外周。屏蔽件46防止离子体处理的副生物附着于腔室主体12。屏蔽件46通过在例如由铝形成的部件的表面形成具有耐腐蚀性的膜而构成。具有耐腐蚀性的膜能够是由氧化钇等陶瓷形成的膜。
在支承部13与腔室主体12的侧壁之间,设置有挡板48。挡板48例如通过在由铝形成的部件的表面形成具有耐腐蚀性的膜而构成。具有耐腐蚀性的膜能够是由氧化钇等陶瓷形成的膜。在挡板48形成有多个贯通孔。在挡板48的下方且在腔室主体12的底部设置有排气口12e。在排气口12e经由排气管52连接有排气装置50。排气装置50具有压力调节阀和涡轮分子泵等真空泵。
等离子体处理装置1还具有第一高频电源62和第二高频电源64。第一高频电源62是产生第一高频电功率的电源。第一高频电功率在一例中具有与等离子体的生成对应的频率。第一高频电功率的频率是例如27MHz~100MHz的范围内的频率。在一例中,第一高频电功率的频率能够是60MHz。第一高频电源62经由匹配器66和电极板16与上部电极30连接。匹配器66具有用于使第一高频电源62的输出阻抗与负载侧(上部电极30侧)的阻抗匹配的电路。另外,第一高频电源62也可以经由匹配器66与下部电极18连接。
第二高频电源64是产生第二高频电功率的电源。第二高频电功率具有比第一高频电功率的频率低的频率。第二高频电功率能够用作用于向基片W引入离子的偏置用的高频电功率。第二高频电功率的频率是例如400kHz~40MHz的范围内的频率。在一例中,第二高频电功率的频率能够是40MHz。第二高频电源64经由匹配器68和电极板16与下部电极18连接。匹配器68具有用于使第二高频电源64的输出阻抗与负载侧(下部电极18侧)的阻抗匹配的电路。另外,等离子体处理装置1也可以仅具有第一高频电源62和第二高频电源64中的任一者。
等离子体处理装置1还具有控制部MC。控制部MC能够是具有处理器、存储器等存储部、输入装置、显示装置、信号的输入输出接口等的计算机。控制部MC控制等离子体处理装置1的各部分。控制部MC中,操作员能够使用输入装置进行用于管理等离子体处理装置1的命令的输入操作等。此外,控制部MC中,能够利用显示装置将等离子体处理装置1的运转状况可视化显示。进而,在控制部MC的存储部中存储有控制程序和方案数据。为了在等离子体处理装置1执行各种处理,由控制部MC的处理器执行控制程序。控制部MC的处理器执行控制程序,依据方案数据控制等离子体处理装置1的各部分,由此方法MT被等离子体处理装置1执行。
再次参照图1,详细说明方法MT。在以下的说明中,以使用等离子体处理装置1对基片W应用方法MT的情况为例,说明方法MT。另外,方法MT也可以应用于与例示的基片W不同的基片。此外,在以下的说明中,也详细说明控制部MC进行的等离子体处理装置1的各部分的控制。此外,在以下的说明中,除了图1,还参照图2的(a)、图2的(b)、图2的(c)、图4的(a)、图4的(b)、图5的(a)和图5的(b)。图2的(a)是掩模形成前的一个状态下的一例的基片的局部放大截面图,图2的(b)是掩模形成前的另一状态下的一例的基片的局部放大截面图,图2的(c)是一例的基片的局部放大截面图。图4的(a)是方法MT的步骤ST1执行后的状态下的一例的基片的局部放大截面图,图4的(b)是进行了含硅层的回蚀后的状态下的一例的基片的局部放大截面图。图5的(a)是方法MT的步骤ST2执行后的状态下的一例的基片的局部放大截面图,图5的(b)是掩模除去后的状态下的一例的基片的局部放大截面图。
如图1所示方法MT包括步骤ST1和步骤ST2。如图2的(a)所示,基片W在步骤ST1执行前的状态中,也可以还具有有机膜OF、反射防止膜ARF和抗蚀剂掩模RM。有机膜OF设置在硅氧化膜OSF上。反射防止膜ARF设置在有机膜OF上。反射防止膜ARF能够含有硅。抗蚀剂掩模RM设置在反射防止膜ARF上。抗蚀剂掩模RM被图案化。即,抗蚀剂掩模RM提供一个以上的开口。抗蚀剂掩模RM例如使用光刻技术图案化。
方法MT可能还包括形成掩模MK的步骤。形成掩模MK的步骤在步骤ST1执行前进行。为了从图2的(a)所示的基片W形成掩模MK,形成掩模MK的步骤中,进行反射防止膜ARF的等离子体蚀刻。在反射防止膜ARF的等离子体蚀刻的执行中,基片W被静电吸盘20保持。反射防止膜ARF的等离子体蚀刻中,在腔室10内从处理气体生成等离子体。该处理气体能够包括CF4气体等碳氟化合物气体。反射防止膜ARF被从等离子体供给的化学种蚀刻。反射防止膜ARF的等离子体蚀刻的结果是,如图2的(b)所示,抗蚀剂掩模RM的图案转印至反射防止膜ARF。
为了进行反射防止膜ARF的等离子体蚀刻,控制部MC控制气体供给部GS,将处理气体向腔室10内供给。控制部MC控制排气装置50,将腔室10内的压力设定为指定的压力。为了进行反射防止膜ARF的等离子体蚀刻,控制部MC控制第一高频电源62和/或第二高频电源64,以供给第一高频电功率和/或第二高频电功率。
在形成掩模MK的步骤中,接着,为了从图2的(b)所示的基片W形成掩模MK,进行有机膜OF的等离子体蚀刻。在有机膜OF的等离子体蚀刻的执行中,基片W被静电吸盘20保持。有机膜OF的等离子体蚀刻中,在腔室10内从处理气体生成等离子体。该处理气体例如是氢气和氮气的混合气体。该处理气体也可以是含氧气体。有机膜OF被从等离子体供给的化学种蚀刻。有机膜OF的等离子体蚀刻的结果是,如图2的(c)所示,反射防止膜ARF的图案转印至有机膜OF。结果形成掩模MK。在该例中,掩模MK包括抗蚀剂掩模RM、反射防止膜ARF和有机膜OF。
为了进行有机膜OF的等离子体蚀刻,控制部MC控制气体供给部GS,将处理气体向腔室10内供给。控制部MC控制排气装置50,将腔室10内的压力设定为指定的压力。为了进行有机膜OF的等离子体蚀刻,控制部MC控制第一高频电源62和/或第二高频电源64,以供给第一高频电功率和/或第二高频电功率。
方法MT中,为了在具有掩模MK的基片W上如图4的(a)所示形成含硅层SCF,执行步骤ST1。含硅层SCF通过使用含有硅的前体气体的等离子体处理形成。含硅层SCF包括硅、碳和氮。含硅层SFC由与在步骤ST2被蚀刻的膜(一例中是硅氧化膜OSF)的材料不同的材料形成。在一实施方式中,含硅层SCF可以实质上在其骨架中不具有硅与氧的键。含硅层SCF能够是碳氮化硅膜(SiCN膜)。在一实施方式中,前体气体包括氨基硅烷类气体。一实施方式中,含硅层SCF可以通过使用前体气体和将前体气体稀释的气体(以下称为“稀释气体”)的混合气体的等离子体处理而形成。稀释气体能够包括含氧气体、含氢气体、稀有气体等。含氢气体能够包括氢气(H2气体)和/或CH4气体等碳氢化合物气体。稀释气体可以是使前体气体氧化的气体,或者可以是使前体气体还原的气体。步骤ST1中使用的混合气体可以还包含氩气等稀有气体。
在一实施方式中,步骤ST1中,为了抑制前体气体的过度离解,第一高频电功率的功率等级和/或第二高频电功率的功率等级设定为比较低的功率等级。在一实施方式中,步骤ST1中,为了生成等离子体,仅供给第一高频电功率和第二高频电功率中的第二高频电功率。一实施方式中,步骤ST1中,为了抑制前体气体的过度离解,腔室10内的压力可以设定为比较高的压力。
在另一实施方式中,前体气体可以是SiCl4气体等卤化硅气体。该实施方式中,通过使用除了前体气体还包含含氮气体和含碳气体的混合气体的等离子体处理,形成含硅层SCF。含氮气体例如是NH3气体。含碳气体能够是CH4气体等碳氢化合物气体。
为了执行步骤ST1,控制部MC控制气体供给部GS,将上述的前体气体或混合气体向腔室10内供给。为了执行步骤ST1,控制部MC控制排气装置50,将腔室10内的压力设定为指定的压力。为了执行步骤ST1,控制部MC控制第一高频电源62和/或第二高频电源64,以供给第一高频电功率和/或第二高频电功率。
以下,参照图6。图6是图1所示的蚀刻方法的步骤ST1的一例的时序图。在图6中,横轴表示时间。图6中,纵轴表示步骤ST1中使用的其它气体的流量、即上述混合气体中的前体气体以外的气体的流量、前体气体的流量和高频电功率。如图6所示,一实施方式的步骤ST1可以包括反复进行流程SQ的内容。
流程SQ包括将其它气体供给到基片W的内容。其它气体在前体气体为氨基硅烷类气体时包括上述稀释气体。其它气体在前体气体为氨基硅烷类气体时,能够还包括上述稀有气体。其它气体在前体气体为卤化硅气体时包括上述含氮气体和含碳气体。其它气体在第一期间P1、第二期间P2和第三期间P3中供给到基片W。第二期间P2是接续第一期间P1的期间。第三期间P3是接续第二期间P2的期间。
流程SQ在第一期间P1和第二期间P2中,还包括将上述前体气体向基片W供给的内容。流程SQ包括在第二期间P2和第三期间P3中供给第一高频电功率和/或第二高频电功率的内容。第二期间P2中,在腔室10内从混合气体形成等离子体。第三期间P3中,在腔室10内,从其它气体形成等离子体。通过反复进行该流程SQ,能够对基片W的表面形成含硅层SCF。此外,通过设定流程SQ的反复进行次数,能够调节含硅层SCF的膜厚。
另外,流程SQ内的第二期间P2中,可以不供给第一高频电功率和第二高频电功率。即,流程SQ内的第二期间P2中,在腔室10内可以不生成等离子体。此时,在第二期间P2中,前体气体吸附于基片W。或者,流程SQ内的第一期间P1~第三期间P3中,在腔室10内可以生成等离子体。通过调节在流程SQ内生成等离子体的期间,能够调节形成在基片W上的含硅层SCF的膜厚。此外,通过调节第一期间P1和/或第二期间P2中的腔室10内的气体的压力和/或第二高频电功率的功率等级,能够调节形成含硅层SCF的部位。例如,通过将第一期间P1和/或第二期间P2中的腔室10内的气体的压力设定为比较高的压力,能够各向同性地形成含硅层SCF。此外也可以是,第一期间P1和/或第二期间P2中,腔室10内的气体的压力设定为比较低的压力,第二高频电功率的功率等级设定为比较高的等级。此时,含硅层SCF容易优先地形成在掩模MK的上表面和界定掩模MK的开口的底面。
方法MT中,接着可以如图4的(b)所示,进行含硅层SCF的回蚀。具体地说,在掩模MK的上表面之上和硅氧化膜OSF的表面上延伸存在的含硅层SCF的部分区域被除去,沿着掩模MK的侧壁延伸存在的含硅层SCF的其它部分区域留下。
在含硅层SCF的回蚀的执行中,基片W被静电吸盘20保持。含硅层SCF的回蚀中,在腔室10内从处理气体生成等离子体。该处理气体包括例如CF4气体等碳氟化合物气体。含硅层SCF的部分区域被从等离子体供给的化学种蚀刻。
为了进行含硅层SCF的回蚀,控制部MC控制气体供给部GS,以向腔室10内供给处理气体。为了进行含硅层SCF的回蚀,控制部MC控制排气装置50,以将腔室10内的压力控制在指定的压力。含硅层SCF的回蚀是各向异性蚀刻。由此,为了进行含硅层SCF的回蚀,控制部MC控制第一高频电源62和第二高频电源64,而供给第一高频电功率和第二高频电功率。
方法MT中,接着执行步骤ST2。步骤ST2中进行基片的膜的等离子体蚀刻。步骤ST2的执行中,基片被静电吸盘20保持。步骤ST2中,在腔室10内从处理气体形成等离子体。步骤ST2中使用的处理气体能够是能够相对于含硅层SCF有选择地蚀刻膜的任意的气体。步骤ST2中,基片的膜被从等离子体供给的化学种蚀刻。
一例的步骤ST2中,进行基片W的硅氧化膜OSF的等离子体蚀刻。步骤ST2的执行中,基片W被静电吸盘20保持。步骤ST2中,在腔室10内从处理气体生成等离子体。该处理气体包括C4F6气体等碳氟化合物气体。该处理气体还包括氧气(O2气体)和氩气等稀有气体。步骤ST2中,硅氧化膜OSF被从等离子体供给的化学种蚀刻。硅氧化膜OSF的等离子体蚀刻的结果是,如图5的(a)所示,掩模MK的图案转印至硅氧化膜OSF。另外,步骤ST2的执行中,抗蚀剂掩模RM和反射防止膜ARF也能够被蚀刻。
为了执行步骤ST2,控制部MC控制气体供给部GS,以向腔室10内供给处理气体。为了执行步骤ST2,控制部MC控制排气装置50,以将腔室10内的压力控制在指定的压力。为了执行步骤ST2,控制部MC控制第一高频电源62和第二高频电源64,来供给第一高频电功率和第二高频电功率。
方法MT可以还包括除去掩模MK的步骤。掩模MK即有机膜OF通过使用O2气体等含氧气体的等离子体处理被除去。结果制成图5的(b)所示的基片W。
为了除去掩模MK,控制部MC控制气体供给部GS,以向腔室10内供给含氧气体。为了除去掩模MK,控制部MC控制排气装置50,以将腔室10内的压力控制在指定的压力。为了除去掩模MK,控制部MC控制第一高频电源62和第二高频电源64,来供给第一高频电功率和第二高频电功率。
方法MT中,形成在掩模上的含硅层SCF包括硅、碳和氮。由此,能够在掩模上形成与硅氧化层不同的层,而蚀刻膜。
方法MT中,至少从步骤ST1的开始时刻到步骤ST2的结束时刻的期间中,基片W配置在减压了的环境下。即,方法MT中,至少从步骤ST1的开始时刻到步骤ST2的结束时刻的期间中,基片W不暴露于大气。换言之,至少从步骤ST1的开始时刻到步骤ST2的结束时刻的期间中,配置有基片W的环境中不破坏真空地处理基片W。一实施方式中,至少从步骤ST1的开始时刻到步骤ST2的结束时刻的期间中,基片W配置在单一的等离子体处理装置1的腔室10内。
一实施方式中,形成在掩模MK上的含硅层SCF在其骨架中实质上不具有硅与氧的键。此外,含硅层SCF能够不暴露于大气地进行硅氧化膜OSF的蚀刻。由此,含硅层SCF的氧化受到抑制。因此,硅氧化膜OSF的等离子体蚀刻时的含硅层SCF的蚀刻得到抑制。
一实施方式的步骤ST1中,基片W的温度可以设定于150℃以下的温度。在步骤ST2执行时,基片W的温度能够设定为比步骤ST1执行时的基片W的温度低的温度。一般含硅层形成时的基片的温度设定为400℃等相当高的温度,但该实施方式中含硅层SCF形成时的基片W的温度低。由此,根据该实施方式,能够减少含硅层SCF形成时的基片W的温度与膜(一例中是硅氧化膜OSF)蚀刻时的基片W的温度的差。由此,能够缩短从步骤ST1转移到步骤ST2的时间。
以下参照图7。图7是概略表示图1所示的蚀刻方法的执行中能够使用的一例的处理系统的图。只要至少从步骤ST1的开始时刻到步骤ST2的结束时刻的期间中,基片W配置在减压了的环境下,则步骤ST1和步骤ST2也可以使用不同的等离子体处理装置来执行。图7所示的处理系统此时能够利用于方法MT的执行。
图7所示的处理系统PS包括基座2a~2d、容器4a~4d、装载模块LM、对准器AN、装载互锁模块LL1、LL2、处理模块PM1~PM6、输送模块TF和控制部MC。另外,处理系统PS中的基座的个数、容器的个数、装载互锁模块的个数能够是2以上的任意的个数。此外,处理模块的个数能够是2以上的任意的个数。
基座2a~2d沿装载模块LM的一个边缘排列。容器4a~4d分别搭载在基座2a~2d上。容器4a~4d各自是例如被称为FOUP(Front Opening Unified Pod,前开式传输盒)的容器。容器4a~4d分别构成为在其内部收纳基片W。
装载模块LM具有腔室。装载模块LM的腔室内的压力设定为大气压。在装载模块LM的腔室内设置有输送装置TU1。输送装置TU1例如是多关节机械手,被控制部MC控制。输送装置TU1构成为在各个容器4a~4d与对准器AN之间、对准器AN与各个装载互锁模块LL1~LL2之间、各个装载互锁模块LL1~LL2与各个容器4a~4d之间输送基片W。对准器AN与装载模块LM连接。对准器AN构成为进行基片W的位置的调节(位置的校正)。
装载互锁模块LL1和装载互锁模块LL2分别设置于装载模块LM与输送模块TF之间。装载互锁模块LL1和装载互锁模块LL2分别提供预备减压室。
输送模块TF与装载互锁模块LL1和装载互锁模块LL2经由闸阀连接。输送模块TF具有能够减压的输送腔室TC。在输送腔室TC内,设置有输送装置TU2。输送装置TU2例如是多关节机械手,被控制部MC控制。输送装置TU2构成为在各个装载互锁模块LL1~LL2与各个处理模块PM1~PM6之间和处理模块PM1~PM6中的任意2个处理模块之间输送基片W。
处理模块PM1~PM6分别是以进行专用的基片处理的方式构成的处理装置。处理模块PM1~PM6中的一个处理模块是第一等离子体处理装置1a。处理模块PM1~PM6中的另一个处理模块是第二等离子体处理装置1b。图7所示的例子中,处理模块PM1是第一等离子体处理装置1a,处理模块PM2是第二等离子体处理装置1b。一实施方式中,第一等离子体处理装置1a和第二等离子体处理装置1b分别能够是与等离子体处理装置1相同的等离子体处理装置。
上述输送模块TF构成真空输送系统。输送模块TF构成为在第一等离子体处理装置1a与第二等离子体处理装置1b之间输送基片。
控制部MC在处理系统PS中控制该处理系统PS的各部分,例如第一等离子体处理装置1a、第二等离子体处理装置1b、输送模块TF。
为了执行步骤ST1的第一等离子体处理装置1a的各部分的由控制部MC所进行的控制,与用于执行上述步骤ST1的等离子体处理装置1的各部分的由控制部MC所进行的控制同样。具体地说,控制部MC为了执行步骤ST1,控制第一等离子体处理装置1a的气体供给部GS,以将上述前体气体或混合气体向第一等离子体处理装置1a的腔室10内供给。此外,为了执行步骤ST1,控制部MC控制第一等离子体处理装置1a的排气装置50,以将第一等离子体处理装置1a的腔室10内的压力控制为指定的压力。此外,控制部MC为了执行步骤ST1,控制第一等离子体处理装置1a的第一高频电源62和/或第一等离子体处理装置1a的第二高频电源64,而供给第一高频电功率和/或第二高频电功率。
控制部MC在步骤ST1执行后,在步骤ST2执行前,将基片W经由输送模块TF的减压了的腔室从第一等离子体处理装置1a的腔室10的内部空间10s向第二等离子体处理装置1b的腔室10的内部空间10s输送。为了进行该输送,控制部MC控制输送模块TF。方法MT中使用处理系统PS时,至少从步骤ST1的开始时刻到步骤ST2的结束时刻的期间中,基片W也不暴露于大气。换言之,至少从步骤ST1的开始时刻到步骤ST2的结束时刻的期间中,配置有基片W的环境中不破坏真空地处理基片W。
为了执行步骤ST2的第二等离子体处理装置1b的各部分的由控制部MC所进行的控制,与为了执行上述步骤ST2的等离子体处理装置1的各部分的由控制部MC所进行的控制同样。具体地说,控制部MC为了执行步骤ST2,控制第二等离子体处理装置1b的气体供给部GS,以向第二等离子体处理装置1b的腔室10内供给处理气体。此外,控制部MC为了执行步骤ST2,控制第二等离子体处理装置1b的排气装置50,以将第二等离子体处理装置1b的腔室10内的压力控制为指定的压力。此外,控制部MC为了执行步骤ST2,控制第二等离子体处理装置1b的第一高频电源62和第二等离子体处理装置1b的第二高频电源64,而供给第一高频电功率和第二高频电功率。
另外,为了进行反射防止膜ARF的等离子体蚀刻,第一等离子体处理装置1a和第二等离子体处理装置1b中的一者的各部分可以与等离子体处理装置1的各部分同样地被控制。此外,为了进行有机膜OF的等离子体蚀刻,第一等离子体处理装置1a和第二等离子体处理装置1b中的一者的各部分可以与等离子体处理装置1的各部分同样地被控制。此外,为了进行含硅层SCF的回蚀,第一等离子体处理装置1a和第二等离子体处理装置1b中的一者的各部分可以与等离子体处理装置1的各部分同样地被控制。此外,为了除去掩模MK,第一等离子体处理装置1a和第二等离子体处理装置1b中的一者的各部分可以与等离子体处理装置1的各部分同样地被控制。反射防止膜ARF的等离子体蚀刻和有机膜OF的等离子体蚀刻可以使用与第一等离子体处理装置1a和第二等离子体处理装置1b不同的等离子体处理装置执行。此外,含硅层SCF的回蚀和反射防止膜ARF的等离子体蚀刻可以使用与第一等离子体处理装置1a和第二等离子体处理装置1b不同的等离子体处理装置执行。
以上说明了各种例示的实施方式,但并不限定于上述例示的实施方式,可以进行各种省略、置换和变更。此外,能够组合不同的实施方式的要素而形成其它实施方式。
例如,在方法MT的执行中使用的一个以上的等离子体处理装置各自可以为任意类型的等离子体处理装置。这样的等离子体处理装置可以是电感耦合型的等离子体处理装置或为了生成等离子体使用微波等表面波的等离子体处理装置。此外,第一等离子体处理装置1a和第二等离子体处理装置1b可以是彼此不同类型的等离子体处理装置。
以下说明为了进行方法MT的评价而进行的实验。在实验中,准备在硅膜上具有由硅氧化膜形成的线和间隔(line and space)图案的样品。样品的直径为300mm。使用处理系统PS对该样品应用步骤ST1和步骤ST2。实验中,使用第一等离子体处理装置1a进行步骤ST1,使用第二等离子体处理装置1b进行步骤ST2。实验中,从步骤ST1的开始时刻到步骤ST2的结束时刻,不将样品暴露于大气。即,实验中,从步骤ST1转移到步骤ST2时,仅经由输送模块TF的减压了的腔室内的空间从第一等离子体处理装置1a向第二等离子体处理装置1b输送该样品。
此外,为了进行比较而进行比较实验。比较实验中,准备与上述样品相同的样品,使用第一等离子体处理装置1a对该样品应用步骤ST1后,将该样品暴露于大气,然后,使用第二等离子体处理装置1b对该样品应用步骤ST2。
以下表示实验和比较实验各自的步骤ST1和步骤ST2的条件。
<步骤ST1的条件>
·氨基硅烷类气体:20sccm
·H2气体:400sccm
·氩气:800sccm
·腔室10内的压力:700mTorr(93.33Pa)
·第一高频电功率:0W
·第二高频电功率:40MHz,30W
·样品的温度:120℃
<步骤ST2的条件>
·C4F6气体:2.7sccm
·O2气体:2.5sccm
·氩气:1000sccm
·腔室10内的压力:30mTorr(4Pa)
·第一高频电功率:40MHz,350W
·第二高频电功率:13MHz,0W
·样品的温度:60℃
实验和比较实验中,取得步骤ST2执行后的样品的图像(SEM图像)。图8的(a)是处理前的样品的图像,图8的(b)是比较实验的应用步骤ST2后的样品的图像,图8的(c)是实验的应用步骤ST2后的样品的图像。对图8的(a)和图8的(b)进行比较可知,比较实验中,通过执行步骤ST2,硅氧化膜的线的膜厚大幅减少。这是因为,步骤ST1执行后,在步骤ST2执行前样品暴露于大气,因此在步骤ST1形成的含硅层氧化。另一方面,对图8的(a)和图8的(c)进行比较可知,实验中,硅氧化膜的线的膜厚几乎不减少。这是因为,在步骤ST1形成的含硅层,在步骤ST2执行前不被氧化,在步骤ST2的执行中保护硅氧化膜的线。
此外,在另外的实验中,使用等离子体处理装置1,在氧化硅制的晶片上形成有含硅层。该含硅层是前述MT中的ST1所形成的膜的一例。以下表示含硅层的形成条件。
<含硅层的形成条件>
·氨基硅烷类气体:100sccm
·H2气体:400sccm
·氩气:500sccm
·腔室10内的压力:500mTorr(87.5Pa)
·第一高频电功率:60MHz,300W
·第二高频电功率:0W
·晶片的温度:80℃
在大气中使用X射线光电子分光法取得形成的含硅层的Si-2p能谱。图9是表示在别的实验中制作出的含硅层的X射线光电子分光法所得到的Si-2p谱的图。此外,图9中,除了含硅层的Si-2p谱之外,还表示了氧化硅(SiO2)、氮化硅(SiN)、碳化硅(SiC)和多结晶硅各自的Si-2p谱。如图9所示,制作出的含硅层在氧化硅的谱与氮化硅的谱之间具有谱。此外,制作出的含硅层具有与氧化硅、氮化硅、碳化硅、多结晶硅各自的谱不同的谱。由此确认,根据上述形成条件,能够形成由与氧化硅、氮化硅、碳化硅、多结晶硅不同的材料形成的含硅层。
根据以上的说明可知,本发明的各种实施方式基于说明目的而在本说明书中进行了说明,在不脱离本发明的范围和主旨的条件下能够进行各种变更。由此,本发明书公开的各种实施方式不是限定性的,真正的范围和主旨在发明申请保护的范围中表示。
Claims (11)
1.一种对膜进行的蚀刻方法,其特征在于,包括:
在基片上形成含硅层的步骤,其中,该基片具有所述膜和设置在该膜上的被图案化的掩模;和
进行所述膜的等离子体蚀刻的步骤,
所述含硅层通过使用了含有硅的前体气体的等离子体处理而形成,包含硅、碳和氮,该含硅层的材料与所述膜的材料不同,
从在基片上形成含硅层的所述步骤的开始时刻到进行所述膜的等离子体蚀刻的所述步骤的结束时刻的期间中,所述基片配置在被减压了的环境下。
2.如权利要求1所述的蚀刻方法,其特征在于:
所述前体气体是氨基硅烷类气体。
3.如权利要求1或2所述的蚀刻方法,其特征在于:
在形成含硅层的所述步骤中,进行使用了包含所述前体气体和稀释所述前体气体的气体的混合气体的所述等离子体处理。
4.如权利要求1或2所述的蚀刻方法,其特征在于:
在形成含硅层的所述步骤中反复执行包含以下步骤的流程:
在第一期间、接续该第一期间的第二期间、接续该第二期间的第三期间中,将稀释所述前体气体的气体供给到所述基片,
在所述第一期间和所述第二期间中,将所述前体气体供给到所述基片,
为了在所述第二期间中从所述前体气体和稀释所述前体气体的所述气体形成等离子体,并在所述第三期间中从稀释所述前体气体的所述气体生成等离子体,在所述第二期间和所述第三期间中供给高频电功率。
5.如权利要求1~4中任一项所述的蚀刻方法,其特征在于:
形成含硅层的所述步骤和进行所述膜的等离子体蚀刻的所述步骤使用单一的等离子体处理装置来执行,
从形成含硅层的所述步骤的开始时刻到进行所述膜的等离子体蚀刻的所述步骤的结束时刻的期间中,所述基片配置在所述单一的等离子体处理装置的腔室内。
6.如权利要求1~4中任一项所述的蚀刻方法,其特征在于:
在形成含硅层的所述步骤中使用的第一等离子体处理装置,与在进行所述膜的等离子体蚀刻的所述步骤中使用的第二等离子体处理装置经由真空输送系统连接,
在形成含硅层的所述步骤执行的过程中,所述基片配置在所述第一等离子体处理装置的腔室内,
在形成含硅层的所述步骤执行后,在进行所述膜的等离子体蚀刻的所述步骤执行前,所述基片仅经由所述真空输送系统从所述第一等离子体处理装置被输送至所述第二等离子体处理装置,
在进行所述膜的等离子体蚀刻的所述步骤执行的过程中,所述基片配置在所述第二等离子体处理装置的腔室内。
7.如权利要求1~6中任一项所述的蚀刻方法,其特征在于:
在形成含硅层的所述步骤中,所述基片的温度设定为150℃以下的温度。
8.如权利要求1~7中任一项所述的蚀刻方法,其特征在于:
所述含硅层在其骨架中不具有硅与氧的键。
9.如权利要求1~8中任一项所述的蚀刻方法,其特征在于:
所述膜是硅氧化膜。
10.一种用于膜的蚀刻的等离子体处理装置,其特征在于,具有:
腔室;
与所述腔室连接的气体供给部;
为了从所述腔室内的气体形成等离子体而供给高频电功率的高频电源;和
控制所述气体供给部和所述高频电源的控制部,
所述控制部进行以下控制:
为了将包含硅、碳和氮且由与所述膜的材料不同的材料形成的含硅层,形成在具有所述膜和设置在该膜上的被图案化的掩模的基片上,而控制所述气体供给部以将含有硅的前体气体供给到所述腔室内,并控制所述高频电源以供给所述高频电功率,
为了进行所述膜的等离子体蚀刻,而控制所述气体供给部以将处理气体供给到所述腔室内,并控制所述高频电源以供给所述高频电功率。
11.一种用于膜的蚀刻的处理系统,其特征在于,具有:
第一等离子体处理装置;
第二等离子体处理装置;
在所述第一等离子体处理装置与所述第二等离子体处理装置之间输送基片的真空输送系统;和
控制所述第一等离子体处理装置、所述第二等离子体处理装置和所述真空输送系统的控制部,
所述第一等离子体处理装置和所述第二等离子体处理装置分别具有:
腔室;
与所述腔室连接的气体供给部;
为了从所述腔室内的气体形成等离子体而供给高频电功率的高频电源,
所述控制部进行以下控制:
为了将包含硅、碳和氮且由与所述膜的材料不同的材料形成的含硅层,形成在具有所述膜和设置在该膜上的被图案化的掩模的基片上,而控制所述第一等离子体处理装置的所述气体供给部以将含有硅的前体气体供给到所述第一等离子体处理装置的所述腔室内,并控制所述第一等离子体处理装置的所述高频电源以供给所述高频电功率,
控制所述真空输送系统以将所述基片从所述第一等离子体处理装置输送至所述第二等离子体处理装置,
为了进行所述膜的等离子体蚀刻,而控制所述第二等离子体处理装置的所述气体供给部以将处理气体供给到所述第二等离子体处理装置的所述腔室内,并控制所述第二等离子体处理装置的所述高频电源以供给所述高频电功率。
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