CN111373556B - 量子位芯片上的倒装芯片集成 - Google Patents
量子位芯片上的倒装芯片集成 Download PDFInfo
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- CN111373556B CN111373556B CN201880075199.0A CN201880075199A CN111373556B CN 111373556 B CN111373556 B CN 111373556B CN 201880075199 A CN201880075199 A CN 201880075199A CN 111373556 B CN111373556 B CN 111373556B
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Abstract
当量子位在第一芯片上形成并且光学透射路径在第二芯片上形成时,形成量子位(量子位)倒装芯片组件。使用焊料凸块接合两个芯片。光学透射路径提供对第一芯片上的量子位的光学访问。
Description
技术领域
本发明涉及芯片制造,并且更具体地,涉及用于量子计算的芯片制造。
背景技术
集成电路技术包括三维集成电路。一种类型的3D集成电路可以包括两层或更多层有源电子部件,这些有源电子部件垂直堆叠并且与贯穿衬底的通孔和焊料凸块电连接。3D集成电路可以提供许多益处,诸如通过使用硅通孔可以实现较短的连接长度,从而提高了封装密度,减小了占地面积并且提高了带宽。上述3D集成电路可以以任何数目的已知方法来制造。一些3D集成电路可以包括硅中介层,其可以用于在载体与一个或多个顶部芯片之间重定向电路。
量子计算使用计算系统来操纵诸如叠加和纠缠等的量子力学现象以实现信息处理。利用冯·诺依曼体系结构的经典计算机处理表示为1或0的二进制数据。在量子计算中,量子位(或"qubit")可以保持0、1的状态或状态的叠加。
发明内容
本公开的实施方案可以针对一种用于形成量子位(量子位)倒装芯片组件的方法。量子位可以形成在第一芯片上,并且光学透射路径可以形成在第二芯片上。第一芯片和第二芯片可以被接合。光学透射路径可以位于量子位之上。
本公开的实施例可以涉及一种具有第一芯片和第二芯片的倒装芯片装置。第一芯片可以包含量子位,并且第二芯片可以用焊料凸块接合到第一芯片。第二芯片可以具有光学透射路径以允许对第一芯片上的量子位的光学访问。
上述发明内容并非旨在描述本公开的每个所示实施例或每种实施方式。
本公开的实施方案可以涉及一种用于形成量子位(量子位)倒装芯片组件的方法。该方法可以包括在第一芯片上形成量子位。然后,可以在第二芯片上形成光学透射路径。可以结合第一芯片和第二芯片以将光学透射路径定位在量子位之上。
本公开的实施例可以涉及一种倒装芯片装置,该倒装芯片装置包括具有量子位(量子位)的第一芯片和第二芯片。第二芯片可以用焊料凸块接合到第一芯片。第二芯片中的光学透射路径可以提供对第一芯片上的量子位的光学访问。
附图说明
本申请中包括的附图被并入说明书中并形成说明书的一部分。附图示出了本公开的实施例,并且与说明书一起用于解释本公开的原理。附图仅说明某些实施例,而不限制本公开。
图1描绘了根据本发明的实施例的包含并联连接的约瑟夫逊结和电容器的量子位。
图2描绘了根据本发明的实施例的用于制造约瑟夫逊结的衬底的俯视图。
图3描绘了根据本发明的实施方案,经历激光退火的示例性量子位的俯视图。
图4描绘了根据本发明实施例的芯片组件的俯视图的示例图。
图5描绘了根据本发明实施例的在形成通孔之后的倒装芯片组件的俯视图的示例图。
图6描绘了根据本发明的实施例的已经被修改以允许量子位处理的倒装芯片组件的截面图。
图7描绘了根据本发明的实施例的经历激光退火的量子位的倒装芯片组件的截面图。
图8A-图8F描绘了根据本发明实施例的在倒装芯片组件的第一芯片中蚀刻通孔的方法的示意图。
图9A-图9F描绘了根据本发明实施例的使用深反应离子蚀刻技术在倒装芯片组件的顶部芯片中蚀刻通孔的方法的示意图。
图10描述了根据本发明的实施方案的用于形成量子位倒装芯片组件的示例方法1100的流程图。
虽然本发明可以有各种修改和替换形式,但是其细节已经通过示例在附图中示出并且将被详细描述。然而,应当理解,其目的不是将本发明限制于所描述的特定实施例。相反,本发明覆盖落入本发明范围内的所有修改、等效和替换。
具体实施方式
现在将参考附图在此更全面地描述示例实施例,在附图中示出了示例实施例。然而,本公开可以以许多不同的形式来实施,并且不应被解释为限于本文阐述的示例实施例。相反,提供这些示例实施例是为了使本公开透彻和完整,并且将本公开的范围传达给本领域技术人员。在描述中,可以省略公知的特征和技术的细节,以避免不必要地模糊所呈现的实施例。
为了下文描述的目的,诸如“上”、“下”、“右”、“左”、“垂直”、“水平”、“顶部”、“底部”及其派生词等术语应当涉及如附图中取向的所公开的结构和方法。诸如“在……上方”、“在……以上”、“在……顶部”、“在……之上”、“位于……上”或“位于……顶部”等术语意味着指第一元件(诸如第一结构)存在于第二元件(诸如第二结构)上,其中诸如界面结构的中间元件可存在于第一元件和第二元件之间。术语"直接接触"是指第一元件(例如第一结构)和第二元件(例如第二结构)在两个元件的界面处没有任何中间导电、绝缘或半导体层的情况下连接。术语“基本上”或“基本上类似”是指其中长度、高度或取向的差异在明确叙述(例如,短语没有基本上类似的术语)和基本上类似的变化之间无实际差异的情况。在一个实施例中,“基本”(及其派生词)表示通过类似设备的公认的工程或制造公差而产生的差异,例如,值偏差最大为10%或角度偏差最大为10°。
为了不模糊本发明的实施例的呈现,在以下详细描述中,本领域已知的一些处理步骤或操作可能已经被组合在一起以用于呈现和用于说明目的,并且在一些实例中,可能没有被详细描述。在其他情况下,可能根本不描述本领域已知的一些处理步骤或操作。应当理解,下面的描述更集中于本发明的各种实施例的区别特征或元件。
根据实施例,在量子计算中,可以使用量子位电路,而不是传统的集成电路。在量子位电路中,在制造或操作之后改变特定量子位的频率可能是有用的。在实施例中,如本文所述,频率调谐可使用聚焦退火来实现,例如通过使用激光束或聚焦离子束。出于各种原因,聚焦退火(即,量子位的频率的调谐)可以在包含量子位的芯片被制造之后执行。制造的结构可以是倒装芯片,其可以包括彼此堆叠的两个或更多个芯片,并且可以例如通过焊料凸块电连接。倒装芯片可以包含顶部芯片和底部芯片。底部芯片可以包含一个或多个量子位并且被称为量子位芯片,并且顶部芯片可以包含输入/输出电路并且被称为I/O芯片。
由顶部上的I/O芯片和底部上的量子位芯片构造的倒装芯片可能使量子位对于聚焦激光退火是不可访问的。因此,顶部芯片中的窗口或其他一个或多个光学透射路径可以有助于使用聚焦退火来访问量子位以进行频率调谐。光学透射路径是任何光谱(例如,红外、可见、紫外)的光可以透射通过的孔径或路径。根据本发明的实施例,顶部芯片可以以本文描述的几种方式设计,以提供对底部芯片中的量子位的光学访问。
量子位倒装芯片组件可以通过将包括I/O芯片的芯片附接到包含一个或多个量子位的量子位芯片上来制造。I/O芯片和量子位芯片可以使用多个焊料凸块彼此附接。如本文所讨论的,可以在I/O芯片中创建光学透射路径。该路径可以使用本文描述的各种技术来创建。可以创建该路径,使得它与对应的量子位对准,由此提供对该对应量子位的光学访问。该路径可以具有孔径,该孔径具有足够大的直径以允许对量子位进行足够访问以进行量子位的处理(例如,用于频率调谐的激光退火、溅射、离子蚀刻、或其他处理)。在多个实施方案中,量子位芯片中的光学透明衬底可以允许从芯片组件的背侧处理量子位。在实施例中,透明衬底是氧化镁(MgO)。
在创建量子计算系统中采用多量子比特芯片。然而,添加到芯片的每个附加量子位增加了芯片的设计复杂性,因为量子位可以基于其谐振频率而与其他邻近量子位具有量子相互作用。这种行为构成了被称为"频率冲突"的故障模式。频率冲突可以通过量子力学系统的建模来预测。当两个邻近量子位的谐振频率相似时(例如,当一个量子位的频率等于另一个量子位的频率时),发生频率冲突的非限制性实例。为了实现高性能,希望能够非常精确地设置每个量子位的频率。传统上,已经使用可调磁场来移位量子位的频率,但是必要的调谐电路往往会引入噪声并且在多量子位系统中增加额外的复杂性。
在本发明的示例性实施例中,量子位包括以下特性:在测量过程中,量子位被投影到两个不同状态(|A>或|B>)之一。当两个状态|A>和|B>稳定时,发生读出,之后量子位去相干。读出谐振器基于所投影的量子位的状态获得谐振频率。
可以基于读出的谐振器频率来推断量子位的投影状态,可以基于读出谐振器的反射或透射系数来确定所述读出的谐振器频率。这可以通过各种技术来实现。在示例技术中,根据一个示例实施例,微波信号被施加到电路的输入,并且被调谐到近似等于测量后准稳定状态之一的谐振频率的频率。当量子位被投影到测量状态时,所施加的微波信号要么传输到输出要么由读出谐振器反射,这取决于量子位到传输线的耦合。因此,取决于量子位状态,微波信号将获得特定的幅度和相位。从这个信号确定量子位状态可以以多种方式完成,例如,使用IQ混频器、阈值检测器等等。也可以使用其他各种用于测量频率或状态的方法。
在一些情况下,可能需要诸如SQUID放大器或HEMT放大器等附加放大器、以及诸如IQ混频器的室温微波电子器件等。
现在参考图1,示出了根据本发明的实施例的量子位300。在一些实施方案中,量子位300包含彼此并联连接的约瑟夫逊结302以及电容器304,如图1所示。并联约瑟夫逊结302和电容器304布置通过耦合电容器310电容耦合到结构306,以及通过耦合电容器320电容耦合到地。虽然仅示出了电容耦合到约瑟夫逊结302和电容器304的单个结构,但是多个结构可以附接到所描绘的并联约瑟夫逊结302和电容器304的布置上。例如,读出结构和到其他量子位结构的互连可以各自被电容性地连接到并联的约瑟夫逊结302和电容器304布置上。另外,虽然量子位300被描绘为使用了耦连电容器310和耦连电容器320,但是可以使用其他的电连接量子位的方法。根据一个示例实施例,电容器304在0.1毫微法(fF)到200毫微法(fF)的范围内。根据一个示例性实施例,约瑟夫逊结302具有范围从10纳安至100纳安的有效临界电流。在达到由Ambegaokar-Baratoff关系所预测的超导状态之前,临界电流与约瑟夫逊结的整体电阻有关。更具体地说,该关系预测,在达到超导状态之前的约瑟夫逊结的电阻与在转向超导之后的临界电流成反比。此外,该临界电流还与约瑟夫逊结的电感成反比。
结果,量子位的谐振频率范围大约在几百MHz到大约20GHz之间。量子位的耦合电容器310可以被设计用于高保真度读出。在该示例性实施例中描述的量子位也被称为单结跨子(transmon)量子位。这种量子位不易于使用磁场调谐,因此其谐振频率由制造时形成的电容器和结的参数固定。其他实施方案可以利用另一种类型的量子位(例如,相位量子位、电荷量子位)。在其他实施例中,被布置为串联或并联电路元件的两个或更多个约瑟夫逊结可以替代图1中所描绘的单个约瑟夫逊结302。
现在参考图2,示出了根据本发明的实施例,在衬底400上制造之后图1中描述的电容性耦合量子位的实施例的示例性布局。约瑟夫逊结402的制造可以通过例如以下各项来进行:(1)三层(超导体-绝缘体-超导体)材料叠层的减法构图,或(2)Dolan桥技术。Dolan桥技术在这里被描述为说明性示例。在这种技术中,约瑟夫逊结402在电容板404之间被图案化,其可以经由电容器410电容耦合到线406,并且经由电容器420电容耦合到地线408,所有这些都位于衬底400上。虽然仅描绘了单条线406,但是多条线可以通信地耦合到电容板404,从而将量子位400电容性地连接到多个结构上。
在图2中描绘的示例性实施方案中,其上形成量子位电路的衬底400可以是高电阻率(本征)八英寸硅晶片。在晶片上旋涂抗蚀剂的双层,例如共聚物甲基丙烯酸甲酯(MMA)层和随后的聚甲基丙烯酸甲酯(PMMA)的较薄层。使用电子束光刻,将约瑟夫逊结402的图案写入抗蚀剂中。该步骤之后是在MIBK:IPA(甲基异丁酮(MIBK)异丙醇(IPA))(1:3)溶液中显影约1分钟,其除去抗蚀剂暴露于电子束的区域。MMA层对电子束更敏感,这产生底切PMMA的区域。这样,可以在PMMA外面制造悬吊桥,也称为Dolan桥,下面没有MMA。将样品置于电子束蒸发器中,其中在Al蒸发之间以两个角度氧化(在Ar/O2气氛中)蒸发铝(Al)。在重叠区域中形成结。通过将样品置于丙酮中除去剩余的抗蚀剂和不需要的金属。使用这种剥离技术,可以制造范围从0.01μm2到1μm2的结区域。这种基本的制造工艺可以与其他额外的制造步骤一起使用,例如PECVD、光刻和RIE,以制造其他器件。在示例实施例中,使用铝作为起始化合物以形成Al/AlOx/Al结构,在硅(Si)衬底上制造约瑟夫逊结402。在示例实施例中,选择衬底400以减小低温下的介电损耗角正切。衬底400也可以选择为一种材料,该材料可以相对于用于约瑟夫逊结402的超导和介电材料被选择性地蚀刻。例如,可以实现高电阻率硅(Si)晶片。
在图2所示的示例性实施例中,电容板404可包括超导材料,例如Nb、NbN、NbCN、NbTiN和Pb。在示例性实施例中,电容板404可以分开大约1至100微米。在示例实施例中,电容板404可以具有从衬底400的表面起约5至约500微米的宽度、约1至约200微米的长度、以及约10至约500纳米的高度。
作为制造过程的结果,所形成的量子位结构可以具有彼此基本上相似的尺寸(例如,电容板和约瑟夫逊结的大小和形状)。然而,由于在纳米水平上工艺参数不受控制,在约瑟夫逊结402的形成期间的制造条件可能导致约瑟夫逊结402的所得电阻的变化。对于在单结跨子量子位中使用的约瑟夫逊结,电阻的这种变化可以是+/-2%。结电阻的变化引入量子位频率的相应变化。例如,在单结跨子量子位中,结电阻的+/-2%的变化导致量子位的频率的-/+1%的变化。根据图3,可以执行退火以调整约瑟夫逊结402的电阻,以便与最初希望的电阻对准,从而减小与另一个量子位的频率冲突的概率。
参考图3,量子位500可以被退火以调整约瑟夫逊结402的电阻,以便调整量子位的频率。约瑟夫逊结402的退火可以包括加热约瑟夫逊结402以允许在约瑟夫逊结402内发生物理变化,这导致电阻的变化。在约瑟夫逊结402的退火中,低于阈值剂量的退火可以导致约瑟夫逊结402的电阻的增加,而高于该阈值的退火可以减小约瑟夫逊结402的电阻。在一个实施例中,约瑟夫逊结402的退火可以通过经由热源520的激光退火来完成,这可以使得能够对约瑟夫逊结402进行局部加热。在示例性实施例中,激光退火可以使用发射波长为532nm的激光的加倍的Nd:YAG源来执行。然而,可以使用或测试各种其他波长的光来确定移位量子位的频率的最佳路径。在示例性实施例中,阈值剂量可以是持续10秒的大约1.4W。因此,在该示例性实施例中,以低于1.4W的剂量对约瑟夫逊结402进行10秒的退火将导致电阻的增大,而以高于1.4W的剂量进行10秒的退火将导致电阻的减小。基于实施例的方法,可测试退火的功率、光频率和持续时间以确定和调节以实现针对给定条件集合的适当频率偏移。
图4描绘了根据实施例的芯片组件的俯视图的示例图。顶部芯片502可以具有对准标记504。图5描绘了在形成通孔506之后的倒装芯片组件500的俯视图的示例图。在实施例中,图4和图5中的每一个的倒装芯片组件8500可以是在使用例如高功率激光束钻出光学透射路径(例如,通孔)之前和之后的相同芯片组件的俯视图。类似地,图4和图5中的芯片502可以分别表示在钻通孔之前和之后的顶部芯片(即,从俯视图可见的唯一芯片),其可以是芯片组件的I/O芯片。
在实施例中,顶部芯片502可以由硅制成。如这里所述,顶部或I/O芯片也可以由透明材料制成,例如蓝宝石,从而消除对芯片502中存在的通孔506的需要。如果材料允许足够的光穿过该材料以进行所需的处理(例如,激光退火),则该材料是透明的。在实施例中,对准标记504可以制作在硅芯片502上。该标记可以用作工具,以指示激光钻孔的正确位置和方位。在形成通孔506之后,图4的对准标记504可以是与图5的对准标记504相同的对准标记。在实施例中,通孔506的形成包括从芯片去除材料的一部分,从而产生穿过芯片的孔。在示例性实施例中,可以使用激光钻孔、机械钻孔或化学蚀刻(如图8A-F和图9A-F中所述)来执行通孔的形成。如图5所示,在形成通孔506之后,可以保留对准标记504的一部分。在实施例中,通孔可具有高达100微米的直径。在实施方案中,通孔可以具有足够大的直径以允许进一步访问或处理倒装芯片组件500的量子位芯片上的一个或多个量子位。
图6描绘了根据实施例的已经被修改以允许量子位处理的倒装芯片组件500的截面视图。在实施例中,倒装芯片制造可以在图4和图5所示的通孔形成之前或之后进行。倒装芯片组件500是图4和图5的倒装芯片组件500的截面图。如这里所讨论的,倒装芯片组件500包括顶部或I/O芯片502和底部或量子位芯片503。I/O芯片502和量子位芯片503通过多个焊料凸块(包括焊料凸块510A和焊料凸块510B,统称为焊料凸块510)连接。在实施例中,根据已知方法,可以使用多个焊料凸块来连接两个芯片以形成3D芯片组件500。3D组件可以包括物理地堆叠一个或多个部件(例如,顶部或I/O芯片502和底部或量子位芯片503)并且施加温度和压力以使焊料凸块510回流并且在这两个部件之间形成机电连接。在实施例中,可以使用诸如倒装芯片接合器等的热压缩工具来施加温度和压力,从而形成焊料凸块连接。
在实施例中,可能需要回流。常见的无铅焊料凸块的回流温度可在约230℃到约260℃的范围内,且用于热压缩工具中的温度可在约230℃到约400℃的范围内。热压缩工具的所施加温度可取决于互连材料和芯片大小。在使用热压缩工具的3D组装期间,可以施加范围6.0×104Pa到约6.0×105Pa的压力,尽管可以基于接触面积和待互连的材料来调整该压力。在一个实施例中,可以施加范围从约5N到约50N的力。该力也可以基于接触面积和待互连的材料来调节。在一些情况下,在组件之间可以存在1,000至170,000之间的焊料凸块连接。
在一些实施例中,焊料凸块510可以包括一种或多种超导材料,例如铟。在多个实施例中,量子位芯片可以包含一个或多个约瑟夫逊结508。
如图7中所描绘的,通孔506(其是光学透射路径)与约瑟夫逊结508对准以提供对约瑟夫逊结508的访问,例如,以使得能够通过激光或其他量子位处理技术进行处理。图6-图7的倒装芯片组件500的约瑟夫逊结508可以接受激光束512的处理,例如,以对约瑟夫逊结508进行退火。在实施例中,通孔506可以被设计成允许激光束治疗,如上所述,但这不是必须限制为仅提供访问以用于通过激光束512进行处理。例如,通孔506可以被配置成提供到约瑟夫逊结508的访问以用于物理处理(例如,聚焦离子束处理、溅射)或其他处理。因此,虽然该路径被描述为"光学透射的",但是应当注意,该路径可以是光学透射的,并且还可以是物理、电学或其他方式透射的,因此提供了约瑟夫逊结508的各种处理。
在多个实施例中,约瑟夫逊结508可以是超导量子位的一部分。每个这样的量子位可以包括至少一个约瑟夫逊结(例如约瑟夫逊结508)、以及或多个电容器。在多个实施例中,通孔506(或其他光学透射路径)可以被对准以便提供对约瑟夫逊结(如以上所描述的)、对量子位的电容器、或对量子位的另一个部件的访问。
在实施例中,如图7所示,激光束512可以用于通过通孔506处理约瑟夫逊结508。如图所示,通孔506足够宽,以允许通过例如激光束512访问约瑟夫逊结508。另外地或替代地,通孔506可以用于访问约瑟夫逊结508,以进行化学或机械处理,例如蚀刻、沉积或抛光步骤。如在此所讨论的,激光束512可以用于对量子位内的约瑟夫逊结进行退火。
图8A-图8F描绘了根据本文所述的方法在倒装芯片组件的I/O芯片900(例如,顶部芯片、第一芯片)中形成光学透射路径。图8A-图8F的示意流程描绘了在光学透射路径(例如,通孔)的不同制造阶段的I/O芯片900。图8A-图8F中的蚀刻可使用四甲基氢氧化铵(TMAH)蚀刻来完成。图8A描绘了I/O芯片900。I/O芯片900可以由硅构成。在其他实施例中,I/O芯片900也可以包含其他元件,包括可以存在于典型芯片中的那些元件。在实施例中,I/O芯片900可以是倒装芯片组件的一部分。在实施例中,I/O芯片900可以是图4-图7中描绘的I/O(例如,顶部)芯片502。I/O芯片900可以在化学蚀刻工艺中例如使用TMAH蚀刻来经历一系列步骤。
在图8A中,芯片衬底901可以具有分别位于顶表面和底表面上的两个氧化物层,第一氧化物层902A和第二氧化物层902B(统称为氧化物层902),其可以根据已知方法形成。氧化物层902(即,图8A-图8E中的氧化物层902)可以用作硬掩模、蚀刻停止和光刻实现器。在图8B中,可以蚀刻第一氧化物层902A。使用光刻法,可以限定蚀刻孔,如附加抗蚀剂层(例如,光致抗蚀剂(photoresist)904)中的间隔所示,其也可以在蚀刻期间被去除。每个通孔906(图8C-8F中所示)在其最窄点处的直径可以高达100微米。
在图8C中,可以在芯片衬底901中产生通孔906。如所描绘的,可以在芯片衬底901中产生通孔906(图8C-8F中描绘的)。在实施例中,可在使用TMAH蚀刻的穿硅蚀刻之后的先前步骤期间移除如图8B处的I/O芯片900中所描绘的光致抗蚀剂904。在实施例中,TMAH蚀刻可以成圆锥形地去除材料,从而产生截头圆锥形通孔,并且可以允许处理下面的量子位,诸如将期望的激光功率递送到量子位。如图8D所示,顶面上的第一氧化物层902A可通过额外的氧化物等离子体或化学蚀刻去除。在图8D中,I/O芯片900被倒置。第二氧化物层902B的邻近于通孔906中的每个通孔的部分可使用光刻来图案化且用氧化物蚀刻来蚀刻。具有抗蚀剂保护的氧化物蚀刻可以是干蚀刻或氢氟酸(HF)蒸气蚀刻。在实施例中,HF气相(vapor)蚀刻可一次蚀刻晶片的两面。在实施例中,HF气相蚀刻的使用可允许在晶片的蚀刻孔的顶部上保留第二氧化物层902B(例如,以允许进一步的光刻处理)。在实施例中,对于较大孔,可使用拉伸化学计量氮化硅层。
在图8E中,可以在芯片900的顶表面上形成用于微波谐振器电路系统的超导图案908。然后,使用光刻法,可以限定微波谐振器,接着进行金属的剥离/RIE(反应离子蚀刻)蚀刻。超导图案908可以包括铝、铌或通过诸如溅射、蒸发或原子层沉积的常规方式沉积的任何其他超导材料。图8E所示的步骤还可导致沉积在剩余的第二氧化物层902B顶部的金属(例如超导图案908)的去除。
在图8F中,可以执行使用氧化物特定的蚀刻化学剂的氧化物的干法蚀刻,例如HF气相蚀刻。在实施例中,当蚀刻是氧化物特定的时,图案保护可以是不必要的。在其他实施例中,可以在氧化物周围使用图案抗蚀剂(例如,以覆盖超导图案908)。这样,氧化物可以暴露于蚀刻,而光致抗蚀剂可以保护超导图案908。此时,用于微波谐振器电路的超导图案908可以保留在图8F的芯片衬底901上。芯片900可以凸块接合到另一芯片,例如量子位芯片,如本文所述。
图9A-图9F描述了根据这里描述的方法(例如Bosch蚀刻),在倒装芯片组件的顶部芯片1000(例如I/O芯片)中形成光学透射路径。图9A-图9F的示意流程图示出了在光学透射路径(例如,通孔)的不同制造阶段的顶部芯片1000。图9A描述了顶部芯片1000。顶部芯片1000可以由硅构成。在其他实施例中,顶部芯片1000还可以包含其他元件,包括可以存在于典型芯片中的那些元件。在实施例中,顶部芯片1000可以是倒装芯片组件的一部分,例如I/O芯片。图9A-图9F所示的顶部芯片1000可以在化学蚀刻工艺中,例如使用Bosch蚀刻,经历一系列步骤。
衬底1001可以具有第一氧化物层1002A和第二氧化物层1002B(统称为氧化物层1002),它们位于衬底1001的顶表面和底表面上,并且根据已知方法形成。氧化物层1002可以用作硬掩模、蚀刻停止和/或光刻实现器。第一氧化物层1002A的部分可以被蚀刻以将如图9A所示的顶部芯片1000过渡到如图9B所示的顶部芯片1000。使用光刻法,可限定蚀刻孔1003;蚀刻孔1003可进一步由附加的抗蚀剂层(例如,光致抗蚀剂1004)限定,其也可在蚀刻之前沉积并在蚀刻期间去除。每个蚀刻孔1003的直径可以高达100微米。
在图9C中,根据实施例,可在衬底1001中进行硅蚀刻。如图所示,通孔1006(例如,图9C-图9F中所示的通孔1006)可在衬底1001中形成。在实施例中,图9B所示的光致抗蚀剂1004可在通孔1006形成之前或之后去除。然而,在去除光致抗蚀剂1004之前进行Bosch蚀刻可能在去除光致抗蚀剂1004时产生更多困难。在实施例中,Bosch蚀刻去除圆柱形形状的材料,并且可能需要比另一蚀刻(例如TMAH蚀刻)更高的功率,以向样品提供期望的激光功率,这取决于例如退火处理中的透镜焦距和晶片厚度,这是由于与TMAH蚀刻相比更高的纵横比(比TMAH锥度更小)。第一氧化物层1002A可通过额外的氧化物等离子体或化学蚀刻去除。在图9D中,根据实施例,可以将顶部芯片1000倒置,并且可以使用光刻法在每个蚀刻孔周围对第二氧化物层1002B进行图案化,随后对蚀刻孔周围的第二氧化物层1002B进行氧化物蚀刻。具有抗蚀剂保护的氧化物蚀刻可以是干蚀刻或氢氟酸(HF)气相蚀刻。在实施例中,HF气相蚀刻可同时蚀刻晶片的两面。在实施例中,使用此HF气相蚀刻可允许在晶片的蚀刻孔的顶部上保留第二氧化物层1002B(例如,以允许进一步的光刻处理)。在实施例中,对于较大孔,可使用拉伸化学计量氮化硅层。
在图9E中,根据实施例,可以在芯片1000的表面上形成用于微波谐振器电路系统的超导图案1008。然后,使用光刻法,可以限定微波谐振器,接着进行金属的剥离/RIE(反应离子蚀刻)蚀刻。超导图案1008可以包括铝、铌或通过诸如溅射、蒸发或原子层沉积的常规方式沉积的任何其他超导材料。除了形成超导图案1008之外,图9E所示的步骤还可导致去除剩余氧化物802顶部上的金属(例如,超导图案1008)。
在图9F,根据实施例,可以在顶部芯片1000上执行使用氧化物特定蚀刻化学物质的氧化物干法蚀刻,例如HF气相蚀刻。此时,用于微波谐振器电路的超导图案1008可以保留在衬底1001上,并且芯片可以随后被接合到另一芯片,例如量子位芯片,如本文所述。
图10描绘了根据实施例的用于形成量子位倒装芯片组件的示例方法1100的流程图。如本文所述,方法1100可以在I/O芯片中创建一个或多个光学透射通道时开始。如在此所描述的,这些光学透射通道可以是通孔或其他光学透射路径,该光学透射路径提供了对该芯片的量子位(例如,该量子位的一个特定的约瑟夫逊结)的光学访问、物理访问、或其他访问。可以如本文所述产生光学透射通道(例如,通孔)。在创建通道之后,I/O芯片可以被附接到量子位芯片(1104)。在实施例中,可以使用例如多个焊料凸块来附接芯片以组装倒装芯片。在实施例中,该I/O芯片可以包含I/O电路,并且该量子位芯片可以包含一个或多个量子位,如在此描述的。在实施例中,操作1102和操作1104可以相对于彼此以任一顺序发生,或者具有在I/O芯片和量子位芯片的附接之前或之后创建的通道。
通过遵循上述步骤,形成具有紧固到量子位芯片的I/O芯片的结构。I/O芯片具有位于量子位芯片的一个或多个量子位上方的一个或多个光学透明路径。光学透明路径可以是通孔,或者可以是透明材料。I/O芯片可以包含位于I/O芯片的顶表面和/或底表面上的超导电路。I/O芯片可以通过多个焊料凸块或者替代地通过将两个芯片化学或机械地紧固在一起的其他手段连接到量子位芯片。
已经出于说明的目的给出了本发明的各种实施例的描述,但是其不旨在是穷尽的或限于所公开的实施例。在不背离所描述的实施例的范围和精神的情况下,许多修改和变化对于本领域的普通技术人员将是显而易见的。选择本文所使用的术语是为了最好地解释实施例的原理、实际应用或对市场上存在的技术改进,或为了使本领域的其他普通技术人员能够理解本文所公开的实施例。因此,本发明不局限于所描述和说明的确切形式和细节,而是落入所附权利要求的范围内。
Claims (18)
1.一种用于形成量子位倒装芯片组件的方法,所述方法包括:
在第一芯片上形成量子位;
在第二芯片中形成光学透射路径;
将所述第一芯片接合到所述第二芯片;以及
通过穿过所述光学透射路径对所述第一芯片的与所述第二芯片相对的表面施加激光来对所述量子位进行激光退火;以及
其中所述光学透射路径位于所述量子位之上。
2.根据权利要求1所述的方法,其中所述路径具有孔径,所述孔径的直径足够大以允许对所述量子位的处理。
3.根据权利要求1所述的方法,其中所述光学透射路径具有100微米或更小的孔径。
4.根据权利要求1所述的方法,还包括离子蚀刻所述量子位。
5.根据权利要求1所述的方法,其中形成所述光学透射路径包括使用高功率激光束来对所述第二芯片进行钻口以在所述第二芯片中形成通孔。
6.根据权利要求1所述的方法,其中形成所述光学透射路径包括在所述第二芯片中蚀刻通孔。
7.根据权利要求6所述的方法,其中所述蚀刻包括深反应离子蚀刻。
8.根据权利要求6所述的方法,其中所述蚀刻包括化学蚀刻,并且其中所述化学蚀刻是四甲基氢氧化铵(TMAH)蚀刻。
9.根据权利要求1所述的方法,其中所述第二芯片包括透明衬底。
10.根据权利要求9所述的方法,其中所述透明衬底是氧化镁(MgO)。
11.一种倒装芯片设备,包括:
包括量子位的第一芯片;
接合到所述第一芯片的第二芯片,其中所述第一芯片和所述第二芯片通过多个焊料凸块结合;以及
其中所述第二芯片中的光学透射路径提供对所述第一芯片上的所述量子位的光学访问,其中所述量子位可访问以用于经由所述光学透射路径进行激光退火。
12.根据权利要求11所述的设备,其中所述第二芯片包括透明衬底。
13.根据权利要求12所述的设备,其中所述透明衬底为蓝宝石。
14.根据权利要求11所述的设备,其中所述光学透射路径具有的直径足够大以允许对所述多个量子位中的一个或多个量子位的处理。
15.根据权利要求11所述的设备,其中所述第二芯片的所述光学透射路径与所述第一芯片上的所述量子位对准。
16.根据权利要求11所述的设备,其中所述光学透射路径是用化学蚀刻形成的。
17.根据权利要求11所述的设备,其中所述光学透射路径是使用高功率激光束形成的。
18.根据权利要求11所述的设备,其中所述第一芯片包括透明衬底。
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