WO2018160184A1

WO2018160184A1 - Grounded coplanar waveguide transmission line structures for qubits

Info

Publication number: WO2018160184A1
Application number: PCT/US2017/020561
Authority: WO
Inventors: Jeanette M. Roberts; Stefano Pellerano; James S. Clarke; Adel A. ELSHERBINI; Roman CAUDILLO; Zachary R. YOSCOVITS; David J. Michalak; Ravi Pillarisetty; Hubert C. GEORGE; Nicole K. THOMAS; Kanwaljit SINGH
Original assignee: Intel Corporation
Priority date: 2017-03-03
Filing date: 2017-03-03
Publication date: 2018-09-07

Abstract

Described herein are new transmission line structures for use as resonators and non-resonant transmission lines in quantum circuits. In one aspect of the present disclosure, a proposed structure includes a lower ground plane structure disposed over or in the substrate, a dielectric layer disposed over the lower ground plane structure, a first and a second upper ground plane structures disposed over the dielectric layer and electrically connected to the lower ground plane structure, and a signal line structure disposed over the dielectric layer, between the first and the second upper ground plane structures. Transmission line structures as proposed herein could be used for providing microwave connectivity to, from, or/and between the qubits, or to control the qubits. Methods for fabricating such structures are disclosed as well.

Description

GROUNDED COPLANAR WAVEGUIDE TRANSMISSION LINE STRUCTURES FOR QUBITS

Technical Field

[0001] This disclosure relates generally to the field of quantum computing, and more specifically, to transmission line structures for use in qubit devices and methods of fabrication thereof.

Background

[0002] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

Brief Description of the Drawings

[0003] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0004] FIG. 1 provides a schematic illustration of an example quantum circuit, according to some embodiments of the present disclosure.

[0005] FIGS. 2A and 2B provide a schematic illustration of a conventional coplanar waveguide provided over a substrate.

[0006] FIGS. 3A and 3B provide a schematic illustration of a grounded coplanar waveguide provided over a substrate, according to some embodiments of the present disclosure.

[0007] FIGS. 4A-4H provide a schematic illustration of fabricating grounded coplanar waveguide transmission lines for qubits using metal deposition and patterning, according to some embodiments of the present disclosure.

[0008] FIG. 5 provides a flow chart of a method for fabricating grounded coplanar waveguide transmission lines for qubits using metal deposition and patterning, according to some embodiments of the present disclosure.

[0009] FIGS. 6A-6F provide a schematic illustration of fabricating grounded coplanar waveguide transmission lines for qubits using dopant implantation and epitaxial growth, according to some embodiments of the present disclosure.

[0010] FIG. 7 provides a flow chart of a method for fabricating grounded coplanar waveguide transmission lines for qubits using dopant implantation and epitaxial growth, according to some embodiments of the present disclosure. [0011] FIG. 8 provides a schematic illustration of an exemplary TEM/SEM image of a grounded coplanar waveguide transmission line in a quantum circuit, according to some embodiments of the present disclosure.

[0012] FIGS. 9A and 9B are top views of a wafer and dies that may include one or more of grounded coplanar waveguide transmission lines disclosed herein.

[0013] FIG. 10 is a cross-sectional side view of a device assembly that may include one or more of grounded coplanar waveguide transmission lines disclosed herein.

[0014] FIG. 11 is a block diagram of an example quantum computing device that may include one or more of grounded coplanar waveguide transmission lines disclosed herein, in accordance with various embodiments.

Detailed Description

Overview

[0015] As previously described herein, quantum computing, or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. One example of quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states. Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole. Yet another example of quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).

[0016] Put simply, superposition postulates that a given particle can be simultaneously in two states, entanglement postulates that two particles can be related in that they are able to instantly coordinate their states irrespective of the distance between them in space and time, and collapse postulates that when one observes a particle, one unavoidably changes the state of the particle and its' entanglement with other particles. These unique phenomena make manipulation of data in quantum computers significantly different from that of classical computers (i.e. computers that use phenomena of classical physics). Classical computers encode data into binary values, commonly referred to as bits. At any given time, a bit is always in only one of two states - it is either 0 or 1. Quantum computers use so-called quantum bits, referred to as qubits (both terms "bits" and "qubits" often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states. Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.

[0017] Compared to well-established and thoroughly researched classical computers, quantum computing is still in its infancy, with the highest number of qubits in a solid-state quantum processor currently being about 10. One of the main challenges resides in protecting qubits from decoherence so that they can stay in their information-holding states long enough to perform the necessary calculations and read out the results. For this reason, materials, structures, and fabrication methods used for building quantum circuits continuously focus on reducing spurious (i.e. unintentional and undesirable) two-level systems (TLS's), thought to be one of the dominant sources of qubit decoherence. In general, as used in quantum mechanics, a two-level (also referred to as "two- state") system is a system that can exist in any quantum superposition of two independent and physically distinguishable quantum states. Another challenge that is unique to quantum computing is the ability to provide substantially lossless connectivity between qubits at very low powers, e.g. as low as a power of a single photon that may be present in a particular resonator interconnecting two qubits.

[0018] As the foregoing illustrates, ability to manipulate and read out quantum states, making quantum-mechanical phenomena visible and traceable, and ability to deal with and improve on the fragility of quantum states of a qubit present unique challenges not found in classical computers. These challenges explain why so many current efforts of the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits. Physical systems for implementing qubits that have been explored until now include e.g. superconducting qubits, quantum dot qubits (e.g. Silicon (Si) quantum dot qubits), single trapped ion qubits, photon polarization qubits, etc.

[0019] Quantum circuits based on various physical systems for implementing qubits use microwaves to control the qubits, for example to initialize, manipulate (e.g. couple), and readout the qubits. The microwaves are generally delivered and supported using transmission line structures. In particular, microwave transmission lines used in quantum circuits can be either resonant (sometimes referred to as "resonators") or non-resonant, sometimes referred to, together, as "microwave elements." In order to provide substantially lossless connectivity to, from, and between the qubits, electrically conductive portions of such microwave elements are typically made from

superconducting materials. Conventionally, microwave transmission lines in quantum circuits have been implemented as coplanar waveguides (CPWs).

[0020] Inventors of the present disclosure realized that, when used in quantum circuits, employing a conventional CPW architecture may have drawbacks.

[0021] Embodiments of the present disclosure propose a new transmission line structure for use as resonators, as well as for use as non-resonant transmission line interconnects, in quantum circuits. Fabrication techniques for forming such a structure are also disclosed.

[0022] In one aspect of the present disclosure, a proposed transmission line structure for qubits includes a lower ground plane structure disposed over or in the substrate, a dielectric layer disposed over the lower ground plane structure, a first and a second upper ground plane structures disposed over the dielectric layer and electrically connected to the lower ground plane structure, and a conductor strip structure (i.e. a strip of a conductive material, preferably a superconductive material) disposed over the dielectric layer, between the first and the second upper ground plane structures. Such a transmission line structure may be referred to as a "grounded CPW line" or simply as a "grounded CPW" (GCPW). In the following, "transmission line structure," "lower/upper ground plane structure," and "conductor strip structure" may be referred to without using the word "structure." Furthermore, the term "conductor strip" may be used interchangeably with the terms such as "signal line," "signal path," or "center line" as known in microwave engineering.

[0023] In general, transmission line structures as proposed herein could be used for providing microwave connectivity to, from, or/and between the qubits, or to set the frequencies that address individual qubits.

[0024] In order to provide substantially lossless connectivity to, from, and between the qubits, some or all of the electrically conductive portions of qubit devices/assemblies proposed herein, i.e. signal lines, ground planes, electrodes, etc., may be made from one or more superconducting materials. However, some or all of these electrically conductive portions could be made from electrically conductive materials which are not superconducting. In the following, unless specified otherwise, reference to an electrically conductive material implies that a superconducting material can be used. Furthermore, materials described herein as "superconducting materials" may refer to materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions (e.g. materials which exhibit superconducting behavior at very low

temperatures at which qubits typically operate, but which may not exhibit such behavior at e.g. room temperatures). [0025] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0026] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0027] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0028] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0029] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art.

Furthermore, as used herein, terms indicating what may be considered an idealized behavior, such as e.g. "superconducting" or "lossless", are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of non-zero electrical resistance or non-zero amount of spurious two-level systems (TLS's) may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms. Specific values associated with an acceptable level of loss are expected to change over time as fabrication precision will improve and as fault-tolerant schemes may become more tolerant of higher losses, all of which are within the scope of the present disclosure.

[0030] Still further, while the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are operated at. In addition, techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 gigahertz (GHz) range, e.g. 5-8 GHz range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering. However, advantageously, because excitation energy of qubits is controlled by the circuit elements, qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.

Quantum computing and grounded CPW transmission lines

[0031] FIG. 1 provides a schematic illustration of a quantum circuit 100 that may include any of the transmission lines described herein, according to some embodiments of the present disclosure. As shown in FIG. 1, an exemplary quantum circuit 100 includes a plurality of qubits 102. The qubits 102 may be implemented as any of the suitable qubits, such as e.g. superconducting qubits (e.g.

transmons), quantum dot qubits, or quantum well qubits.

[0032] As shown in FIG. 1, the quantum circuit 100 typically includes substantially non-resonant transmission lines 104 for providing microwave signals to different quantum circuit elements and components, such as e.g. various control lines for various qubits. For example, for superconducting qubits, examples of the non-resonant transmission lines 104 include flux bias lines, microwave lines, and drive lines. In another example, for quantum dot qubits, examples of the non-resonant transmission lines 104 include lines that may control microwave pulses applied to gates and/or the doped regions of quantum dot device(s) in order to control spins of charge carriers in quantum dots formed in such device(s) or microwave pulses transmitted over a conductive pathway to induce a magnetic field in magnet line(s) of quantum dot devices. [0033] In some embodiments, e.g. when the qubits 102 are superconducting qubits, in addition to the non-resonant transmission lines 104, the quantum circuit 100 may also include a plurality of resonant microwave elements commonly referred to as "resonators," shown in FIG. 1 as resonators 106, e.g. coupling and readout resonators used in quantum circuits which employ superconducting qubits.

[0034] In general, a resonator of a quantum circuit differs from a non-resonant microwave transmission line in that a resonator is a transmission line that is deliberately designed to support resonant oscillations (i.e. resonance) within the line, under certain conditions. In contrast, non- resonant transmission lines may be similar to conventional microwave transmission lines in that they are designed to avoid resonances, especially resonances at frequencies/wavelengths close to the resonant frequencies/wavelengths of any resonators in the proximity of such non-resonant lines. Once non-resonant transmission lines are manufactured, some of them may inadvertently support some resonances, but, during its design, efforts are taken to minimize resonances, standing waves, and reflected signals as much as possible, so that all of the signals can be transmitted through these lines without, or with as little resonance as possible. For example, the ends of non-resonant transmission lines are typically engineered to have a specific impedance (e.g. substantially 50 Ohm) to minimize impedance mismatches to other circuit elements to which the lines are connected, in order to minimize the amount of reflected signal at transitions (e.g., transitions from the chip to the package, the package to the connector, etc.).

[0035] A resonator is made with fixed boundary conditions, and these boundary conditions control the frequencies/wavelengths which will resonate within a given transmission line structure used to implement a resonator. In order to satisfy boundary conditions for resonance, each end of a transmission line that implements a resonator can be either a node, if it is shorted to ground (e.g. by being electrically connected to a ground plane of a transmission line structure that implements the resonator, or to any other ground potential), or an antinode, if it is capacitively or inductively coupled to another quantum circuit element. Thus, resonators 106 differ from non-resonant microwave transmission lines 104 in how these lines are terminated. A line used to route a signal on a substrate, i.e. one of the non-resonant transmission lines 104, typically extends from a specific source, e.g. a bonding pad or another type of electrical connection to a source, to a specific load (e.g. a short circuit proximate to a quantum dot device or another bonding pad or another electrical connection to a load). In other words, non-resonant transmission lines 104 terminate with direct electrical connections to sources and loads. On the other hand, a transmission line resonator is typically composed of a piece of transmission line terminated with an open or short circuit. In this case, for a desired resonant frequency, transmission line length may e.g. be a multiple of a microwave wavelength divided by 4. However, other terminations are possible, for example capacitive or inductive, and in this case the required line length to support resonance will be different from that identified above. For example, capacitive terminations may be used for resonators which are coupled to a line or another resonator by capacitors.

[0036] Besides line termination by capacitive or inductive coupling or a short circuit, in order to support resonant oscillations, transmission lines of the resonators 106 need to be of a specific length that can support such oscillations. That is why, often times, resonators 106 may be laid out on a substrate longer than the actual distance would require (i.e. a non-resonant transmission line would typically be laid out to cover the distance in the most compact manner possible, e.g. without any curves, wiggles, or excess length, while a resonator may need to have curves, wiggles, and be longer than the shortest distance between the two elements the resonator is supposed to couple in order to be sufficiently long to support resonance).

[0037] One type of the resonators 106 used with superconducting qubits are so-called coupling resonators, which allow coupling different qubits together in order to realize quantum logic gates. A coupling resonator may be implemented as a microwave transmission line that includes capacitive or inductive connections to ground on both sides (e.g. a half wavelength resonator), which results in oscillations (resonance) within the transmission line. While the ends of a coupling resonator have open circuits to the ground, each side of a coupling resonator is coupled, either capacitively or inductively, to a respective (i.e. different) qubit by being in sufficient proximity to the qubit. Because each side of a coupling resonator has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator. In this manner, state of one qubit depends on the state of the other qubit, and the other way around. Thus, coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit, a necessary functionality for implementing logic gates.

[0038] Another type of the resonators 106 used with superconducting qubits are so-called readout resonators, which may be used to read the state(s) of qubits. In some embodiments, a

corresponding readout resonator may be provided for each qubit. A readout resonator is similar to a coupling resonator in that it may be implemented as a transmission line that includes a capacitive or an inductive connection to ground on one side. On the other side, a readout resonator may either have a capacitive connection to ground (for a half wavelength resonator) or may have a short circuit to the ground (for a quarter wavelength resonator), which also results in oscillations within the transmission line, with the resonant frequency of the oscillations being close to the frequency of the qubit. A readout resonator is coupled to a qubit by being in sufficient proximity to the qubit, again, either through capacitive or inductive coupling. Due to a coupling between a readout resonator and a qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, changes in the resonant frequency of the readout resonator can be read externally via connections which lead to external electronics e.g. wire or solder bonding pads.

[0039] Coupling resonators and readout resonators 106 may be considered as interconnects for supporting propagation of microwave signals in a quantum circuit. The non-resonant transmission lines 104 may also be considered as being included within a broad category of interconnects.

Further, any other connections for providing microwave or other electrical signals to different quantum circuit elements and components, such as e.g. connections between electrodes of various circuit components, or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as

interconnects. Still further, the term "interconnect" may also be used to refer to elements providing electrical interconnections to/from/between quantum circuit elements and components and non- quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit. Examples of non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.

[0040] In various embodiments, the interconnects included in a quantum circuit could have different shapes and layouts. In general, the term "line" as used herein in context of signal lines or transmission lines does not imply straight lines, unless specifically stated so. For example, some transmission lines or parts thereof (e.g. conductor strips of transmission lines) may comprise more curves, wiggles, and turns while other transmission lines or parts thereof may comprise less curves, wiggles, and turns, and some transmission lines or parts thereof may comprise substantially straight lines. In some embodiments, various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g. a bridge, bridging one interconnect over the other.

[0041] In some embodiments, materials forming the interconnects include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and/or niobium titanium nitride (NbTiN), all of which are particular types of superconductors, as well as their alloys. However, in various embodiments, other suitable superconductors as well as non-superconducting conductors may be used as well. [0042] The qubits 102, the resonators 106, and the non-resonant transmission lines 104 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1).

[0043] In various embodiments, quantum circuits such as the one shown in FIG. 1 may be used to implement components associated with a quantum integrated circuit (IC). Such components may include those that are mounted on or embedded in a quantum IC, or those connected to a quantum IC. The quantum IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the integrated circuit. The integrated circuit may be employed as part of a chipset for executing one or more related functions in a quantum system.

[0044] In various embodiments, some or all of the non-resonant transmission lines 104 shown in FIG. 1, some or all of the resonators 106 (if present), as well as, optionally, some or all of other microwave interconnects in a quantum circuit such as the quantum circuit 100 may be implemented in the form of grounded coplanar waveguide structures as proposed herein.

[0045] In order to highlight the advantages offered by novel quantum circuit transmission line structures proposed herein, it would be helpful to first explain how conventional quantum circuit microwave resonators are implemented. Even though some of the following descriptions refer to resonators, as described above, the new transmission line structures proposed herein may be used to implement not only quantum circuit resonators but also the non-resonant transmission lines. Furthermore, while references are made to microwave signals, the new transmission line structures proposed herein may be used to implement interconnects for routing non-microwave signals, e.g. DC biases, digital signals or/and various control signals that may need to be routed to, between, and around the qubits.

[0046] As mentioned above, conventionally, quantum circuit resonators have been implemented as coplanar waveguides. An example of a coplanar waveguide (CPW) is shown in FIGS. 2A and 2B providing, respectively, a perspective and a cross-section illustrations. In FIGS. 2A and 2B, a CPW includes two ground planes 204 and 208 and a signal line 206 provided in the middle, between the two ground planes. The signal line 206 and the ground planes 204 and 208 all lie in the same plane over a dielectric substrate 202. FIG. 2A indicates a height hi, which refers to the thickness of the substrate 202, a strip width Wl of the signal line 206, and slot spaces SI between the signal line 206 and each of the ground planes 204 and 208. The height hi, strip width Wl, and slot spaces SI are parameters that define characteristics of a CPW transmission line, such as e.g. impedance of the transmission line and electromagnetic field distribution. [0047] FIG. 2B illustrates exemplary electromagnetic field distribution in a CPW architecture, where curved arrows illustrate directions of an exemplary electric field. As can be seen with the electric field distributions shown in FIG. 2B, in a conventional CPW, some of the electromagnetic energy is immediately below the transmission line, i.e. within the dielectric substrate 202. This can become problematic due to electromagnetic interference (EMI), or crosstalk, between such a CPW and other conductors which may be present below such a CPW.

[0048] There are several other reasons why conventional CPW architecture may not be the most suitable architecture for implementing transmission lines in quantum circuits. One reason is that a conventional CPW architecture as shown in FIGS. 2A-2B does not allow for the fine control of electromagnetic fields and mutual inductances as needed for adequate quantum circuit

performance. Another reason is that, because a conventional CPW architecture is two-dimensional by nature, employing such a CPW in three-dimensional interconnect schemes may be challenging, and such schemes are likely to become necessary if quantum circuits are to be scaled up in order to become commercially feasible.

[0049] Embodiments of the present disclosure propose using a grounded CPW (GCPW) as a new transmission line structure for use as resonators as well as non-resonant transmission lines in quantum circuits. An example of a GCPW is shown in FIGS. 3A and 3B providing, respectively, a perspective and a cross-section illustrations. In FIGS. 3A and 3B, a GCPW 300 includes two upper ground planes 304 and 308 and a signal line 306 provided in the middle, between the two upper ground planes, similar to the ground planes 204 and 208 and the signal line 206 shown in FIGS. 2A and 2B. The signal line 306 and the ground planes 304 and 308 all lie in the same plane over a dielectric substrate 302. In addition, as shown in FIGS. 3A and 3B, the GCPW 300 further includes a lower ground plane 310 electrically connected to the upper ground planes 304 and 308 with interconnects 314 and 318, respectively. As also shown in FIGS. 3A and 3B, dielectric material 312 is enclosed between the plane of the upper ground planes 304 and 308 and the signal line 306 and the plane of the lower ground plane 310, between the interconnects 314 and 318.

[0050] FIG. 3A indicates a height Λ2, which refers to the thickness of the dielectric material 312, i.e. a distance between the upper ground planes 304/308, and the lower ground plane 310, a strip width W2 of the signal line 306, and slot spaces 52 between the signal line 306 and each of the upper ground planes 304 and 308. The height Λ2, strip width W2, and slot spaces 52 are parameters that define characteristics of a GCPW transmission line, such as e.g. impedance of the transmission line and electromagnetic field distribution. In various embodiments, the height h2 may be between 20 and 10,000 nanometers, including all values and ranges therein, e.g. between 4,000 and 7,000 or between 300 and 800 nanometers. In various embodiments, a thickness of each of the lower ground plane structure 310 and the first and the second upper ground plane structures 304 and 308 may be between 10 and 10,000 nanometers, including all values and ranges therein, e.g. between 500 and 1,500 nanometers or between 20 and 200 nanometers. In various embodiments, a thickness of the signal line 306 may also be between 10 and 10,000 nanometers, including all values and ranges therein, e.g. between 20 and 200 nanometers. In various embodiments, a distance from the signal line 306 to each of the first and the second upper ground plane structures 304 and 308 (i.e.52) may be between 100 and 100,000 nanometers, including all values and ranges therein, e.g. between 5,000 and 10,000 nanometers or between 500 and 2,000 nanometers.

[0051] FIG. 3B illustrates exemplary electromagnetic field distribution in a GCPW architecture, where, similar to FIG. 2B, curved arrows illustrate directions of an exemplary electric field. As can be seen with the electric field distributions shown in FIG. 3B, in a GCPW, the electromagnetic fields below the signal line end at the lower ground plane 310, thus eliminating or at least reducing EMI with other conductors which may be present in the vicinity of such a transmission line, particularly with other conductors present below the GCPW, as compared to a conventional CPW as shown in FIGS. 2A and 2B. In other words, having a ground plane below the signal line allows greater control over the electromagnetic fields to reduce stray electromagnetic fields and mutual inductances.

[0052] The GCPW 300 may have additional advantages over the conventional CPW as shown in FIGS. 2A and 2B.

[0053] One advantage is a unique advantage applicable only in context of quantum circuits, and stems from the fact that providing a lower ground plane below the signal line allows concentrating the electromagnetic fields generated by the signal line to be within the bulk of the dielectric material between the upper ground planes and the lower ground plane. The bulk of the dielectric material between the upper ground planes and the lower ground plane may be controlled to be a high- quality dielectic in terms of causing qubit decoherence. Concentrating electromagnetic fields in the bulk of such a high-quality dielectric, as opposed to having the electromagnetic field reach into a typically more lossy substrate material below, may improve decoherence issues of qubits. At the very least, concentrating electromagnetic fields in the bulk of a carefully controlled high-quality dielectric provided between the upper ground planes and the lower ground plane may relax the requirements on suitable substrates which may be used to implement quantum circuits.

[0054] Another advantage relates to the fact that, with a conventional CPW, when a circuit includes many non-resonant and resonant microwave transmission lines and these lines may include twists and turns to reduce the area occupied by them, keeping all of the ground planes connected with one another is very challenging, from a manufacturing perspective. Typically, this is achieved with extra processing steps, such as e.g. implementing airbridges, bridging different ground planes together. In general, reducing processing steps necessary for manufacturing a device is always desirable, and, in particular eliminating the need to use airbridges may improve mechanical stability and

manufacturability of final devices. With GCPW structures as proposed herein, multiple upper ground planes can be easily connected by a shared common lower ground plane that can run across the entire die/chip.

[0055] Furthermore, proposed transmission line structures may advantageously allow

implementation of three-dimensional interconnect schemes in quantum circuits.

[0056] Although not specifically shown in FIGS. 3A and 3B, the upper ground plane structures 304/308 and the conductor 306 may be covered with a dielectric material which is a low-loss material in terms of spurious TLS's, with controlled interfaces between these materials. Such encapsulation of the GCPW in quantum circuits may further help with reducing qubit decoherence problems because it would eliminate superconductor-air interfaces above the upper ground plane structures 304/308 and the conductor 306.

[0057] FIGS. 4A-4H provide a schematic illustration of fabricating a GCPW for qubits using metal deposition and patterning, according to some embodiments of the present disclosure. A legend provided within a dashed box at the bottom of FIGS.4A-4H illustrates patterns used to indicate different elements shown in FIGS. 4A-4H, so that the FIGs are not cluttered by many reference numerals. FIGS. 4A-4H will now be described with reference to FIG. 5 providing a flow chart of a method 500 for fabricating a GCPW for qubits using metal deposition and patterning, according to some embodiments of the present disclosure. In particular, FIGS. 4A-4G illustrate a sequence of structures 402, 404, 406, 408, and so on until structure 414, each of which illustrates an exemplary result of a corresponding one of different subsequent fabrication processes 502, 504, 506, 508, and so on until process 514 of the method 500. Thus, each structure 4XX corresponds to a respective process box 5XX of the method 500, e.g. a structure 402 illustrates an exemplary result of a fabrication process 502, a structure 404 illustrates an exemplary result of a fabrication process 504, a structure 406 illustrates an exemplary result of a fabrication process 506, and so on (FIG.4H illustrates an exemplary result of a process not specifically shown in FIG. 5). Furthermore, each of FIGS. 4A-4H provides two views of the same structure. Namely, the view on the left side of each of FIGS. 4A-4H is a cross-sectional view with a cross-section of the structures taken along a y-z plane of a coordinate system as shown for the perspective drawing of a transmission line shown in FIG. 3A, while the view on the right side of each of FIGS. 4A-4H is a top-down view of an x-y plane of that coordinate system.

[0058] Although the operations discussed below with reference to the method 500 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 500 may be illustrated with reference to one or more of the embodiments discussed above, but the method 500 may be used to manufacture any suitable quantum circuit element comprising one or more GCPWs according to any embodiments disclosed herein.

[0059] The method 500 may begin with depositing a layer of a lower ground plane material 444 provided over a substrate 442 (process 502 of FIG. 5, result of which is illustrated with a structure 402 of FIG. 4A).

[0060] The substrate 442 may comprise any substrate suitable for realizing quantum circuit components described herein. In one implementation, the substrate 442 may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof. In other implementations, the substrate may be non-crystalline. In general, any material that provides sufficient advantages (e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure. Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.

[0061] In some embodiments, the substrate may be cleaned prior to or/and after any of the processes for forming GCPW described herein, e.g. to remove surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with UV radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using HF).

[0062] The lower ground plane material 444 may comprise any conducting or superconducting material suitable for serving as an interconnect in a quantum circuit, such as e.g. aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TIN), molybdenum rhenium (MoRe), etc., or any alloy of two or more superconducting/conducting materials. The lower ground plane material 444 may be deposited over the substrate 442 using any known techniques for depositing conducting/superconducting materials, such as e.g. atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), chemical vapor deposition (CVD), or electroplating. [0063] In various embodiments, the thickness of the layer of the lower ground plane material 444 may be between 20 and 500 nanometers (nm) including all values and ranges therein, e.g. between 20 and 300 nm, or between 20 and 200 nm.

[0064] As used herein, the term "thickness" refers to a dimension of a certain element or layer as measured along the z-axis as illustrated in the coordinate systems shown in the FIGS., the term "width" refers to a dimension of a certain element or layer as measured along the y-axis as illustrated in the coordinate systems shown in the FIGS., while the term "length" refers to a dimension of a certain element or layer as measured along the x-axis as illustrated in the coordinate systems shown in the FIGS.

[0065] The method 500 may proceed with patterning the layer of the lower ground plane material 444 to form a structure that will serve as a lower ground plane of a GCPW for one or more qubits, e.g. as the lower ground plane 310 of the GCPW 300 (process 504 of FIG. 5, result of which is illustrated with a structure 404 of FIG. 4B). An example of such structure is shown as a rectangular structure 462 shown in FIG. 4B. However, in other embodiments, the ground plane structure 462 could have any other shapes/geometries suitable for serving as a lower ground plane conductor of a GCPW, all of which shapes/geometries being within the scope of the present disclosure.

[0066] In various embodiments, the width of the lower ground plane structure 462 may be between 50 nm and 33 millimeters (mm) including all values and ranges therein, typically between 100 and 15 micrometers (micron), e.g. between 300 nm and 15 microns. In general, the width of the ground plane structure is limited by practical application, as the ground planes would be ideally infinite planes. The smallest width of the lower ground plane could be equal to or slightly larger than the sum of the signal line width ( W2), two ground gaps (52) and two upper ground plane widths (each typically around W2), resulting in approximately 3*W2+2*52. In some embodiments, a single lower ground plane extending across the entire die/chip can be used and shared among all, or some, of the microwave transmission lines.

[0067] In various embodiments, any kind of conventional patterning techniques may be used to form the lower ground plane 462 at the desired locations on the substrate 442, such as e.g.

patterning techniques employing photoresist or other masks defining the dimensions and location of the future lower ground plane conductor 462. An exemplary photoresist patterning technique could include depositing a photoresist over the layer of interest, in this case - over the substrate 442. The photoresist may be a positive or negative resist and may include for example, poly(methyl methacrylate), poly(methyl glutarimide), DNQ/novolac, or SU-8 (an expoxy based negative resist). The photoresist may be chemically amplified containing a photoacid generator and may be based on polymers or co-polymers which contain aromatic rings or alicyclic norbornene derivatives (e.g. for etch resistance), and have protecting groups such as t-butyl. The polymers may include polystyrene or acrylate polymers. The photoresist may be deposited by a casting process such as, for example, spin-coating. The photoresist may then be patterned by optically projecting an image of a desired pattern onto the photoresist using photolithography, such as optical photolithography, immersion photolithography, deep UV lithography, extreme UV lithography, or other techniques. A developer, such as tetramethylammonium hydroxide TMAH (with or without surfactant) at a concentration of in the range of 0.1 N to 0.3 N, may be applied to the photoresist, such as by spin-coating, and portions of the photoresist are removed to expose regions of the underlying layer correlating to the desired pattern. In some embodiments, baking of the substrate may occur before or after any of the above actions. For example, the substrate may be prebaked to remove surface water. After application of the photoresist, a post application bake may occur, wherein at least a portion of the solvents in the photoresist are driven off. After exposure to light, a post-exposure bake may occur to induce chemical reactions, such as de-protecting the photoresist. After patterning, the resist may be hard baked.

[0068] Next, a layer of dielectric material 446 is provided over the substrate 442 with the lower ground plane 462 formed thereon (process 506 of FIG. 5, result of which is illustrated with a structure 406 of FIG. 4C). The dielectric material 446 will implement the dielectric 312 as shown in the GCPW 300. Examples of dielectric materials that may be used as the material of the dielectric layer 446 include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

[0069] The dielectric material 446 could be selected as any dielectric material suitable for undergoing further fabrication processing described herein. For example, since the dielectric layer 446 will need to later be etched to form via openings 466, etching properties of potential candidate materials are to be considered when selecting a suitable material to be used for the layer 446. Besides appropriate etching characteristics, some other considerations in selecting a suitable material may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability). In some implementations it may be preferred that the dielectric material 446 is a low-loss dielectric material, in terms of spurious TLS's, able to form well-controlled interfaces with conducting/superconducting materials of the signal line and the ground planes, thus potentially reducing decoherence issues of qubits. Examples of such low-loss dielectric materials able to form well-controlled interfaces include, but are not limited to epitaxially grown intrinsic silicon, carbon- doped oxides, and silicon nitrides, and fluoropolymers. Other materials from those listed as examples of materials for the dielectric 446 may also be suitable in terms of being low-loss dielectric materials able to form well-controlled interfaces.

[0070] In some embodiments, the dielectric material 446 may include an oxide deposited over the lower ground plane conductor 462 using e.g. CVD or/and plasma-enhanced chemical vapor deposition (PECVD), as typically done in conventional processing. In still other embodiments, the dielectric material 446 may include a dielectric material formed over the lower ground plane conductor 462 using coating techniques involving cross-linking of liquid precursors into solid dielectric materials. In some embodiments, the surface of the lower ground plane conductor 462 may be cleaned or treated prior to applying the dielectric to reduce surface contamination and minimize interface traps and/or promote adhesion, for example using chemical or plasma clean, or applying heat in a controlled environment. In some embodiments, an "interface layer" may be applied between the lower ground plane conductor 462 and the dielectric material 446 to prevent, decrease, or minimize spontaneous and uncontrolled formation of other interfacial layers. In some embodiments, an adhesion promoter or adhesion layer may be applied prior to application of the dielectric.

[0071] Planarization may also be performed in order to achieve a relatively smooth, plane surface of the dielectric layer 446. In various embodiments, planarization may be performed using either wet or dry planarization processes. In one embodiment, planarization may be performed using chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

[0072] A thickness of the dielectric layer 446 above the lower ground plane 462, e.g. measured as a thickness 464 shown in FIG. 4C, would depend on e.g. the desired distance between the signal line and the ground plane of the future GCPW. For example, the dielectric layer 446 may have a thickness between e.g. 20 and 3000 nm, including all values and ranges therein, typically for qubit applications between 0.5 and 1500 nm.

[0073] The method 500 may then proceed with forming a via opening 466 and a via opening 468 in the dielectric layer 446 to connect to the lower ground plane 462 (process 508 of FIG. 5, result of which is illustrated with a structure 408 of FIG. 4D). When filled with electrically conductive material, the via openings 466 and 468 will form interconnects for electrically interconnecting the lower ground plane 462 and the future upper ground plane structures of a GCPW. For example, the via opening 466 may be used to implement the interconnect 314, electrically interconnecting the lower ground plane 310 and the upper ground plane structure 304 of the GCPW 300 shown in FIGS. 3A and 3B, while the via opening 468 may be used to implement the interconnect 318, electrically interconnecting the lower ground plane 310 and the upper ground plane structure 308 of the GCPW 300. In order to properly illustrate the via openings, the side view of FIG. 4D is shown as a cross- section along a line that goes through the via openings 466, such as e.g. line AA shown in the top view of FIG. 4D.

[0074] Dimensions and shapes of the via openings 466 and 468 could depend on e.g. the conductive/superconductive material used to fill these openings, dimensions and shape of the lower ground plane 462 as well as the upper conductors of the future GCPW, and the etching process used to form the vias 466 and 468. For example, in some embodiments, the via opening 466 may be arranged as a continuous line at one edge of the ground plane 462 and the via opening 468 may be arranged along a continuous line at another edge of the ground plane 462, as shown in the top view in FIG. 4D. Providing electrical connections between the upper and lower ground planes of a GCPW using a such continuous interconnects along the length of the signal line may ensure consistent ground performance of the GCPW along the length of the GCPW. However, in other embodiments, each of the via openings 466 and 468 may include a plurality of via openings, arranged in any location and in any shape/geometry as suitable for providing electrical interconnection to the lower ground plane conductor 462 from the upper ground plane conductors of a GCPW may be used, all of which being within the scope of the present disclosure.

[0075] The via openings 466 and 468 extend from the surface of the dielectric layer 446 to the ground plane structure 462. The dielectric layer 446 at least partially surrounds the via openings 466 and 468, isolating them from one another and from other openings that may be formed (not shown in FIG. 4D) both physically and electrically.

[0076] In various embodiments, largest dimensions of the via openings 466, 468 could be between 5 and 1000 nm for both the x-axis and y-axis, including all values and ranges therein.

[0077] In various embodiments, any kind of etching techniques, possibly techniques that involve etching in combination with patterning, e.g. patterning as described above, may be used to form the via openings 466, 468. For example, once patterning has been done to expose portions of the underlying layer 446 in a patterned mask that defines location and arrangement of future via openings 466, 468, exposed portions of the underlying layer 446 are then chemically etched. During the etch, the exposed portions of the surface of the dielectric layer 446 are removed until a desired depth is achieved, forming via openings 466, 468 in the dielectric layer 446. If photoresist patterning is used for creating a mask for forming via openings, the remaining photoresist may then optionally removed via e.g. a process such as ashing, where the photoresist is exposed to oxygen or fluorine, which combines with the photoresist to form ash.

[0078] The method 500 may then proceed with filling the via openings 466, 468 in the dielectric layer 446 with a conducting or superconducting material 448 suitable to provide electrical connectivity to the lower ground plane 462 (process 510 of FIG. 5, result of which is illustrated with a structure 410 of FIG.4E). In various embodiments, the via material 448 may comprise any conducting or superconducting material suitable for serving as an interconnect in a quantum circuit, such as e.g. materials described above with reference to the material of the lower ground plane layer 444. In some embodiments, the via material 448 may be the same as the material of the lower ground plane layer 444. In other embodiments, at least some of the conductive or superconductive materials used in different elements described herein could be different. Although FIG. 4E and subsequent FIGS, illustrate the via opening 466 being filled with the same via material 448 as the via opening 468, in some embodiments, materials filling these two via openings may be different.

[0079] The vias 466, 468 could be filled with the via material using any known techniques for filling via openings, such as e.g. CVD or PVD. Planarization, using e.g. any planarization processes described above, may also be performed in order to expose the surfaces 470, shown in FIG.4E, of the dielectric layer 446 which may be covered with the via material 448 as a result of depositing that material into the via openings.

[0080] In some embodiments, one or more of diffusion and adhesion barrier layers as known in the art may be deposited into the via openings 466, 468 prior to filling the openings with the via material at 510. As is known, diffusion barriers may serve to reduce diffusion of the conductive or superconductive via material out of the via, while adhesion barriers may serve to promote adhesion between the conductive/superconductive via material and the walls of the via openings.

[0081] Next, a layer of upper plane conductor material 450 is provided over the surface 470 of the dielectric material 446 with the vias 466 and 468 filled with via material (process 512 of FIG. 5, result of which is illustrated with a structure 412 of FIG. 4F). Considerations described above with reference to the lower ground plane material 444 are applicable to the upper plane conductor material 450 and deposition thereof and, therefore, in the interest of brevity, are not repeated here. In some embodiments, the upper plane conductor material 450 may be the same as the material of the lower ground plane layer 444 or/and as the material 448 of the vias 466, 468 in the dielectric layer 446. In other embodiments, some or all of these electrically conductive/superconductive materials could be different materials.

[0082] In some embodiments, the surface of the dielectric material 446 may be cleaned or treated prior to applying the upper plane conductor material 450 to reduce surface contamination and minimize interface traps and/or promote adhesion, for example using a chemical or plasma clean, or applying heat in a controlled environment. In some embodiments, an adhesion promoter or adhesion layer may be applied prior to application of the upper plane conductor material 450. [0083] In various embodiments, the thickness of the layer of the upper plane conductor material 450 may be between 20 and 500 nm including all values and ranges therein, e.g. between 20 and 300 nm, or between 20 and 200 nm.

[0084] The method 500 may then proceed with patterning the layer of the upper plane conductor material 450 to form structures that will serve as two upper ground planes and a structure that will serve as a signal line of a GCPW for one or more qubits (process 514 of FIG. 5, result of which is illustrated with a structure 414 of FIG. 4G where upper ground plane structures 474 and 476 and a signal line structure 472 are shown). The upper ground plane structures 474 and 476 could implement the upper ground plane structures 304 and 308 of the GCPW 300 shown in FIGS. 3A and 3B, while the signal line structure 472 could implement the signal line 306 of the GCPW 300.

[0085] The top view of FIG. 4G illustrates an example of a signal line structure 472 implemented as a substantially straight line. However, in other embodiments, the signal line structure 472 could have any other shapes/geometries suitable for serving as a signal line conductor of a GCPW, all of which shapes/geometries being within the scope of the present disclosure. For example, the signal line 472 may have various shapes such as e.g. substantially straight line, a lines with bends (e.g. a wiggly line or a line comprising one or more loop portions), or any other configuration suitable for a particular quantum circuit design. In some embodiments, the upper ground plane structures 474 and 476 would conform to the shape of the signal line 472 in that the shortest distance between the signal line 472 and the ground plane structures 474/476 would be the same along the length of the signal line 472.

[0086] In various embodiments, the width of the signal line 472 may be between 0.05 and 100 micron including all values and ranges therein, e.g. between 1 and 11 micron, or between 3 and 5 micron.

[0087] The length of a resonator, and, hence, the length of the signal line 472, is primarily set by the desired resonant frequency. In some embodiments, target frequencies may be between 2 and 10 GHz, e.g. between 3 and 7 GHz. The resonant frequency of a microwave resonator inversely depends on the length of the resonator, where, with everything else equal, a longer resonator will resonate at longer wavelengths and, therefore, lower frequencies. Resonators can also be designed to be at same length as the resonant wavelength, to be half the wavelength, or to be a quarter of the wavelength. The resonant frequency, and therefore the length of the center conductor, is also affected by the capacitance and inductance of the resonator, including the kinetic inductance of the superconducting wire. On the upper end, the longest microwave transmission line could be limited, roughly, by the length of the chip, although the length could exceed the chip length if the transmission line has curves/wiggles. A microwave feedline could be towards the upper end in length. In various embodiments, the length of the signal line 472 may be between 60 microns and 33 millimeters (mm), including all values and ranges therein, e.g. between 5 mm and 20 mm, or between 6 mm and 15 mm.

[0088] In various embodiments, any kind of conventional patterning techniques may be used to form the signal line 472 and the upper ground plane structures 474 and 476. Descriptions provided above with reference to patterning the lower ground plane 462 are applicable to patterning the signal line 472 and the upper ground plane structures 474 and 476 and, therefore, in the interests of brevity, are not repeated here.

[0089] At least one of the lower ground plane 462 and the upper ground plane structures 474 and 476 need to be electrically connected to the ground potential, and the signal line 472 needs to be electrically connected to a signal source as known in the art, which steps, therefore not described here. At this point, the fabrication of the GCPW may be considered finished.

[0090] Optionally, the structure 414 may also be encapsulated in order to be protected from the negative effects of the environment when such a structure is to be deployed and electrical connections could be made. In some embodiments, the encapsulation may be carried out as follows (not shown in FIGS.).

[0091] First, a layer of dielectric material, e.g. a suitable inter layer dielectric (ILD), is provided over structure 414 with the GCPW formed thereon. Considerations for and examples of suitable dielectric materials and methods of depositing these materials which were provided above with reference to the dielectric material 446 are applicable to a dielectric material used for the encapsulation, therefore, in the interest of brevity, are not repeated here. In some embodiments, the dielectric material used for the encapsulation may be the same as the dielectric material 446. In other embodiments, these materials may be different. Optionally, planarization may be performed in order to achieve a relatively smooth, plane surface of the dielectric layer used for the

encapsulation. A thickness of the dielectric layer used for the encapsulation could depend on e.g. the desired distance to the surface of the device from the upper ground planes of the GCPW. For example, the dielectric layer used for the encapsulation may have a thickness between e.g. 20 and 3000 nm, including all values and ranges therein, typically for qubit applications between 50 and 100 nm.

[0092] Next, one or more first via openings are formed in the dielectric material used for the encapsulation to connect to the signal line 472 and one or more second via openings are formed to connect to the two upper ground planes of the GCPW of the structure 414. Number, dimensions and a shape of the via openings could depend on e.g. the conductive/superconductive material used to fill the via openings, dimensions and shape of the upper ground planes and the conductor strip, and the etching process used to form these via openings. For example, in some embodiments, one via opening could be used as a first via opening and one via opening could be used as a second via opening. However, in other embodiments, any other number of first and second via openings, arranged in any location and in any shape/geometry as suitable for providing electrical

interconnection to the conductor strip and the ground planes of the GCPW may be used, all of which being within the scope of the present disclosure. The first and second via openings extend from the surface of the dielectric layer used for the encapsulation to the respective conductors of the GCPW. The dielectric layer used for the encapsulation at least partially surrounds each of the via openings, isolating them from one another and from other openings that may be formed in that layer, both physically and electrically. In various embodiments, largest dimensions of the first and second via openings could be between 5 and 40 nm for both the x-axis and y-axis, including all values and ranges therein. In various embodiments, any kind of etching techniques, possibly techniques that involve etching in combination with patterning, e.g. patterning as described above, may be used to form the first and second via openings. In some embodiments, both the first and second via openings are formed in a single etching step. For example, once patterning has been done to expose portions of the underlying dielectric layer used for the encapsulation in a patterned mask that defines location and arrangement of future first and second vias, exposed portions of the underlying dielectric layer are then chemically etched, which could be done in a manner described above for the via openings 466 and 468.

[0093] The method may then proceed with filling the one or more first via openings and one or more second via openings in the dielectric layer used for the encapsulation with a conducting or superconducting material suitable to provide electrical connectivity to, respectively, the signal line 472 and the upper ground planes 474 and/or 476. Considerations provided above for filling the via openings 466 and 468 are applicable to filling the first and second via openings and, therefore, in the interests of brevity, the descriptions are not repeated. In various embodiments, the via material used to fill the first and second via openings may be the same or different

conductive/superconductive material used for fill other via openings of the GCPW and the same or different conductive/superconductive material used to form various conductors of the GCPW.

Planarization, using e.g. any planarization processes described above, may also be performed in order to expose the surfaces of the dielectric layer used for the encapsulation which may be covered with the via material as a result of depositing that material into the first and/or second via openings.

[0094] In some embodiments, prior to encapsulation, the method 500 may then proceed with another optional process (not shown in FIGURE 5) where some of the dielectric material 446 may be removed in regions between the signal line a signal line 472 and each of the upper ground plane structures 474 and 476 shown in FIG. 4G, resulting in a structure 416 of FIG. 4H where regions 480 and 482 illustrate such regions where the dielectric 446 is removed. Doing so may be advantageous for quantum circuits because it allows removing potentially lossy dielectric material from the regions with the highest electric field (the higher the electric field is in a certain region, the greater may be the effect of any losses in that region on the decoherence times of qubits). In various embodiments, removal of the dielectric material 446 from the regions 480 and 482 may be performed using a suitable etchant, such as e.g. a corrosive liquid, such as e.g. hydrofluoric acid (HF), or a chemically active ionized gas (i.e. plasma) such as using C_xF_y gases. In some embodiments, the photoresist used to pattern the signal line and first and the second upper ground plane may be left on during this etch in order to protect the metal, and later removed. If this process is implemented, then the encapsulation described above with reference to the structure 414 may be carried out on the structure 416 instead.

[0095] As previously described above, spurious TLS's can be very detrimental to the performance and stability of qubits, especially to the performance and stability of superconducting qubits such as e.g. transmons. FIGS. 6A-6F and 7, described below, provide an alternative fabrication approach to forming GCPW which may be particularly useful in reducing the amount of spurious TLS's by having a greater control over the quality of the materials deposited and by enabling greater control of the interfaces.

[0096] FIGS. 6A-6F provide a schematic illustration of fabricating a GCPW for qubits using dopant implantation and epitaxial growth, according to some embodiments of the present disclosure. A legend provided within a dashed box at the bottom of FIGS. 6A-6F illustrates patterns used to indicate different elements shown in FIGS. 6A-6F, so that the FIGs are not cluttered by many reference numerals. FIGS. 6A-6F will now be described with reference to FIG. 7 providing a flow chart of a method 700 for fabricating a GCPW for qubits using dopant implantation and epitaxial growth, according to some embodiments of the present disclosure. In particular, FIGS. 6A-6F illustrate a sequence of structures 602, 604, 606, and so on until structure 610, each of which illustrates an exemplary result of a corresponding one of different subsequent fabrication processes 702, 704, 706, and so on until process 710 of the method 700. Thus, each structure 6XX corresponds to a respective process box 7XX of the method 700, e.g. a structure 602 illustrates an exemplary result of a fabrication process 702, a structure 604 illustrates an exemplary result of a fabrication process 704, and so on. Furthermore, each of FIGS. 6A-6F provides two views of the same structure similar to the views of FIGS. 4A-4H.

[0097] Although the operations discussed below with reference to the method 700 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 700 may be illustrated with reference to one or more of the embodiments discussed above, but the method 700 may be used to manufacture any suitable quantum circuit element comprising one or more GCPWs according to any embodiments disclosed herein.

[0098] The method 700 may begin with depositing a mask for the subsequent dopant implantation to form a lower ground plane structure in the topmost layer of a substrate 642 (process 702 of FIG. 7, result of which is illustrated with a structure 602 of FIG. 6A). FIG. 6A illustrates that a mask 652 is provided over the substrate 642, the mask 652 having an opening 661 in a location on the substrate where the lower ground plane structure of the future GCPW is to be subsequently formed. In general, descriptions provided above with respect to the substrate 442 are applicable to the substrate 642 and, therefore, not repeated. In some embodiments, it may be particularly advantageous to use a silicon substrate as the substrate 642 used in the method 700, because of the established techniques for dopant implantation and epitaxial growth on such substrates and because such substrates may be suitably low-loss in terms of spurious TLS's. Thus, the following processing operations are described with reference to a silicon (Si) substrate 642.

[0099] Prior to providing a mask on the substrate 642, any standard processing cleaning techniques as known in the art may be applied to obtain single crystal silicon surface that is either as received from a supplier or has an intrinsic (i.e. non-doped or low-doped, where doping is either

unintentional or deliberate) epitaxially grown silicon region in the upper 0.5 to 5 micrometers (microns). In various implementations, this thin epitaxially grown region may comprise silicon that is sufficiently pure so that it can behave as a low-loss insulator at qubits operating temperatures (i.e. either no dopants or sufficiently low-level of dopants) or might be isotopically enriched 28Si (i.e. sufficiently few atoms with nuclear moments to ensure a low loss).

[0100] In this context, non-doped or low-doped silicon implies a non-conductive silicon at temperatures at which qubits operate (i.e. cryogenic temperatures). A person of ordinary skill in the art would recognize that intrinsic layers may sometimes be accidentally doped with defects due to e.g. the addition of unintentional impurities (e.g., oxygen, residual dopants in the chamber, etc.) or unintentional doping from the highly conductive region by diffusion during subsequent thermal processing. Furthermore, sometimes dopants may be deliberately added to materials for reasons such as e.g. thermal or mechanical stability. As long as dopants, whether unintentional or deliberately added, are in amounts that are low enough so that the substrate 642 may still be considered low-loss and insulating at low temperatures at which qubits operate, such silicon may be referred to as intrinsic or non-doped silicon. [0101] After that, the mask 652 may be provided over the substrate 642 in any manner known in the art for providing suitable ion implantation masks, e.g. using photoresist and patterning of the photoresist in a manner similar to that described above. Dimensions and shape/geometry of the opening 661 may be the same or comparable to the dimensions and shape/geometry of the lower ground plane structure to be formed, and could be as described above with reference to the dimensions and shape/geometry of the lower ground plane structure 462, described above.

[0102] Next, dopants 654 are implanted into the substrate 642 through the opening 661 in the mask 652 (process 704 of FIG. 7, result of which is illustrated with a structure 604 of FIG. 6B). As shown in FIG. 6B, this results in dopants implanting in a portion 662 of the substrate 642 exposed by the window 661. Dopants are also implanted into the mask 652, as also schematically illustrated in FIG. 6B with the dopants 654 shown within the mask 652, but dopants implanted into mask 652 do not reach the substrate 642 below it.

[0103] Dopant implantation may be performed by any known dopant implantation techniques. For example, a Si or silicon germanium (SiGe) substrate 642 may be doped with phosphorus (P), boron (B), or arsenic (As) to doping concentrations ranging lel8 to le21 atoms/cm³, including all values and ranges therein, e.g. to about le20 atoms/cm³. As a result, doped regions, such as the region 662, of the substrate 642 could be made conductive or superconductive, as suitable for forming a conductive/superconductive lower ground plane structure for the future GCPW employed in a quantum circuit.

[0104] After ion implantation, the mask 652 may be removed (e.g. the photoresist of which the mask 652 could be made is cleaned off) and the substrate 642 may be annealed to activate the dopants (process 706 of FIG. 7, result of which is illustrated with a structure 606 of FIG. 6C). In some implementations, a photoresist mask may be removed e.g. via a process such as ashing, where the photoresist is exposed to oxygen or fluorine, which combines with the photoresist to form ash which can subsequently be removed. Annealing to activate dopants may, for example, be performed at temperatures in the range of 900^* C to 1100" C, including all values and ranges therein, for a time period in the range of 1 nanoseconds to 1 minute, including all values and ranges therein.

[0105] The substrate 642 with the portion 662 comprising implanted and activated dopants may then, optionally, be cleaned again, using any suitable cleaning techniques as known in the art.

[0106] After dopant activation, the portion 662 becomes conductive/superconductive, as is illustrated in FIG. 6C wit the portion 662 shown with a material 644 instead of just with unactivated dopants 654 as was shown in FIG. 6B. At this point the portion 662 may be considered to form a structure that will serve as a lower ground plane of a GCPW for one or more qubits, e.g. as the lower ground plane 310 of the GCPW 300. [0107] Next, a layer of dielectric material 646 is provided over the substrate 642 with the lower ground plane 662 formed thereon (process 708 of FIG. 7, result of which is illustrated with a structure 608 of FIG. 6D). The dielectric material 646 will implement the dielectric 312 as shown in the GCPW 300. In general, the dielectric material 646 could be selected as any dielectric material suitable for undergoing further fabrication processing described herein and the discussions provided above with respect to the choices for the dielectric material 446 and the methods for deposition of such a material are applicable to the dielectric material 646 used in the method 700. In the interests of brevity, those discussions are not repeated here.

[0108] However, in other embodiments, since the substrate 642 is a Si substrate, the dielectric material 646 may be Si grown over the substrate 646 with the doped portion 662 using any of the atomic level growth techniques as known in the art, e.g. using epitaxial growth. As shown in FIG. 6D, growth of Si over the substrate 642 with the doped portion 662 results in the doped portion being embedded (enclosed on all sides) within the substrate, i.e. being below the surface of the substrate but above the very bottom of the substrate.

[0109] The method 700 may then proceed with a process 710 where a signal line, upper ground plane structures, and interconnects connecting the upper ground plane structures to the lower ground plane structure are formed over the dielectric 646 (process 710 of FIG. 7, result of which is illustrated with a structure 610 of FIG. 6E showing a signal line 672, upper ground plane structures 674 and 676, and interconnects 666 and 668 connecting the upper ground plane structures to the lower ground plane structure 662). Discussions provided above with respect to the signal line 472, the upper ground plane structures 474 and 476, and interconnects 466 and 468 are applicable to the signal line 672, the upper ground plane structures 674 and 676, and the interconnects 666 and 668, and, therefore, in the interests of brevity are not repeated. In particular, the signal line 672, the upper ground plane structures 674 and 676, and interconnects 666 and 668 form, respectively, the signal line 306, the upper ground plane structures 304 and 308, and interconnects 314 and 318 of the GCPW 300 as shown in FIGS. 3A-3B.

[0110] It should be noted that there are some choices involving the order of forming the signal line 672, the upper ground plane structures 674 and 676, and the interconnects 666 and 668, in particular in the order of via formation, deposition of superconductor, and circuit patterning to form upper ground plane structures, which is also applicable to the method of FIG. 5, described above. For example, in some embodiments of the structure 608 of FIG. 6D undergoing the process 710, first, the vias 666 and 668 are formed, then an upper plane conductor material 650 is deposited, and finally, the signal line 472 and the upper ground plane structures 474 and 476 are patterned in the upper plane conductor material 650, resulting in the structure 610 as shown in FIG. 6E. In other embodiments of the structure 608 of FIG. 6D undergoing the process 710, first, the upper plane conductor material 650 is deposited, then the vias 666 and 668 are formed, and finally, the signal line 472 and the upper ground plane structures 474 and 476 are patterned in the upper plane conductor material 650, again resulting in the structure 610 as shown in FIG. 6E. In still other embodiments of the structure 608 of FIG. 6D undergoing the process 710, first, the upper plane conductor material 650 is deposited, then the signal line 472 and the upper ground plane structures 474 and 476 are patterned in the upper plane conductor material 650, and, finally, the vias 666 and 668 are formed, yet again resulting in the structure 610 as shown in FIG. 6E.

[0111] In some embodiments where the vias 666 and 668 are provided before the upper plane conductor material 650 is deposited, the vias 666 and 668 may be provided using one or more dopant implantation techniques, e.g. similar to that used to create doped region 662 shown in FIG. 6D, followed up by the anneal described above, to activate the dopants. After the anneal, such an approach is expected to preserve the Si lattice and lead to the growth/deposition of the upper plane conductor material 650 for the upper plan conductors of the GCPW on top of the substrate without disturbing the epitaxially grown dielectric Si film 646 grown near the via regions.

[0112] In all of the three embodiments with the different order (i.e. irrespective of the order described above), the vias 666 and 668 may be provided using one or more patterning, etching, and metal filling techniques as e.g. was described above with respect to the formation of the vias 466 and 468.

[0113] In all of the three embodiments with the different order, deposition of the upper plane conductor material 650 and patterning of the upper plane conductor material 650 to form the signal line 672 and the upper ground plane structures 674 and 676 may be carried out as described above for the deposition of the upper plane conductor material 450 and patterning of the upper plane conductor material 450 to form the signal line 472 and the upper ground plane structures 474 and 476.

[0114] In some embodiments, the surface of the dielectric 646, in particular where the dielectric 646 is epitaxially grown Si, may be processed prior to deposition of the upper plane conductor material 650 in order to improve quality of Si/superconductor or Si/conductor interface in terms of removal of any lossy native oxide layers followed by any deposition or treatment to change the chemical nature of the resulting Si surface. Such processing may include removal of the native oxide by using one or a combination of wet chemical fluorine etching solutions including but not limited to aqueous HF or aqueous NH₄F or combinations thereof. Such processing may also include dry etching, for example using a plasma dry etch tool along with SF₆, CF_4/ or NF₃, or any combination thereof to remove native oxide followed by further in-situ or ex-situ processing which may include, but is not limited to, high temperature thermal treatments for times up to a few hours at temperatures up to 1400 C, exposure of the surface to hot gaseous vapor or plasmas containing chemicals such as N₂, NH₃, organic molecules, organosilicon molecules, metal precursors, etc., designed to create a chemically distinct transition region between the Si substrate and the superconducting film. Such processing may also be applied when the dielectric 646 is not Si, as well as to the dielectric material 446 described with reference to the method of FIG. 5.

[0115] In some embodiments, the method 700 may then proceed with an optional process (not shown in FIGURE 7) where some of the dielectric material 646 may be removed in regions of relatively high electric field between the signal line a signal line 672 and each of the upper ground plane structures 674 and 676 shown in FIG. 6E, resulting in a structure 612 of FIG. 6F where regions 680 and 682 illustrate such regions where the dielectric 646 is removed. Descriptions provided above with reference to FIG. 4H are applicable to the structure of FIG. 6F and, therefore, in the interests of brevity, are not repeated.

[0116] In further embodiments, the structure 610 shown in FIG. 6E or the structure 612 shown in FIG. 6F, may further be encapsulated as known in the art, e.g. as described above with respect to the encapsulation of the structure 414 of FIG.4G or the structure 416 of FIG. 4H.

[0117] It should be noted that while FIGS. 3A-3B, FIGS. 4A-4H and FIGS. 6A-6F illustrate an example with only one signal line 306/472/672 formed within a transmission line structure, explanations provided herein could easily be extended to embodiments where multiple such signal lines are formed, all of which are within the scope of the present disclosure. Furthermore, in various embodiments, the lower and the upper ground planes may either be connected to a single ground potential or these ground planes could be connected to individual reference potentials.

[0118] GCPW transmission line structures as described herein could be particularly useful as a quantum circuit resonator 106 coupled to the one or more of the plurality of qubits 102, shown in FIG. 1. In various embodiments, such a resonator could be coupled to the one or more qubits 102 via capacitive or inductive coupling. The resonator could be a coupling resonator or a readout resonator. If the resonator is a coupling resonator, then it could be coupled to two or more qubits, thereby coupling two or more qubits so that a change of state of one qubit may cause a change of state of the other qubits. If the resonator is a readout resonator, then typically each qubit could have its own readout resonator (i.e. a given readout resonator would be coupled to only one qubit) so that a state of each qubit could be determined independently from other qubits.

[0119] At least portions of qubits could be advantageously provided within the same plane as the signal line 306/472/672. Providing the qubits in the plane of the signal line 306/472/672 may be particularly advantageous for the encapsulated GCPW architecture described above in that the qubits could then be encapsulated (i.e. hermetically sealed) by the upper dielectric used for the encapsulation on top and by the lower dielectric 312/446/646 on the bottom, eliminating or at least reducing interfaces of conductive/superconductive materials and air, which could be present if the qubits were not encapsulated.

[0120] Any of the known methods could be used for providing the qubits, all of which being within the scope of the present disclosure. In some embodiments, at least some of the processes of forming the signal line 306/472/672 and the upper ground planes 304/474/674 and 308/477/676 could also be used to fabricate at least parts of the qubits (i.e. qubits and parts of the GCPW could be fabricated in some shared process steps). In other embodiments, qubits may be fabricated after all of most of the fabrication processes used for forming the GCPW are finished, in order to eliminate or reduce potential negative impacts due to the fabrication processes used for forming the GCPW on the integrity and performance of the qubits.

[0121] FIG. 8 provide a schematic illustration of a cross-section 800 of a structure comprising a GCPW for use with qubits, according to some embodiments of the present disclosure. As can be seen, FIG. 8 is drawn to reflect example real world process limitations, in that the features are not drawn with precise right angles and straight lines. As shown, FIG. 8 represents a cross-section view similar to that shown in FIGs. 3B, 4G, and 6E as could be visible in e.g. a scanning electron microscopy (SEM) image or a transmission electron miscroscope (TEM) image of any of the structures described above with reference to those FIGS. In such an image of a real structure, possible processing defects could also be visible, such as e.g. tapered vias, occasional screw, edge, or combination dislocations within the crystalline region, occasional dislocation defects of single atoms or clusters of atoms. In particular, FIG. 8 illustrates a substrate 842, a lower ground plane structure 862, vias 866 and 868 electrically interconnecting the lower ground plane structure 862 to upper ground plane structures 874 and 876, respectively, a signal line 872, and a dielectric material 846 enclosed by the lower and upper conductors of the GCPW 800. Each of the elements labeled in FIG. 8 with a reference numeral can be one of the corresponding elements described in the various embodiments described above. Furthermore, although not specifically shown in FIG. 8, features of the GCPW described in the various embodiments above, could also be seen in a real-life image such as the one shown in FIG. 8.

[0122] FIGS. 9A-9B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure. The dies 1102 may include any of the quantum circuits/devices disclosed herein, e.g., the quantum circuit 100, and may include any of the GCPW transmission lines described herein, such as e.g. the GCPW shown in FIGS. 3A-3B, 4G, and 6E, or any combinations of these GCPWs. The wafer 1100 may include semiconductor material and may include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100. Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device. After the fabrication of the semiconductor product is complete, the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product. A die 1102 may include one or more quantum circuits 100 and/or supporting circuitry to route electrical signals to the quantum circuits 100 (e.g., interconnects connected to the conductive contacts of the GCPWs described herein, and other conductive vias and lines), as well as any other IC components. In some embodiments, the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 11) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0123] FIG. 10 is a cross-sectional side view of a device assembly 1300 that may include any of the embodiments of the quantum circuits employing GCPWs disclosed herein. The device assembly 1300 includes a number of components disposed on a circuit board 1302. The device assembly 1300 may include components disposed on a first face 1340 of the circuit board 1302 and an opposing second face 1342 of the circuit board 1302; generally, components may be disposed on one or both faces 1340 and 1342.

[0124] In some embodiments, the circuit board 1302 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1302. In other embodiments, the circuit board 1302 may be a package substrate or flexible board.

[0125] The IC device assembly 1300 illustrated in FIG. 10 includes a package-on-interposer structure 1336 coupled to the first face 1340 of the circuit board 1302 by coupling components 1316. The coupling components 1316 may electrically and mechanically couple the package-on-interposer structure 1336 to the circuit board 1302, and may include solder balls (as shown in FIG. 10), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. [0126] The package-on-interposer structure 1336 may include a package 1320 coupled to an interposer 1304 by coupling components 1318. The coupling components 1318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1316. Although a single package 1320 is shown in FIG. 10, multiple packages may be coupled to the interposer 1304; indeed, additional interposers may be coupled to the interposer 1304. The interposer 1304 may provide an intervening substrate used to bridge the circuit board 1302 and the package 1320. The package 1320 may be a quantum circuit device package as described herein, e.g. a package including the quantum circuit 100 with any of the GCPWs described herein, or a combination thereof, or may be a conventional IC package, for example. Generally, the interposer 1304 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1304 may couple the package 1320 (e.g., a die) to a ball grid array (BGA) of the coupling components 1316 for coupling to the circuit board 1302. In the embodiment illustrated in FIG. 10, the package 1320 and the circuit board 1302 are attached to opposing sides of the interposer 1304; in other embodiments, the package 1320 and the circuit board 1302 may be attached to a same side of the interposer 1304. In some embodiments, three or more components may be interconnected by way of the interposer 1304.

[0127] The interposer 1304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1306. The interposer 1304 may further include embedded devices 1314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1304. The package-on-interposer structure 1336 may take the form of any of the package-on-interposer structures known in the art.

[0128] The device assembly 1300 may include a package 1324 coupled to the first face 1340 of the circuit board 1302 by coupling components 1322. The coupling components 1322 may take the form of any of the embodiments discussed above with reference to the coupling components 1316, and the package 1324 may take the form of any of the embodiments discussed above with reference to the package 1320. The package 1324 may be a package including one or more quantum circuits with qubits as described herein or may be a conventional IC package, for example. In some embodiments, the package 1324 may take the form of any of the embodiments of the quantum circuit 100 with any of the GCPWs described herein.

[0129] The device assembly 1300 illustrated in FIG. 10 includes a package-on-package structure 1334 coupled to the second face 1342 of the circuit board 1302 by coupling components 1328. The package-on-package structure 1334 may include a package 1326 and a package 1332 coupled together by coupling components 1330 such that the package 1326 is disposed between the circuit board 1302 and the package 1332. The coupling components 1328 and 1330 may take the form of any of the embodiments of the coupling components 1316 discussed above, and the packages 1326 and 1332 may take the form of any of the embodiments of the package 1320 discussed above. Each of the packages 1326 and 1332 may be a qubit device package as described herein or may be a conventional IC package, for example. In some embodiments, one or both of the packages 1326 and 1332 may take the form of any of the embodiments of the quantum circuit 100 with any of the GCPWs described herein, or a combination thereof.

[0130] FIG. 11 is a block diagram of an example quantum computing device 2000 that may include any of the quantum circuits with GCPWs disclosed herein. A number of components are illustrated in FIG. 11 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 2000 may be attached to one or more printed circuit boards (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with GCPWs described herein. In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 11, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.

[0131] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum circuits 100 with GCPWs disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits 100, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read. The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to- digital converters.

[0132] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0133] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0134] The quantum computing device 2000 may include a cooling apparatus 2030. The cooling apparatus 2030 may maintain the quantum processing device 2026, in particular the quantum circuits 100 as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0135] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0136] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless

communications (such as AM or FM radio transmissions).

[0137] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[0138] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[0139] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0140] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0141] The quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0142] The quantum computing device 2000 may include a global positioning system (GPS) device 2018 (or corresponding interface circuitry, as discussed above). The GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[0143] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0144] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0145] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0146] The following paragraphs provide examples of various ones of the embodiments disclosed herein.

[0147] Example 1 provides a quantum integrated circuit assembly/device that includes a substrate and a plurality of qubits disposed over or in the substrate. The assembly also includes a transmission line structure associated with one or more of the plurality of qubits and including a lower ground plane structure disposed over or in the substrate, a dielectric layer disposed over the lower ground plane structure, a signal line structure disposed over the dielectric layer, and a first and a second upper ground plane structures disposed over the dielectric layer, where the signal line is provided between the first and the second upper ground plane structures and where each of the first and the second upper ground plane structures are electrically connected to the lower ground plane structure. [0148] Example 2 provides the quantum integrated circuit assembly according to Example 1, where a portion of the dielectric layer that is between the lower ground plane structure and the first and the second upper ground plane structures includes a dielectric material with losses in a microwave spectrum being below a predefined threshold.

[0149] Example 3 provides the quantum integrated circuit assembly according to Example 2, where said portion of the dielectric layer includes epitaxial silicon.

[0150] Example 4 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where a thickness of the dielectric layer is between 20 and 10000 nanometers.

[0151] Example 5 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where a thickness of each of the lower ground plane structure and the first and the second upper ground plane structures is between 20 and 10000 nanometers.

[0152] Example 6 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where a thickness of the signal line structure is between 20 and 10000 nanometers.

[0153] Example 7 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where the first and the second upper ground plane structures are disposed on different sides of the signal line and along the length of the signal line.

[0154] Example 8 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where a distance from the signal line to each of the first and the second upper ground plane structures is between 100 and 100000 nanometers.

[0155] Example 9 provides the quantum integrated circuit assembly according to any one of the preceding Examples, further including one or more first interconnects for connecting the signal line structure to a signal source and one or more second interconnects for connecting at least one of the lower ground plane structure and the first and the second upper ground plane structures to a ground potential.

[0156] Example 10 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where the transmission line structure is a quantum circuit resonator coupled to the one or more of the plurality of qubits.

[0157] Example 11 provides the quantum integrated circuit assembly any one of the preceding Examples, where each of the lower ground plane structure, the signal line structure, and the first and the second upper ground plane structures includes one or more of superconductive materials.

[0158] Example 12 provides the quantum integrated circuit assembly according to Example 11, where the one or more of superconductive materials includes one or more of aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (UN), or niobium titanium nitride (NbTiN). [0159] Example 13 provides a method of manufacturing a quantum device. The method includes providing a lower ground plane structure over or in a substrate; providing a dielectric layer over the lower ground plane structure; providing a first and a second upper ground plane structures disposed over the dielectric layer; providing a signal line structure over the dielectric layer and between the first and the second upper ground plane structures; providing a plurality of interconnects electrically interconnecting the first and the second upper ground plane structures to the lower ground plane structure; and providing a plurality of qubits over or in the substrate, where the lower ground plane structure, the signal line, the first and the second upper ground plane structures, and the plurality of interconnects form a transmission line structure for one or more of the plurality of qubits.

[0160] Example 14 provides the method according to Example 13, where the substrate is a silicon substrate and where providing the lower ground plane structure includes implanting dopants in a portion of a top layer of the substrate to form the lower ground plane structure and activating the implanted dopants.

[0161] Example 15 provides the method according to Example 14, where the top layer of the substrate includes an uppermost layer of intrinsic or low-doped epitaxially grown silicon.

[0162] Example 16 provides the method according to Example 15, where the uppermost layer includes silicon that is sufficiently pure to behave as a low-loss insulator at qubit operating temperatures.

[0163] Example 17 provides the method according to Examples 15 or 16, where the uppermost layer of intrinsic or low-doped epitaxially grown silicon includes isotopically enriched silicon.

[0164] Example 18 provides the method according to any one of Examples 15-17, where the uppermost layer has a thickness between 0.5 and 5 micrometers (microns).

[0165] Example 19 provides the method according to any one of Examples 13-18, where providing the dielectric layer over the lower ground plane structure includes epitaxially growing silicon on the top layer of the substrate.

[0166] Example 20 provides the method according to Example 19, where providing the plurality of interconnects includes providing interconnect openings in the epitaxially grown silicon, the openings extending to the lower ground plane structure, and filling the interconnect openings with one or more electrically conductive materials.

[0167] Example 21 provides the method according to Example 19, where the dielectric layer includes epitaxial silicon and where providing the plurality of interconnects includes implanting dopants in portions of the dielectric layer to form the plurality of interconnects, dopant implantation extending to the lower ground plane structure, and activating the implanted dopants. [0168] Example 22 provides the method according to any one of Examples 13-21, where the plurality of qubits include superconducting qubits and are provided over the substrate after the transmission line structure is formed.

[0169] Example 23 provides a quantum computing device that includes a quantum processing device that includes a die including a plurality of qubits, a non-quantum processing device coupled to the quantum processing device, and a memory device to store data generated by the plurality of qubits during operation of the quantum processing device. The quantum processing device further includes a transmission line structure associated with one or more of the plurality of qubits, the transmission line including a lower ground plane structure, a dielectric layer disposed over the lower ground plane structure, a first and a second upper ground plane structures disposed over the dielectric layer and electrically connected to the lower ground plane structure, and a signal line structure disposed over the dielectric layer between the first and the second upper ground plane structures.

[0170] Example 24 provides the quantum computing device according to Example 23, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

[0171] Example 25 provides the quantum computing device according to Examples 23 or 24, where the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

[0172] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0173] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

Claims:

1. A quantum integrated circuit assembly, comprising:

a substrate;

a plurality of qubits over or in the substrate; and

a transmission line structure comprising

a lower ground plane structure,

a dielectric layer over the lower ground plane structure,

a signal line structure over the dielectric layer, and

a first and a second upper ground plane structures over the dielectric layer, wherein the signal line is provided between the first and the second upper ground plane structures and wherein each of the first and the second upper ground plane structures are electrically connected to the lower ground plane structure.

2. The quantum integrated circuit assembly according to claim 1, wherein a portion of the dielectric layer that is between the lower ground plane structure and the first and the second upper ground plane structures comprises a dielectric material with losses in a microwave spectrum being below a predefined threshold.

3. The quantum integrated circuit assembly according to claim 2, wherein said portion of the dielectric layer comprises epitaxial silicon.

4. The quantum integrated circuit assembly according to any of claims 1-3, wherein a thickness of the dielectric layer is between 20 and 10000 nanometers.

5. The quantum integrated circuit assembly according to any of claims 1-3, wherein a thickness of each of the lower ground plane structure and the first and the second upper ground plane structures is between 20 and 10000 nanometers.

6. The quantum integrated circuit assembly according to any of claims 1-3, wherein a thickness of the signal line structure is between 20 and 10000 nanometers.

7. The quantum integrated circuit assembly according to any of claims 1-3, wherein the first and the second upper ground plane structures are on different sides of the signal line and along the length of the signal line.

8. The quantum integrated circuit assembly according to claim 7, wherein a distance from the signal line to each of the first and the second upper ground plane structures is between 100 and 100000 nanometers.

9. The quantum integrated circuit assembly according to any of claims 1-3, further comprising one or more first interconnects for connecting the signal line structure to a signal source and one or more second interconnects for connecting at least one of the lower ground plane structure and the first and the second upper ground plane structures to a ground potential.

10. The quantum integrated circuit assembly according to any of claims 1-3, wherein the transmission line structure is a quantum circuit resonator coupled to the one or more of the plurality of qubits.

11. The quantum integrated circuit assembly according to any of claims 1-3, wherein each of the lower ground plane structure, the signal line structure, and the first and the second upper ground plane structures comprises one or more of superconductive materials.

12. The quantum integrated circuit assembly according to claim 11, wherein the one or more of superconductive materials comprises one or more of aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), or niobium titanium nitride (NbTiN).

13. A method of manufacturing a quantum device, the method comprising:

providing a lower ground plane structure over or in a substrate;

providing a dielectric layer over the lower ground plane structure;

providing a first and a second upper ground plane structures over the dielectric layer;

providing a signal line structure over the dielectric layer and between the first and the second upper ground plane structures;

providing a plurality of interconnects electrically interconnecting the first and the second upper ground plane structures to the lower ground plane structure; and

providing a plurality of qubits over or in the substrate, wherein the lower ground plane structure, the signal line, the first and the second upper ground plane structures, and the plurality of interconnects form a transmission line structure for one or more of the plurality of qubits.

14. The method according to claim 13, wherein the substrate is a silicon substrate and wherein providing the lower ground plane structure comprises implanting dopants in a portion of a top layer of the substrate to form the lower ground plane structure and activating the implanted dopants.

15. The method according to claim 14, wherein the top layer of the substrate comprises an uppermost layer of intrinsic or low-doped epitaxially grown silicon.

16. The method according to claim 15, wherein the uppermost layer comprises silicon that is sufficiently pure to behave as a low-loss insulator at qubit operating temperatures.

17. The method according to claims 15 or 16, wherein the uppermost layer of intrinsic or low- doped epitaxially grown silicon comprises isotopically enriched silicon.

18. The method according to claims 15 or 16, wherein the uppermost layer has a thickness between 0.5 and 5 micrometers (microns).

19. The method according to any one of claims 13-16, wherein providing the dielectric layer over the lower ground plane structure comprises epitaxially growing silicon on the top layer of the substrate.

20. The method according to claim 19, wherein providing the plurality of interconnects comprises providing interconnect openings in the epitaxially grown silicon, the openings extending to the lower ground plane structure, and filling the interconnect openings with one or more electrically conductive materials.

21. The method according to claim 19, wherein the dielectric layer comprises epitaxial silicon and wherein providing the plurality of interconnects comprises implanting dopants in portions of the dielectric layer to form the plurality of interconnects, dopant implantation extending to the lower ground plane structure, and activating the implanted dopants.

22. The method according to any one of claims 13-16, wherein the plurality of qubits comprise superconducting qubits and are provided over the substrate after the transmission line structure is formed.

23. A quantum computing device, comprising:

a quantum processing device, wherein the quantum processing device includes a die comprising a plurality of qubits and a transmission line structure associated with one or more of the plurality of qubits, the transmission line comprising

a lower ground plane structure,

a dielectric layer disposed over the lower ground plane structure,

a first and a second upper ground plane structures disposed over the dielectric layer and electrically connected to the lower ground plane structure, and a signal line structure disposed over the dielectric layer between the first and the second upper ground plane structures;

a non-quantum processing device coupled to the quantum processing device; and

a memory device to store data generated by the plurality of qubits during operation of the quantum processing device.

24. The quantum computing device according to claim 23, further comprising a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

25. The quantum computing device according to claims 23 or 24, wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.