JP7322832B2 - 量子コンピュータ用半導体装置の製造方法 - Google Patents
量子コンピュータ用半導体装置の製造方法 Download PDFInfo
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- H—ELECTRICITY
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- H10N60/00—Superconducting devices
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- H10N60/0884—Treatment of superconductor layers by irradiation, e.g. ion-beam, electron-beam, laser beam, X-rays
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Description
(注) 上記の10dBは正確には+9.54dB = 20 × Log3である。
前記半導体基板上に前記量子コンピュータ用素子及び前記周辺回路を形成する工程と、
前記半導体基板のうち少なくとも量子コンピュータ用素子形成部及び周辺回路形成部に粒子線を照射することにより、半導体基板中のキャリアを不活性化する工程と
を含むことを特徴とする量子コンピュータ用半導体装置の製造方法を提供する。
前記半導体基板上に前記量子コンピュータ用素子及び前記周辺回路を形成する工程と、
前記半導体基板のうち少なくとも量子コンピュータ用素子形成部及び周辺回路形成部に粒子線を照射することにより、半導体基板中のキャリアを不活性化する工程と
を含むことを特徴とする量子コンピュータ用半導体装置の製造方法である。
CZ法で作製した直径300mmボロンドープの高抵抗率シリコン単結晶基板(抵抗率5000Ω・cm)を準備した。この基板に電子線を基板全面に照射(加速エネルギー:2MeV、ドーズ量:1×1014~1×1015/cm2)した。その後、SR(Spreading Resistance)法で基板抵抗率を測定した。測定結果を図3に示す。図3に示した結果から、電子線照射量が多くなるほど、基板抵抗率が高くなることがわかった。
CZ法で作製した直径300mmボロンドープの高抵抗率シリコン単結晶基板(抵抗率1000Ω・cm)を準備した。この基板に電子線を基板全面に照射(加速エネルギー:2MeV、ドーズ量:1×1014~1×1015/cm2)した。その後、SR法で基板抵抗率を測定した。測定結果を図6に示す。図6に示した結果から、電子線照射量が多くなるほど、基板抵抗率が高くなることがわかった。
CZ法で作製した直径300mmノンドープの高抵抗率シリコン単結晶基板(P型、抵抗率20000Ω・cm)を準備した。この基板にプラズマCVDにて表面に厚さが400nmの酸化膜を形成した。次いで、この基板上の中心部、半径方向の中央部(中心から半径方向に75mmの位置:4箇所)、外周部(中心から半径方向に140mmの位置:4箇所)の位置に、アルミニウム電極で図10に示したのと同様の構造を有するCPW5(路線長:2200μm)を形成した素子を作製した。その後、電子線を基板全面に照射(加速エネルギー:2MeV、ドーズ量:1×1015/cm2)して、実施例3の評価用基板を作製した。
Claims (5)
- 半導体基板と、前記半導体基板上に形成された量子コンピュータ用素子と、前記半導体基板上に形成され且つ前記量子コンピュータ用素子に接続された周辺回路とを具備し、量子コンピュータとして使用する量子コンピュータ用半導体装置の製造方法であって、
前記半導体基板上に前記量子コンピュータ用素子及び前記周辺回路を形成する工程と、
前記半導体基板のうち少なくとも量子コンピュータ用素子形成部及び周辺回路形成部に粒子線を照射することにより、半導体基板中のキャリアを不活性化する工程と
を含むことを特徴とする量子コンピュータ用半導体装置の製造方法。 - 前記粒子線の照射により、前記半導体基板の前記量子コンピュータ用素子形成部及び前記周辺回路形成部の抵抗率を3000Ω・cm以上にすることを特徴とする請求項1に記載の量子コンピュータ用半導体装置の製造方法。
- 前記半導体基板上に前記量子コンピュータ用素子及び前記周辺回路を形成する前に、前記半導体基板のうち少なくとも前記量子コンピュータ用素子形成部及び前記周辺回路形成部に前記粒子線を照射することを特徴とする請求項1または請求項2に記載の量子コンピュータ用半導体装置の製造方法。
- 前記半導体基板上に前記量子コンピュータ用素子及び前記周辺回路を形成した後に、前記半導体基板のうち少なくとも前記量子コンピュータ用素子形成部及び前記周辺回路形成部に前記粒子線を照射することを特徴とする請求項1または請求項2に記載の量子コンピュータ用半導体装置の製造方法。
- 前記粒子線として電子線を照射することを特徴とする請求項1から請求項4のいずれか一項に記載の量子コンピュータ用半導体装置の製造方法。
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KR1020227046223A KR20230044151A (ko) | 2020-07-29 | 2021-05-26 | 양자 컴퓨터용 반도체 장치의 제조 방법 |
PCT/JP2021/019893 WO2022024526A1 (ja) | 2020-07-29 | 2021-05-26 | 量子コンピュータ用半導体装置の製造方法 |
EP21851363.8A EP4190742A1 (en) | 2020-07-29 | 2021-05-26 | Method for manufacturing quantum computing semiconductor device |
US18/014,221 US20230276716A1 (en) | 2020-07-29 | 2021-05-26 | Method for producing semiconductor apparatus for quantum computer |
CN202180046661.6A CN115867509A (zh) | 2020-07-29 | 2021-05-26 | 量子计算机用半导体装置的制造方法 |
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JP2011512525A (ja) | 2008-02-11 | 2011-04-21 | クコー ピーティーワイ リミテッド | 電子又はホールスピンの制御及び読み取り |
WO2019081970A1 (en) | 2017-10-27 | 2019-05-02 | International Business Machines Corporation | VERTICAL SUPERCONDUCTIVE CAPACITORS FOR QUANTITIES TRANSMON |
WO2019105716A1 (en) | 2017-11-28 | 2019-06-06 | International Business Machines Corporation | Flip chip integration on qubit chips |
JP2020061447A (ja) | 2018-10-09 | 2020-04-16 | 国立研究開発法人科学技術振興機構 | 超伝導複合量子計算回路 |
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JPS5193684A (en) | 1975-02-14 | 1976-08-17 | Dendorono seizohoho | |
JPS51100644A (ja) | 1975-03-04 | 1976-09-06 | Ise Electronics Corp | |
JP3236228B2 (ja) | 1996-09-18 | 2001-12-10 | 財団法人半導体研究振興会 | 半導体デバイス及びその製造方法 |
JP2005093939A (ja) | 2003-09-19 | 2005-04-07 | Mitsubishi Heavy Ind Ltd | 集積型タンデム接合太陽電池及び集積型タンデム接合太陽電池の製造方法 |
DE112017006442T5 (de) | 2016-12-21 | 2019-09-19 | Intel Corporation | Drahtlose kommunikationstechnologie, einrichtungen und verfahren |
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JP2011512525A (ja) | 2008-02-11 | 2011-04-21 | クコー ピーティーワイ リミテッド | 電子又はホールスピンの制御及び読み取り |
WO2019081970A1 (en) | 2017-10-27 | 2019-05-02 | International Business Machines Corporation | VERTICAL SUPERCONDUCTIVE CAPACITORS FOR QUANTITIES TRANSMON |
WO2019105716A1 (en) | 2017-11-28 | 2019-06-06 | International Business Machines Corporation | Flip chip integration on qubit chips |
JP2020061447A (ja) | 2018-10-09 | 2020-04-16 | 国立研究開発法人科学技術振興機構 | 超伝導複合量子計算回路 |
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