CN111354785A - 形成氧化物结构的方法 - Google Patents
形成氧化物结构的方法 Download PDFInfo
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Abstract
本发明提供一种形成氧化物结构的方法与其结构,所述半导体结构包括:具有多个沟槽的衬底;非晶衬层,设置在所述衬底的顶面上以及在所述多个沟槽中的至少一者内;和设置在所述非晶衬层上的电介质衬垫层。其中,所述多个沟槽包括第一组沟槽和第二组沟槽,且所述非晶衬层仅设置在所述第一组沟槽中。
Description
技术领域
本公开总体上涉及形成半导体结构的方法,更具体地,涉及在半导体结构中形成氧化物结构的方法。
本申请要求于2018年12月24日提交的美国临时专利申请号62784553和于2018年12月24日提交的美国临时专利申请号62784554的优先权,在此通过引用将其并入,并作为其一部分。
背景技术
在半导体器件制造中,非晶层缺陷常导致在非晶层上方形成的氧化物结构上的污染和针孔缺陷。因此,有需要开发一种形成连续均匀的非晶层的方法。
发明内容
有鉴于此,有必要提供一种在半导体结构中形成氧化物结构的方法与其结构,以解决上述技术问题。
一种形成氧化物结构的方法,包括:在衬底的顶面上形成第一组沟槽;以及对所述基板进行表面处理工艺,所述表面处理工艺包括:在基板上形成非晶层;氧化所述非晶层;蚀刻所述非晶层的一部分以形成衬里层,其中所述非晶层的厚度比所述衬里层的厚大;以及在所述衬里层上形成电介质衬垫层。
一种制造半导体器件的方法,包括:在衬底的顶面上形成多个沟槽;在所述衬底上进行表面处理工艺,所述表面处理工艺包括:在所述衬底的沟槽的暴露表面上形成非晶衬层;减少所述非晶衬层的厚度;和将所述非晶衬里层至少部分地转变成电介质衬垫层;以及在所述电介质衬垫层上设置导电材料以填充所述沟槽。
一种半导体结构,包括:具有多个沟槽的衬底;非晶衬层,设置在所述衬底的顶面上以及在所述多个沟槽中的至少一者内;和设置在所述非晶衬层上的电介质衬垫层。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据提供的附图获得其他的附图。
图1示出了根据本公开的一些实施例的形成氧化物结构的方法的流程图;
图2示出了根据本公开的一些实施例的形成氧化物结构的方法的流程图;
图3A-3D示出了根据本公开的一些实施例的半导体结构的截面示意图;
图4A-4D示出了根据本公开的一些实施例的半导体结构的截面示意图;
图5示出了根据本公开的一些实施例的半导体结构的截面示意图。
然而,要注意的是,随附图式仅说明本案之示范性实施态样并因此不被视为限制本案的范围,因为本案可承认其他等效实施态样。
主要组件符号说明
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
以下描述将参考附图以更全面地描述本发明。附图中所示为本公开的示例性实施例。然而,本发明可以以许多不同的形式来实施,并且不应该被解释为限于在此阐述的示例性实施例。提供这些示例性实施例是为了使本公开透彻和完整,并且将本发明的范围充分地传达给本领域技术人员。类似的附图标记表示相同或类似的组件。
本文使用的术语仅用于描述特定示例性实施例的目的,而不意图限制本发明。如本文所使用的,除非上下文另外清楚地指出,否则单数形式“一”,“一个”和“该”旨在也包括复数形式。此外,当在本文中使用时,“包括”和/或“包含”或“包括”和/或“包括”或“具有”和/或“具有”,整数,步骤,操作,组件和/或组件,但不排除存在或添加一个或多个其它特征,区域,整数,步骤,操作,组件,组件和/或其群组。
除非另外定义,否则本文使用的所有术语(包括技术和科学术语)具有与本公开所属领域的普通技术人员通常理解的相同的含义。此外,除非文中明确定义,诸如在通用字典中定义的那些术语应该被解释为具有与其在相关技术和本公开内容中的含义一致的含义,并且将不被解释为理想化或过于正式的含义。以下内容将结合附图对示例性实施例进行描述。须注意的是,参考附图中所描绘的组件不一定按比例显示;而相同或类似的组件将被赋予相同或相似的附图标记表示或类似的技术用语。
图1示出了根据本公开的一些实施例的形成氧化物结构的方法的流程图。该方法包括在衬底的顶表面上形成第一组沟槽(101),并且在衬底上执行表面处理工艺(102)。形成表面处理的方法包括在衬底上形成非晶层(102-1),氧化上述非晶层(102-2),去除一部分上述非晶层(102-2)。处理后的所述非晶层形成衬里层(102-3),并在所述衬里层上形成电介质衬里(102-4)。在上述制程中,所述非晶层比所述衬里层厚。在一些实施例中,该方法还包括在衬底的顶表面形成第二组沟槽。在一些实施例中,在表面处理工艺之后,将导电材料设置在电介质衬垫层上,进而填充衬底上的沟槽。
如图3B所示,非晶层301被形成于衬底300上。在一些实施例中,非晶层301具有沿着衬底300的顶表面以及第一组沟槽S的壁面方向而适形延伸的均匀厚度T1。在一些实施例中,厚度T1约为在一些实施例中,厚度T1可小于约在一些实施例中,厚度T1为大于大约在一些实施例中,厚度T1为大约至大约的范围。在一些实施例中,厚度T1在大约90埃至大约150埃的范围。所述非晶层301可以包括有机或无机材料。例如,前述非晶层301可以包括非晶硅。在一些实施例中,非晶层301可以包括例如薄膜润滑剂、金属玻璃、聚合物、和凝胶等的至少一种材料。在一些实施例中,可通过使用化学气相沉积在衬底的顶表面上沉积非晶材料来而衬底300上形成非晶层301。
在一些实施例中,非晶层301在随后的制程步骤中被氧化。在一些实施例中,非晶层301是通过使用氧气(O2)的干式氧化而氧化。在一些实施方案中,可使用水(H2O)通过湿氧化方是将非晶层氧化。在一些实施例中,可藉由去除非晶层301的一部分而形成前述衬里层301-1,其制程程序可包括:使用氟化氢(HF)溶液蚀刻前述非晶层301被氧化的部分而形成衬里层(301-1)。
在一些实施例中,部分去除非晶层301以形成衬里层301-1的流程包括:蚀刻所述非晶层301的一部分以形成所述衬里层301-1。在一些实施例中,前述蚀刻程序可为使用标准清洁蚀刻剂1(SC1)的湿蚀刻工艺。前述SC1蚀刻剂包括NH4OH、H2O2、和去离子水中的至少一种。在一些实施例中,H2O2用于氧化非晶层301,而NH4OH用于去除非晶层301的被氧化部分,进而形成所示的衬里层301-1。在一些实施例中,可使用氢氟酸(HF)为蚀刻剂的湿蚀刻工艺。氢氟酸(O3_HF)蚀刻剂包括O3水和HF。在一些实施例中,O3用于氧化非晶层301,而HF用于去除非晶层301上的氧化部分,进而形成所示的衬里层301-1。
如图3C所示,非晶层301的一部分被去除而形成衬里层301-1。在一些实施例中,衬里层301-1适形地沿着衬底300的顶表面和第一组沟槽S的壁延伸而具有大致均匀的厚度T2。在一些实施例中,厚度T2约为在一些实施例中,厚度T2小于约在一些实施例中,厚度T2大于约在一些实施例中,厚度T2在大约至大约的范围。在一些实施例中,厚度T2为大约至大约的范围。所述非晶层301的厚度T1约为所述衬里层301-1的厚度T2的约3至5倍。
如图3D所示,第二组沟槽G被形成于衬底300的顶表面上。随后,电介质衬层302被形成于前述衬里层301-1上。在一些实施例中,电介质衬层302被设置在第一组沟槽S内。同样地,电介质衬层302被进一步设置在第二组沟槽G内。在一些实施例中,被设置在第二组沟槽G中的电介质衬层302系直接与衬底300的表面接触。在一些实施例中,第一组沟槽S用于形成浅沟槽隔离结构(STI),而第二组沟槽G用于形成沟槽式栅极结构。
在一些实施例中,在衬里层上形成电介质衬垫层之前,前述的衬底表面处理过程可以在图3C所示的步骤之后被重复执行数次。藉此,取而代之地,图1中所示的结构将被图5所示的结构取代。图5示出了根据本公开的一些实施例的半导体结构的截面示意图。其中,副衬里层503被形成于前述第一组沟槽S”和第二组沟槽G”的结构表面。前述副衬里层503可以被形成于第一组沟槽S”内并与衬里层501-1的表面直接接触。同样地,副衬里层503可以与第二组沟槽G”内的衬底500的表面直接接触。在一些实施例中,第一组沟槽S”用于形成浅沟槽隔离(STI),而第二组沟槽G”用于形成沟槽式栅极。
在一些实施例中,所述副衬里层503的厚度T3约为在一些实施例中,厚度T3小于约在一些实施例中,厚度T3大于约在一些实施例中,厚度T3为大约至大约的范围。在一些实施例中,厚度T3在大约至大约的范围。在一些实施例中,所述副衬里层503和衬里层501-1的总厚度为约至约
图2示出了根据本公开的一些实施例的形成氧化物结构的方法的流程图。该方法包括:在衬底的顶表面上形成第一组沟槽与第二组沟槽(201)、并且在衬底上执行表面处理工艺(202)。上述表面处理的方法包括在衬底上形成非晶层(202-1)、氧化所述非晶层(202-2),去除一部分所述非晶层以形成衬里层(202-3)、并在所形成的衬里层上形成电介质衬层(202-4)。在一些实施例中,第一组沟槽和第二组沟槽为同时形成。在该过程中,非晶层的厚度比衬里层厚。在一些实施例中,可进一步将导电材料设置在所述电介质衬垫层上以填充衬底上的沟槽。
图4A-4D示出了根据本公开的一些实施例的半导体结构的截面示意图。较具体地,图4A-4D示出了在形成氧化物结构的过程中半导体结构的横截面。如图4A所示,所述制程起始于提供衬底400。在一些实施例中,第一沟槽S'和第二沟槽G'被形成在衬底400上。第一沟槽S'和第二沟槽G'并不穿透其底部。之后,在衬底400上执行表面处理工艺。
在一些实施例中,第一组沟槽S'的开口的宽度大于第二组沟槽G'的开口的宽度。在一些实施例中,第一组沟槽S'的底部到衬底400的顶表面的距离大于第二组沟槽G'的底部到衬底400的顶表面的距离。在一些实施例中,第一组沟槽S'的底部由衬底400的顶表面起算的深度与第二组沟槽G'的底部从衬底400的顶表面起算的沟槽深度大致相同。
如图4B所示,非晶层301被形成于衬底300上。在一些实施例中,非晶层401适形地沿着衬底400的顶表面、第一组沟槽S'的壁、和第二组沟槽G'的壁延伸,并具有大致均匀的厚度T1'。。在一些实施例中,厚度T1’约为在一些实施例中,厚度T1’小于约在一些实施例中,厚度T1’大于约 在一些实施例中,厚度T1’在大约至大约的范围。在一些实施例中,厚度T1’在大约至大约的范围。非晶层401可以包括有机或无机材料。例如,非晶层401可以包括非晶硅。在一些实施例中,非晶层301可以包括例如薄膜润滑剂、金属玻璃、聚合物、和凝胶等材料的至少一种。
在一些实施例中,非晶层401在随后的制程步骤中被氧化。在一些实施例中,非晶层401是通过使用氧气(O2)的干式氧化而氧化。在一些实施方案中,可使用水(H2O)通过湿氧化方式将非晶层氧化。在一些实施例中,可藉由去除非晶层401的一部分而形成前述衬里层401-1,其制程程序可包括:使用氟化氢(HF)溶液蚀刻前述非晶层401被氧化的部分而形成衬里层(401-1)。
在一些实施例中,硅(Si)和碳(C)之间的比率(Si:C比率)为大约1:2至大约2:1的范围。前述硅:碳比可以根据射频功率,基板温度和气体混合物而变化。在一些实施例中,RF功率可设在300W至1000W的范围(在700W下可形成1:1的比率)。在一些实施例中,衬底温度在约50℃至500℃的范围。
在一些实施例中,部分去除非晶层401以形成衬里层401-1的流程包括:蚀刻所述非晶层401的一部分以形成所述衬里层401-1。在一些实施例中,前述蚀刻程序可为使用标准清洁蚀刻剂1(SC1)的湿蚀刻工艺。前述SC1蚀刻剂包括NH4OH、H2O2、和去离子水中的至少一种。在一些实施例中,H2O2用于氧化非晶层401,而NH4OH用于去除非晶层301的被氧化部分,进而形成所示的衬里层401-1。在一些实施例中,可使用氢氟酸(HF)为蚀刻剂的湿蚀刻工艺。氢氟酸(O3_HF)蚀刻剂包括O3水和HF。在一些实施例中,O3用于氧化非晶层401,而HF用于去除非晶层401上的氧化部分,进而形成所示的衬里层401-1。
在一些实施例中,衬里层401-1适形地沿着衬底400的顶表面和第一组沟槽S的壁延伸而具有大致均匀的厚度T2’。在一些实施例中,厚度T2’约为在一些实施例中,厚度T2’小于约在一些实施例中,厚度T2’大于约在一些实施例中,厚度T2’在大约至大约的范围。在一些实施例中,厚度T2’为大约至大约的范围。所述非晶层401的厚度T1’约为所述衬里层401-1的厚度T2’的约3至5倍。
如图4D所示,电介质衬垫层402被形成于衬里层401-1上。所述电介质衬垫层402被设置在第一组沟槽S’和第二组沟槽G’内。在一些实施例中,前述第一组沟槽S’被用于形成浅沟槽隔离结构(STI),而第二组沟槽G’被用于形成沟槽式栅极结构。
有鉴于前述揭露内容,本公开的另一个方面提供了一种形成氧化物的方法,包括:在衬底的顶面上形成第一组沟槽;和在所述衬底上进行表面处理,所述表面处理工艺包括:在所述衬底上形成非晶层;蚀刻所述非晶层的一部分以形成衬里层,其中所述非晶层比所述衬里层厚;和在衬里层上设置介电材料。
在一些实施例中,所述方法还包括:在所述衬底的顶表面上形成第二组沟槽。
在一些实施例中,所述第一组沟槽的底部与所述衬底的顶表面的距离大于所述第二组沟槽的底部与所述衬底的顶表面的距离。
在一些实施例中,所述第一组沟槽和所述第二组沟槽同时形成。
在一些实施例中,所述方法还包括:在形成所述第二组沟槽之后重复前述表面处理过程。
在一些实施例中,所述第一组沟槽的开口的宽度大于所述第二组沟槽的开口的宽度。
在一些实施例中,其中在所述衬底上形成所述非晶层包括使用化学气相沉积在所述衬底的顶表面上沉积非晶材料。
在一些实施例中,所述第一组沟槽不穿透所述衬底的底表面。
在一些实施例中,所述非晶层的厚度是所述衬里层的厚度的约3至5倍。
在一些实施例中,蚀刻所述非晶层的所述部分以形成所述衬里层包括使用标准清洁剂1(SC1)蚀刻剂的湿蚀刻工艺。
在一些实施例中,所述SC1蚀刻剂包括NH4OH,H2O2和去离子水中的至少一种。
在一些实施例中,蚀刻所述非晶层的所述部分以形成所述衬里层包括使用氢氟酸(O3_HF)蚀刻剂的湿蚀刻工艺。
本公开的另一个方面提供了一种制造半导体器件的方法,其包括:在衬底的顶面上形成多个沟槽;在所述衬底上进行表面处理工艺,所述表面处理工艺包括:在所述衬底的沟槽的暴露表面上形成非晶衬层;减少所述非晶衬层的厚度;和将所述非晶衬里层至少部分地转变成电介质衬垫层;以及在所述电介质衬垫层上设置导电材料以填充所述沟槽。
本公开的又一个方面提供了一种半导体结构,其包括:具有多个沟槽的衬底;非晶衬层,设置在所述衬底的顶面上以及在所述多个沟槽中的至少一者内;和设置在所述非晶衬层上的电介质衬垫层。
在一些实施例中,所述多个沟槽包括第一组沟槽和第二组沟槽,且所述非晶衬层仅设置在所述第一组沟槽中。
在一些实施例中,所述的结构,还包括设置在所述衬底与所述电介质衬垫层之间的辅助衬里层。
在一些实施例中,所述多个沟槽从所述衬底的顶表面具有基本相同的深度。
最后所应说明的是,以上实施例仅用以说明本发明的技术方案而非限制,尽管参照以上较佳实施例对本发明进行了详细说明,本领域的普通技术人员应当理解,可以对本发明的技术方案进行修改或等同替换,而不脱离本发明技术方案的精神和范围。
Claims (10)
1.一种半导体结构,包括:
具有多个沟槽的衬底;
非晶衬层,设置在所述衬底的顶面上以及在所述多个沟槽中的至少一者内;和
设置在所述非晶衬层上的电介质衬垫层。
2.根据权利要求1所述的结构,其中,所述多个沟槽包括第一组沟槽和第二组沟槽,且所述非晶衬层仅设置在所述第一组沟槽中。
3.根据权利要求1所述的结构,还包括设置在所述衬底与所述电介质衬垫层之间的辅助衬里层。
5.根据权利要求1所述的结构,其中,所述多个沟槽从所述衬底的顶表面具有基本相同的深度。
6.一种形成氧化物的方法,包括:
在衬底的顶面上形成第一组沟槽;和
在所述衬底上进行表面处理,所述表面处理工艺包括:
在所述衬底上形成非晶层;
蚀刻所述非晶层的一部分以形成衬里层,其中所述非晶层比所述衬里层厚;和
在衬里层上设置介电材料。
7.根据权利要求6所述的方法,其特征在于,还包括:
在所述衬底的顶表面上形成第二组沟槽,
其中,所述第一组沟槽的底部与所述衬底的顶表面的距离大于所述第二组沟槽的底部与所述衬底的顶表面的距离,
其中,所述第一组沟槽的开口的宽度大于所述第二组沟槽的开口的宽度。
8.根据权利要求6所述的方法,其特征在于,其中,其中蚀刻所述非晶层的所述部分以形成所述衬里层包括使用标准清洁剂1(SC1)蚀刻剂的湿蚀刻工艺。
9.根据权利要求6所述的方法,其特征在于,其中,所述SC1蚀刻剂包括NH4OH,H2O2和去离子水中的至少一种。
10.根据权利要求6所述的方法,其特征在于,其中蚀刻所述非晶层的所述部分以形成所述衬里层包括使用氢氟酸(O3_HF)蚀刻剂的湿蚀刻工艺。
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CN1339820A (zh) * | 2000-08-17 | 2002-03-13 | 三星电子株式会社 | 防止半导体层弯曲的方法和用该方法形成的半导体器件 |
US20050186755A1 (en) * | 2004-02-19 | 2005-08-25 | Smythe John A.Iii | Sub-micron space liner and densification process |
US20150102456A1 (en) * | 2013-10-11 | 2015-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Amorphorus silicon insertion for sti-cmp planarity improvement |
CN104867860A (zh) * | 2014-02-20 | 2015-08-26 | 中芯国际集成电路制造(上海)有限公司 | 一种浅沟槽隔离结构的制作方法 |
CN207852674U (zh) * | 2017-12-07 | 2018-09-11 | 睿力集成电路有限公司 | 晶体管及存储单元阵列 |
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US8629020B2 (en) * | 2010-10-25 | 2014-01-14 | Electronics & Telecommunications Research Institute | Semiconductor device and method of fabricating the same |
US8501607B1 (en) * | 2012-11-07 | 2013-08-06 | Globalfoundries Inc. | FinFET alignment structures using a double trench flow |
US9190478B2 (en) * | 2013-12-22 | 2015-11-17 | Alpha And Omega Semiconductor Incorporated | Method for forming dual oxide trench gate power MOSFET using oxide filled trench |
US20170317166A1 (en) * | 2016-04-29 | 2017-11-02 | Globalfoundries Inc. | Isolation structures for circuits sharing a substrate |
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2019
- 2019-10-25 CN CN201911024932.9A patent/CN111354785A/zh active Pending
- 2019-10-25 US US16/663,382 patent/US20200203216A1/en not_active Abandoned
- 2019-10-25 CN CN201911025940.5A patent/CN111354676A/zh active Pending
- 2019-11-11 US US16/679,338 patent/US20200219761A1/en not_active Abandoned
Patent Citations (5)
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CN1339820A (zh) * | 2000-08-17 | 2002-03-13 | 三星电子株式会社 | 防止半导体层弯曲的方法和用该方法形成的半导体器件 |
US20050186755A1 (en) * | 2004-02-19 | 2005-08-25 | Smythe John A.Iii | Sub-micron space liner and densification process |
US20150102456A1 (en) * | 2013-10-11 | 2015-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Amorphorus silicon insertion for sti-cmp planarity improvement |
CN104867860A (zh) * | 2014-02-20 | 2015-08-26 | 中芯国际集成电路制造(上海)有限公司 | 一种浅沟槽隔离结构的制作方法 |
CN207852674U (zh) * | 2017-12-07 | 2018-09-11 | 睿力集成电路有限公司 | 晶体管及存储单元阵列 |
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CN111354676A (zh) | 2020-06-30 |
US20200203216A1 (en) | 2020-06-25 |
US20200219761A1 (en) | 2020-07-09 |
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