CN111223842A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN111223842A CN111223842A CN201911175431.0A CN201911175431A CN111223842A CN 111223842 A CN111223842 A CN 111223842A CN 201911175431 A CN201911175431 A CN 201911175431A CN 111223842 A CN111223842 A CN 111223842A
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Abstract
一种半导体装置及其制造方法,其中半导体装置的制造方法包括形成第一导电部件于介电层内。选择性地回蚀第一导电部件。形成蚀刻停止层于第一导电部件和介电层上,蚀刻停止层在第一导电部件上的高度与在介电层上的高度不同。图案化蚀刻停止层以暴露出第一导电部件的顶表面。横向蚀刻蚀刻停止层。在第一导电部件上沉积导电材料以形成第二导电部件。
Description
技术领域
本发明实施例涉及半导体技术,且特别涉及一种具有改进的电性连接的半导体装置及其制造方法。
背景技术
集成电路(IC)工业经历了指数级的发展。IC材料和设计的技术进步已经产生了好几代IC,其中每一代都比上一代具有更小,更复杂的电路。在IC发展的过程中,功能密度(即每个芯片面积的互连装置的数量)通常增加而几何尺寸(即可以使用制造工艺产生的最小元件(或线))减小。这种尺寸缩小的工艺通常会带来好处,例如提高生产效率及降低相关成本。
尺寸缩小还增加了IC工艺和制造的复杂度,而为了实现这些进步,需要在IC工艺和制造中进行类似的发展。例如,随着互连线的宽度持续缩小,导孔底部阻挡层与金属导体之间的接触面积变得越来越小,这导致导孔与金属导体之间的接触电阻更高。尤其是随着技术节点的缩小,更希望降低这种接触电阻。
发明内容
一种半导体装置制造方法,包括:形成第一导电部件于介电层内。选择性地回蚀第一导电部件。形成蚀刻停止层于第一导电部件和介电层上,蚀刻停止层在第一导电部件上的高度与在介电层上的高度不同。图案化蚀刻停止层以暴露出第一导电部件的顶表面。横向蚀刻蚀刻停止层。在第一导电部件上沉积导电材料以形成第二导电部件。
一种半导体装置制造方法,包括:执行第一蚀刻工艺以图案化介电层并暴露接触蚀刻停止层。执行第二蚀刻工艺以除去蚀刻停止层并暴露下方部件的顶表面。执行第三蚀刻工艺以横向凹蚀蚀刻停止层,并在下方部件上沉积导电材料,以形成与下方部件直接接触的导电部件。
一半导体装置包括:第一导电部件,其嵌入在第一介电层中,使得第一介电层的顶表面高于第一导电部件的顶表面。接触蚀刻停止层(CESL)设置在第一介电层上。第二导电部件嵌入在第二介电层中。第二介电层设置在CESL上,并且第二导电部件延伸穿过CESL并与第一导电部件直接接触。
附图说明
通过以下的详细描述配合说明书附图,可以更加理解本文实施例的内容。需强调的是,根据产业上的标准惯例,许多部件(feature)并未按照比例绘制。事实上,为了能清楚地讨论,各种部件的尺寸可能被任意地放大或缩小。
图1A、图1B、图1C、图1D、图1E、图1F、图1G到图1H是根据本文描述的原理的一实施例所示出在两个导电部件之间形成改进的电性连接的说明性工艺的图。
图2A到图2B是根据本文描述的原理的一实施例所示出各种下方的部件的图。
图3是根据本文描述的原理的一实施例所示出形成在下方的部件上的导电部件的更多细节的图。
图4是根据本文描述的原理的一实施例所示出用于在两个导电部件之间形成改进的电性连接的说明性的方法的流程图。
图5是根据本文描述的原理的一实施例所示出用于在两个导电部件之间形成改进的电性连接的说明性方法的流程图。
附图标记说明:
102~介电层;
104~导电部件;
106~蚀刻工艺;
108~沉积工艺;
110~CESL;
112~介电层;
114~蚀刻工艺;
115~沟槽;
116~蚀刻工艺;
118~蚀刻工艺;
120~沉积工艺;
122~导电部件;
202~栅极装置;
204~栅极装置;
302~上部;
304~中间部;
306~下部;
308~宽度;
310~宽度;
312~宽度;
400~方法;
402-412~流程;
500~方法;
502-508~流程。
具体实施方式
以下内容提供了很多不同的实施例或范例,用于实现本发明实施例的不同部件。组件和配置的具体实施例或范例描述如下,以简化本发明实施例。当然,这些仅仅是范例,并非用以限定本发明实施例。举例来说,元件尺寸并未限于所公开的范围或数值,而可取决于工艺条件及/或装置期望的特性。再者,叙述中若提及第一部件形成于第二部件之上,可能包含形成第一和第二部件直接接点的实施例,也可能包含额外的部件形成于第一和第二部件之间,使得第一和第二部件不直接接点的实施例。另外,本发明实施例可能在许多范例中重复元件符号及/或字母。这些重复是为了简化和清楚的目的,其本身并非代表所讨论各种实施例及/或配置之间有特定的关系。
再者,此处可能使用空间上的相关用语,例如“在……之下”、“在……下方”、“下方的”、“在……上方”、“上方的”和其他类似的用语可用于此,以便描述如图所示的一元件或部件与其他元件或部件之间的关系。此空间上的相关用语除了包含附图示出的方位外,也包含使用或操作中的装置的不同方位。当装置被转至其他方位时(旋转90度或其他方位),则在此所使用的空间相对描述可同样依旋转后的方位来解读。
如上所述,集成电路的缩小也增加了IC工艺和制造的复杂性,并且为了实现这些进步,在IC工艺和制造中需要进行类似的发展。例如,随着互连线的宽度持续缩小,导孔底层和金属导体之间的接触面积变得越来越小,这导致导孔和金属导体之间的接触电阻更高。尤其是随着技术节点的缩小,更希望降低这种接触电阻。根据本文所述的原理,在沉积用于导电部件之一的材料之前,通过在蚀刻停止层上进行横向凹蚀来改善两个导电部件之间的连接。这增加了两个导电部件之间的接触面积,因此减小了接触电阻。
在一实施例中,在第一介电层(例如,层间介电质(Interlayer Dielectric,ILD)层)内形成第一导电部件之后,执行选择性的蚀刻工艺以选择性地回蚀第一导电部件。接着,形成蚀刻停止层于第一导电部件及第一介电层上。然后形成第二介电层于蚀刻停止层上。然后图案化第二介电层和蚀刻停止层以暴露第一导电部件。然后,执行横向蚀刻工艺以横向蚀刻蚀刻停止层。在横向蚀刻工艺之后,形成上方导电部件于导电部件上。因为在横向蚀刻工艺期间对蚀刻停止层进行了横向蚀刻,所以下方的导电部件与新形成的导电部件之间具有更多的接触面积。这降低了下方的导电部件与新形成的导电部件之间的接触电阻。
本文说明的原理也提供其他优点。例如,蚀刻停止层的拐角(corner)保护了下方的导电部件和上方的导电部件之间的桥接。此外,由于下方的导电部件的一部分被上方的导电部件替代,因此可以减小片电阻。
图1A至图1H示出用于在两个导电部件之间形成改进的电性连接的说明性工艺。图1A显示形成在例如层间介电质(ILD)层的介电层内的导电部件104。介电层102可以由例如氮化硅的氮化物材料制成。介电层102可以形成在半导体基板上。半导体基板可以是硅基板。然而,在一些实施例中,基板可以是硅锗基板。其他类型的半导体基板也可以考虑使用。
在一实施例中,导电部件104可以是导孔接点。导孔接点是将接点(例如栅极接点或源极/漏极接点)连接到上方的导电部件(例如金属互连)的导电结构。在一些实施例中,导电部件104可以是连通到下方的金属互连层的导孔。其他类型的导电结构也可以被考虑。导电部件可以包括金属材料,例如铜、钴、镍、钨或钌等。
导电部件104可以多种方式中的一种来形成。在一实施例中,将光微影图案化工艺(photolithographic patterning process)应用于介电层102。例如,可以将光刻胶剂应用到介电层102。然后,可以通过遮罩将光刻胶剂暴露于光源。曝光后,光刻胶剂可以在显影溶液中显影。这将除去光刻胶剂的曝光部分或未曝光部分。然后,下方的介电层102可以通过光刻胶剂的曝光部分实施蚀刻工艺。蚀刻工艺在介电层102内形成沟槽。然后可以用例如金属材料的导电材料填充此沟槽以形成导电部件104。
图1B显示蚀刻工艺106,用于选择性地回蚀导电部件104。蚀刻工艺是选择性的,因为其被设计成主要除去导电部件104而基本上不影响介电层102。蚀刻工艺106可以从导电部件104除去约0.1至50nm厚的材料。在蚀刻工艺106之后,导电部件104的顶表面将低于介电层102的顶表面。在一实施例中,蚀刻工艺106可以是多种蚀刻工艺中的一种,例如蚀刻工艺106可以是湿蚀刻工艺。在一实施例中,蚀刻工艺106为干蚀刻工艺。
图1C显示沉积工艺108以形成接触蚀刻停止层(Contact Etch-Stop Layer,CESL)110。CESL 110可用于提供对随后执行的蚀刻工艺的更好控制,以避免对导电部件104或介电层102进行不必要的蚀刻工艺。CESL 110具有顶表面,其在导电部件104上方的部分低于在介电层102上方的部分。
CESL 110可以由多种材料制成。在一实施例中,CESL可以包括高介电常数材料,例如氮氧化硅(SiON)、氧化钽(Ta2O5)、氧化铝(Al2O3)、氧化锆(ZrO2)、含铝氧化物层、含氮氧化物层、氮氧化物、金属氧化物介电质、含铪氧化物、含钽氧化物、含钛氧化物、含铬氧化物、含铝氧化物、含镧氧化物或其他高介电常数材料。CESL可以是与用于形成栅极装置的介电层102或金属栅极间隔层不同的介电材料。CESL可以由多层介电层制成。
图1D显示形成在CESL 110上的第二介电层112。在一些实施例中,介电层112可以由与介电层102相同的材料制成。然而,在一些实施例中,介电层112的材料可以与介电层102不同。介电层可以包括例如氧化硅或氮化硅的低介电常数介电材料。
图1E显示蚀刻工艺114,以在第二介电层112内形成沟槽115。蚀刻工艺114可以是干蚀刻工艺。蚀刻工艺114可以使用氟基蚀刻剂。蚀刻工艺114可以被执行为光微影图案化工艺的一部分。因此,蚀刻工艺114仅施加于介电层112的某些部分。进行蚀刻工艺直到到达CESL 110。这是因为蚀刻工艺114是选择性的,并且选择了CESL和介电层112的材料,使得蚀刻工艺114除去了介电层而基本不影响CESL 110。
图1F显示另一蚀刻工艺116,以去除CESL层。在一实施例中,蚀刻工艺116为干蚀刻工艺。干蚀刻工艺是非等向性的。换句话说,蚀刻工艺在单一方向上蚀刻。蚀刻工艺116可以使用氯基蚀刻剂。蚀刻工艺116除去CESL 110以暴露导电部件104的顶表面。然而,此时导电部件104的整个顶表面没有暴露。
图1G显示另一蚀刻工艺118,蚀刻工艺118横向凹蚀CESL 110以暴露出更多导电部件的顶表面。横向蚀刻工艺可以是等向性蚀刻工艺,例如湿蚀刻工艺。在一些实施例中,蚀刻工艺118可以使用氨基蚀刻剂或标准清洁液SC1。
图1H显示沉积工艺120以在沟槽115内形成第二导电部件122。导电部件122可以包括金属材料,例如铜、钴、镍、钨或钌。因为在蚀刻工艺118期间对CESL 110进行了横向蚀刻,所以在下方的导电部件104和新形成的导电部件122之间存在更多的接触面积。这降低了下方的导电部件104和新形成的导电部件122之间的接触电阻。在一些实施例中,在形成导电部件122之后,可以执行化学机械研磨(Chemical Mechanical Polish,CMP)工艺以平坦化导电部件122和介电层112的顶表面。
因为蚀刻停止层在横向蚀刻工艺期间被横向蚀刻,所以在下方的导电部件和新形成的导电部件之间存在更多的接触面积。这降低了下方的导电部件与新形成的导电部件之间的接触电阻。此外,蚀刻停止层的拐角保护了下方的导电部件和上方的导电部件之间的桥接。此外,由于下方的导电部件的一部分被上方的导电部件替代,因此可以降低片电阻。
当使用本文所述的工艺时,CESL 110具有锥形部分,其在此锥形部分与导电部件122接触。具体而言,锥形部分从介电层102的顶表面向下朝第一导电部件104延伸。在一些实施中,锥形部分的顶点可以接触导电部件104。在一些实施中,锥形部分的顶点可以不延伸到导电部件104。
图2A-图2B显示各种下方的部件。图2A显示一示例,其中下方的导电部件是源极/漏极部件。在这种情况下,上方导电部件122可以是与栅极装置202相邻的源极/漏极接点。栅极装置202可以具有顶表面,此顶表面与上方的导电部件122的顶表面共平面或在同一水平上。在一些实施例中,源极/漏极部件可以是外延成长的源极/漏极部件。源极/漏极部件可以包括例如硅或硅锗的半导体材料。源极/漏极部件可以掺杂n型或p型掺质。
在一实施例中,在形成源极/漏极部件之后,执行选择性的蚀刻工艺以选择性地回蚀源极/漏极部件。接着,在源极/漏极部件及第一介电层上形成蚀刻停止层。然后形成第二介电层于蚀刻停止层上。然后图案化第二介电层及蚀刻停止层以暴露源极/漏极部件。然后,执行横向蚀刻工艺以横向蚀刻蚀刻停止层。横向蚀刻工艺之后,形成上方的导电部件于源极/漏极部件上。因为蚀刻停止层是在横向蚀刻工艺期间被横向蚀刻的,所以在源极/漏极部件与新形成的导电部件之间存在更多的接触面积。这降低了源极/漏极部件和新形成的导电部件之间的接触电阻。
图2B显示说明性的实施例,其中下方的导电部件是栅极装置204。在此实施例中,栅极装置204如上所述内容的被凹蚀。接着,将CESL 110层放置在凹入的栅极装置204及介电层102上方。通过将本文所述的原理应用于下方的导电部件是栅极装置的情况,可以使栅极装置204和栅极接点(例如122)之间更好地接触。
在一实施例中,在形成栅极装置于介电层(例如ILD)内之后,执行选择性的蚀刻工艺以选择性地回蚀栅极装置。接着,形成蚀刻停止层于栅极装置和第一介电层上。然后形成第二介电层于蚀刻停止层上。然后图案化第二介电层及蚀刻停止层以暴露栅极装置。然后,执行横向蚀刻工艺以横向蚀刻蚀刻停止层。横向蚀刻工艺之后,形成上方的导电部件于栅极部件上。因为蚀刻停止层是在横向蚀刻工艺期间被横向蚀刻的,所以在栅极部件和新形成的导电部件之间存在更多的接触面积。这降低了栅极部件和新形成的导电部件之间的接触电阻。
图3显示形成在下方的部件104上的导电部件的更多细节。特别地,图3显示应用本文描述的原理而产生的上方导电部件122的各种尺寸关系。在本实施例中,导电部件122具有上部302、中间部304及下部306。下部306的宽度312大于中间部304的宽度310。此外,上部302的宽度308大于中间部304的宽度310和下部306的宽度312。
图4示出用于在两个导电部件之间形成改进的电性连接的说明性的方法的流程图。根据本实施例,方法400包括用于在介电层(例如102)内形成第一导电部件(例如104)的流程402。介电层可以由例如氮化硅的氮化物材料制成。介电层可以形成在半导体基板上。半导体基板可以是硅基板。然而,在一些实施例中,基板可以是硅锗基板。其他类型的半导体基板也可以考虑。
在一实施例中,导电部件可以是导孔接点。导孔接点是将接点(例如栅极接点或源极/漏极接点)连接到上方的导电部件(例如金属互连)的导电结构。在一些实施例中,导电部件可以是到下方的金属互连层的导孔。其他类型的导电结构也可以考虑。
导电部件可以多种方式之一形成。在一实施例中,将光微影图案化工艺应用于介电层。例如,可以将光刻胶剂应用于介电层。接着,可以通过遮罩将光刻胶剂暴露于光源。曝光后,光刻胶剂可以在显影溶液中显影。这将去除光刻胶剂的曝光部分或未曝光部分。然后,下方的介电层可以通过光刻胶剂的曝光部分实施蚀刻工艺。蚀刻工艺在介电层内形成沟槽。然后此沟槽可以用例如金属材料的导电材料填充以形成导电部件。
方法400还包括用于选择性地回蚀导电部件的流程404。蚀刻工艺是选择性的,因为其被设计成主要除去导电部件而基本上不影响介电层。蚀刻工艺可以从导电部件除去约0.1至50nm厚的材料。在蚀刻工艺之后,导电部件的顶表面将低于介电层的顶表面。在一实施例中,蚀刻工艺可以是多种蚀刻工艺中的一种,例如蚀刻工艺可以是湿蚀刻工艺。在一实施例中,蚀刻工艺为干蚀刻工艺。
方法400还包括用于在导电部件和介电层上形成蚀刻停止层(例如,CESL 110)的流程406,蚀刻停止层在第一导电部件上的高度与在介电层上的高度不同。CESL可用于提供对随后执行的蚀刻工艺的更好控制,以避免对导电部件或介电层进行不必要的蚀刻工艺。CESL具有顶表面,其在导电部件上方的部分低于在介电层上方的部分。CESL可以由多种材料制成。在一实施例中,CESL可以包括高介电常数材料,例如氮氧化硅(SiON)、氧化钽(Ta2O5)、氧化铝(AL2O3)、氧化锆(ZrO2)、含铝氧化物层、含氮氧化物层、氮氧化物、金属氧化物介电质、含铪氧化物、含钽氧化物、含钛氧化物、含铬氧化物、含铝氧化物、含镧氧化物或其他高介电常数材料。CESL可以是与用于形成栅极装置的介电层或金属栅极间隔层不同的介电材料。CESL可以由多层介电层制成。
方法400进一步包括用于图案化蚀刻停止层以暴露第一导电部件的顶表面的流程408。例如,这可以通过使用蚀刻工艺(例如116)以除去CESL层来完成。在一实施例中,蚀刻工艺为干蚀刻工艺。干蚀刻工艺是非等向性的。换句话说,蚀刻工艺在单一方向上蚀刻。蚀刻工艺可以使用氯基蚀刻剂。蚀刻工艺除去CESL以暴露导电部件的顶表面。然而,此时导电部件的整个顶表面没有暴露。
方法400还包括用于横向蚀刻蚀刻停止层的流程410。这可以通过使用蚀刻工艺(例如118)以横向凹蚀CESL以暴露出更多导电部件的顶表面来完成。横向蚀刻工艺可以是等向性蚀刻工艺,例如湿蚀刻工艺。在一些实施例中,蚀刻工艺可以使用氨基蚀刻剂或标准清洁液SC1。
方法400还包括用于在第一导电部件上方沉积导电材料以形成第二导电部件的流程412。因为在横向蚀刻工艺期间对CESL进行了横向蚀刻,所以在下方的导电部件和新形成的导电部件之间存在更多的接触面积。这降低了下方的导电部件和新形成的导电部件之间的接触电阻。在一些实施例中,在形成导电部件之后,可以执行化学机械研磨(CMP)工艺以平坦化导电部件和介电层的顶表面。
图5是示出用于在两个导电部件之间形成改进的电性连接的说明性方法的流程图。根据本实施例,方法500包括用于执行第一蚀刻工艺(例如114)以图案化介电层(例如112)及暴露接触蚀刻停止层(例如110)的流程502。蚀刻工艺可以在第二介电层内形成沟槽(例如115)。第一蚀刻工艺可以是干蚀刻工艺。第一蚀刻工艺可以使用氟基蚀刻剂。第一蚀刻工艺可以被执行为光微影图案化工艺的一部分。因此,第一蚀刻工艺仅施加于介电层的某些部分。进行蚀刻工艺直到到达CESL。这是因为第一蚀刻工艺是选择性的,并且选择了CESL和介电层的材料,使得第一蚀刻工艺除去了介电层而基本不影响CESL。CESL可以由多种材料制成。在一实施例中,CESL可以包括高介电常数材料,例如氮氧化硅(SiON)、氧化钽(Ta2O5)、氧化铝(AL2O3)、氧化锆(ZrO2)、含铝氧化物层、含氮氧化物层、氮氧化物、金属氧化物介电质、含铪氧化物、含钽氧化物、含钛氧化物、含铬氧化物、含铝氧化物、含镧氧化物或其他高介电常数材料。CESL可以是与用于形成栅极装置的介电层或金属栅极间隔层不同的介电材料。CESL可以由多层介电层制成。
在一些实施例中,CESL形成在另一介电层(例如102)上。此介电层例如可以是层间介电质(ILD)层。介电层可以由例如氮化硅的氮化物材料制成。介电层可以形成在半导体基板上。半导体基板可以是硅基板。然而,在一些实施例中,基板可以是硅锗基板。其他类型的半导体基板也可以考虑使用。
在一实施例中,导电部件可以是导孔接点。导孔接点是将接点(例如栅极接点或源极/漏极接点)连接到上方的导电部件(例如金属互连)的导电结构。在一些实施例中,导电部件可以是到下方的金属互连层的导孔。其他类型的导电结构也可以被考虑。
导电部件可以多种方式中的一种来形成。在一实施例中,将光微影图案化工艺应用于介电层。例如,可以将光刻胶剂应用到介电层。然后,可以通过遮罩将光刻胶剂暴露于光源。曝光后,光刻胶剂可以在显影溶液中显影。这将除去光刻胶剂的曝光部分或未曝光部分。然后,下方的介电层可以通过光刻胶剂的曝光部分实施蚀刻工艺。蚀刻工艺在介电层内形成沟槽。然后可以用例如金属材料的导电材料填充此沟槽以形成导电部件。
方法500还包括用于执行第二蚀刻工艺(例如116)以除去蚀刻停止层并暴露下方部件的顶表面的流程504。在一实施例中,第二蚀刻工艺为干蚀刻工艺。干蚀刻工艺是非等向性的。换句话说,蚀刻工艺在单一方向上蚀刻。第二蚀刻工艺可以使用氯基蚀刻剂。第二蚀刻工艺除去CESL以暴露导电部件的顶表面。然而,此时导电部件的整个顶表面没有暴露。
方法500还包括用于执行第三蚀刻工艺以横向凹蚀(横向凹陷,laterallyrecess)蚀刻停止层的流程506。这暴露出导电部件的更多顶表面。横向蚀刻工艺可以是等向性蚀刻工艺,例如湿蚀刻工艺。在一些实施例中,第三蚀刻工艺可以使用氨基蚀刻剂或标准清洁液SC1。
方法500还包括用于在下方部件上沉积导电部件以产生与下方部件直接接触的导电部件的流程508。因为在横向蚀刻工艺期间对CESL进行了横向蚀刻,所以在下方的导电部件和新形成的导电部件之间存在更多的接触面积。这降低了下方的导电部件和新形成的导电部件之间的接触电阻。在一些实施例中,在形成导电部件之后,可以执行化学机械研磨(CMP)工艺以平坦化导电部件和介电层的顶表面。
通过应用本文描述的原理,可以实现改进的方法和结构。例如,由于在横向蚀刻工艺期间对蚀刻停止层进行了横向蚀刻,因此在下方的导电部件与新形成的导电部件之间具有更多的接触面积。这降低了下方的导电部件与新形成的导电部件之间的接触电阻。此外,蚀刻停止层的拐角保护了下方的导电部件和上方的导电部件之间的桥接。此外,由于下方的导电部件的一部分被上方的导电部件替代,因此可以降低片电阻。
根据本文的一些实施例,一种半导体装置制造方法,包括:形成第一导电部件于介电层内。选择性地回蚀第一导电部件。形成蚀刻停止层于第一导电部件和介电层上,蚀刻停止层在第一导电部件上的高度与在介电层上的高度不同。图案化蚀刻停止层以暴露出第一导电部件的顶表面。横向蚀刻蚀刻停止层。在第一导电部件上沉积导电材料以形成第二导电部件。
在一实施例中,第一导电部件包括导孔接点。
在一实施例中,第一导电部件包括后端工艺(Back End of Line,BEOL)导孔。
在一实施例中,第一导电部件包括栅极装置。
在一实施例中,第一导电部件包括源极/漏极部件。
在一实施例中,图案化蚀刻停止层包括第一蚀刻工艺,第一蚀刻工艺使用氟基蚀刻剂来除去介电层。
在一实施例中,图案化蚀刻停止层包括第二蚀刻工艺,第二蚀刻工艺使用氯基蚀刻剂来除去蚀刻停止层。
在一实施例中,横向蚀刻蚀刻停止层包括湿蚀刻工艺。
在一实施例中,选择性地回蚀第一导电部件除去约0.1-50纳米的材料。
在一实施例中,第二导电部件具有下部、中间部及上部,中间部比下部窄,上部比中间部及下部宽。
根据本文的一些实施例,一种半导体装置制造方法,包括:执行第一蚀刻工艺以图案化介电层并暴露接触蚀刻停止层。执行第二蚀刻工艺以除去蚀刻停止层并暴露下方部件的顶表面。执行第三蚀刻工艺以横向凹蚀蚀刻停止层,并在下方部件上沉积导电材料,以形成与下方部件直接接触的导电部件。
在一实施例中,第一蚀刻工艺使用氟基蚀刻剂。
在一实施例中,第二蚀刻工艺使用氯基蚀刻剂
在一实施例中,第三蚀刻工艺使用氨。
在一实施例中,在执行第一蚀刻工艺之前,先回蚀下方部件。
在一实施例中,在回蚀下方部件之后,沉积接触蚀刻停止层。
在一实施例中,沉积介电层于蚀刻停止层上。
根据本文的一些实施例,一种半导体装置包括:第一导电部件,其嵌入在第一介电层中,使得第一介电层的顶表面高于第一导电部件的顶表面。接触蚀刻停止层(CESL)设置在第一介电层上。第二导电部件嵌入在第二介电层中。第二介电层设置在CESL上,并且第二导电部件延伸穿过CESL并与第一导电部件直接接触。
在一实施例中,第二导电部件具有上部、中间部及下部,其中中间部比下部窄。
在一实施例中,上部比中间部及下部宽。
以上概述数个实施例的部件,以便在本发明所属技术领域中技术人员可以更加理解本发明实施例的观点。在本发明所属技术领域中技术人员应理解,他们能轻易地以本发明实施例为基础,设计或修改其他工艺和结构,以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域中技术人员也应理解,此类等效的结构并无悖离本发明的构思与范围,且他们能在不违背本发明的构思和范围下,做各式各样的改变、取代和替换。因此,本发明的保护范围当视权利要求所界定为准。
Claims (1)
1.一种半导体装置的制造方法,包括:
形成一第一导电部件于一介电层内;
选择性地回蚀该第一导电部件;
形成一蚀刻停止层于该第一导电部件和该介电层上,该蚀刻停止层在该第一导电部件上的高度与在该介电层上的高度不同;
图案化该蚀刻停止层以暴露出该第一导电部件的一顶表面;
横向蚀刻该蚀刻停止层;以及
在该第一导电部件上沉积一导电材料以形成一第二导电部件。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1913128A (zh) * | 2005-08-06 | 2007-02-14 | 三星电子株式会社 | 双金属镶嵌金属布线图案的形成方法和形成的布线图案 |
CN101231949A (zh) * | 2007-01-24 | 2008-07-30 | 国际商业机器公司 | 提高两个不同层之间粘附强度的半导体结构和方法 |
US20150364420A1 (en) * | 2014-06-16 | 2015-12-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Interconnect structure with footing region |
US20160365446A1 (en) * | 2015-06-11 | 2016-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd | Fin field effect transistor (finfet) device structure with stop layer and method for forming the same |
CN106298733A (zh) * | 2015-06-26 | 2017-01-04 | 台湾积体电路制造股份有限公司 | 具有导线上方的蚀刻停止层的互连结构 |
CN107342259A (zh) * | 2016-04-28 | 2017-11-10 | 台湾积体电路制造股份有限公司 | 半导体装置的形成方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001308181A (ja) * | 2000-04-27 | 2001-11-02 | Nec Corp | 半導体装置とその製造方法 |
KR100366635B1 (ko) * | 2000-11-01 | 2003-01-09 | 삼성전자 주식회사 | 반도체 소자의 금속 배선 및 그 제조방법 |
US6620732B1 (en) * | 2000-11-17 | 2003-09-16 | Newport Fab, Llc | Method for controlling critical dimension in a polycrystalline silicon emitter and related structure |
KR100467023B1 (ko) * | 2002-10-31 | 2005-01-24 | 삼성전자주식회사 | 자기 정렬 접촉 구조 및 그 형성 방법 |
DE10334240A1 (de) * | 2003-07-28 | 2005-02-24 | Robert Bosch Gmbh | Verfahren zur Herstellung eines mikromechanischen Bauteils vorzugsweise für fluidische Anwendungen und Mikropumpe mit einer Pumpmembran aus einer Polysiliciumschicht |
US7247569B2 (en) * | 2003-12-02 | 2007-07-24 | International Business Machines Corporation | Ultra-thin Si MOSFET device structure and method of manufacture |
US8164190B2 (en) * | 2009-06-25 | 2012-04-24 | International Business Machines Corporation | Structure of power grid for semiconductor devices and method of making the same |
US8390000B2 (en) * | 2009-08-28 | 2013-03-05 | Transphorm Inc. | Semiconductor devices with field plates |
US8227339B2 (en) * | 2009-11-02 | 2012-07-24 | International Business Machines Corporation | Creation of vias and trenches with different depths |
US8614126B1 (en) * | 2012-08-15 | 2013-12-24 | Sandisk Technologies Inc. | Method of making a three-dimensional memory array with etch stop |
KR20160019253A (ko) * | 2014-08-11 | 2016-02-19 | 에스케이하이닉스 주식회사 | 전자 장치 |
US9536826B1 (en) * | 2015-06-15 | 2017-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (finFET) device structure with interconnect structure |
US10566232B2 (en) * | 2017-05-18 | 2020-02-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Post-etch treatment of an electrically conductive feature |
US10141260B1 (en) * | 2017-05-26 | 2018-11-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure and method for forming the same |
US10163651B1 (en) * | 2017-09-28 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method to expose memory cells with different sizes |
US10950497B2 (en) | 2018-11-26 | 2021-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electrical connection for semiconductor devices |
-
2019
- 2019-04-01 US US16/371,780 patent/US10950497B2/en active Active
- 2019-11-26 TW TW108142980A patent/TWI840458B/zh active
- 2019-11-26 CN CN201911175431.0A patent/CN111223842A/zh active Pending
-
2021
- 2021-03-15 US US17/201,637 patent/US11508616B2/en active Active
-
2022
- 2022-11-18 US US18/057,158 patent/US11955380B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1913128A (zh) * | 2005-08-06 | 2007-02-14 | 三星电子株式会社 | 双金属镶嵌金属布线图案的形成方法和形成的布线图案 |
CN101231949A (zh) * | 2007-01-24 | 2008-07-30 | 国际商业机器公司 | 提高两个不同层之间粘附强度的半导体结构和方法 |
US20150364420A1 (en) * | 2014-06-16 | 2015-12-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Interconnect structure with footing region |
US20160365446A1 (en) * | 2015-06-11 | 2016-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd | Fin field effect transistor (finfet) device structure with stop layer and method for forming the same |
CN106298733A (zh) * | 2015-06-26 | 2017-01-04 | 台湾积体电路制造股份有限公司 | 具有导线上方的蚀刻停止层的互连结构 |
CN107342259A (zh) * | 2016-04-28 | 2017-11-10 | 台湾积体电路制造股份有限公司 | 半导体装置的形成方法 |
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