CN111180524A - 薄膜晶体管、显示面板及其制备方法、显示装置 - Google Patents
薄膜晶体管、显示面板及其制备方法、显示装置 Download PDFInfo
- Publication number
- CN111180524A CN111180524A CN202010070957.9A CN202010070957A CN111180524A CN 111180524 A CN111180524 A CN 111180524A CN 202010070957 A CN202010070957 A CN 202010070957A CN 111180524 A CN111180524 A CN 111180524A
- Authority
- CN
- China
- Prior art keywords
- metal
- layer
- metal oxide
- hole
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 46
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 123
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 122
- 229910052751 metal Inorganic materials 0.000 claims abstract description 107
- 239000002184 metal Substances 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims abstract description 6
- 238000002161 passivation Methods 0.000 claims description 17
- 239000010408 film Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 229910021542 Vanadium(IV) oxide Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- GRUMUEUJTSXQOI-UHFFFAOYSA-N vanadium dioxide Chemical compound O=[V]=O GRUMUEUJTSXQOI-UHFFFAOYSA-N 0.000 claims description 4
- 230000008859 change Effects 0.000 abstract description 11
- 230000004044 response Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract 1
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Abstract
本发明涉及电子显示技术领域,公开了一种薄膜晶体管、显示面板及其制备方法、显示装置,该薄膜晶体管包括衬底基板、栅极金属、栅极、有源层;位于有源层背离衬底基板一侧、第一金属氧化物和第二金属氧化物;先给予栅极一个较高的电压,第一金属氧化物和第二金属氧化物相变为导电状态,沟道长度减小,且减小了源漏极层整体的电阻,由漏极端流出的电流变大,提高了薄膜晶体管的性能。且相变过程中第一金属和第二金属会吸收因对栅极施加的高电压而产生的热量,对热量进行了再利用。再给予栅极一个较小的电压,薄膜晶体管达到相变发生前的光源或显示的响应亮度。此时线路的电流负载降低,提高了薄膜晶体管使用寿命的同时,还起到了节能的作用。
Description
技术领域
本发明涉及电子显示的技术领域,尤其是涉及一种薄膜晶体管、显示面板及其制备方法、显示装置。
背景技术
在显示、光源以及电子领域,器件都存在着高能耗的问题;且由于器件或产品本身容易发热,促使了器件的老化速率过快,降低其使用寿命。
因此,降低器件及产品的能耗,延长其使用寿命成为现代社会显示、光源电子产品开发的主流方向之一。
发明内容
本发明提供了一种薄膜晶体管、显示面板及其制备方法、显示装置,上述薄膜晶体管提高了薄膜晶体管的性能、对生成的无用的热量进行了再利用、提高了薄膜晶体管使用寿命、且起到了节能的作用。
为达到上述目的,本发明提供以下技术方案:
一种薄膜晶体管,包括衬底基板、位于衬底基板一侧的栅极金属、位于栅极金属背离衬底基板一侧的栅极绝缘层,还包括:位于栅极绝缘层背离衬底基板一侧的有源层;位于有源层背离衬底基板一侧、且同层设置的第一金属氧化物和第二金属氧化物,第一金属氧化物设置有第一过孔,第二金属氧化物设置有第二过孔;位于第一金属氧化物和第二金属氧化物背离衬底基板一侧、且同层设置的源极金属和漏极金属;源极金属与第一金属氧化物连接、且通过第一过孔与有源层连接;漏极金属与第二金属氧化物连接、且通过第二过孔与有源层连接;第一金属氧化物和第二金属氧化物能够在温度上升至预定值时由绝缘状态相变为导电状态。
本发明提供的薄膜晶体管,在薄膜晶体管的温度小于预定值时,第一金属氧化物和第二金属氧化物均处于绝缘状态,此时薄膜晶体管的沟道长度为:第一金属氧化物与有源层接触的部位靠近第二金属氧化物的一侧,到第二金属氧化物与有源层接触的部位靠近第一金属氧化物的一侧之间的距离。工作时,先给予栅极一个较高的电压,直到薄膜晶体管的温度上升至预定值时,第一金属氧化物和第二金属氧化物均发生晶格相变,由绝缘状态相变为导电状态,则此时源极金属和第一金属氧化物共同构成薄膜晶体管的源极结构,漏极金属和第二金属氧化物共同构成薄膜晶体管的漏极结构,因此,此时薄膜晶体管的沟道长度为:第一金属氧化物靠近第二金属氧化物的一端到第二金属氧化物靠近第一金属氧化物的一端之间的距离。然后再给予栅极一个较小的电压,以令薄膜晶体管达到相变发生前的光源或显示的响应亮度。
这种设置方式,由于当温度上升至预定值时,第一金属氧化物和第二金属氧化物均由绝缘状态相变为导电状态,且源漏金属层下端对应薄膜晶体管走线区域的部分均设置有第一金属氧化物和第二金属氧化物,因此,薄膜晶体管的沟道长度减小,且减小了源漏极层整体的电阻,由漏极端流出的电流变大,提高了薄膜晶体管的性能。另外,相变过程中第一金属和第二金属会吸收因对栅极施加的高电压而产生的热量,对生成的无用的热量进行了再利用,且最终给予栅极一个较小的电压,薄膜晶体管还是会恢复到相变发生前的光源或显示的响应亮度,此时线路的电流负载降低,提高了薄膜晶体管使用寿命的同时,还起到了节能的作用。
优选地,第一金属氧化物和第二金属氧化物材质均为二氧化钒;预定值为68℃。
优选地,第一金属氧化物和第二金属氧化物均可掺杂稀有金属。
一种显示面板,包括上述任一种的薄膜晶体管,显示面板还包括:位于源极金属和漏极金属背离衬底基板一侧的钝化层;位于钝化层背离衬底基板一侧的有机膜层。
优选地,显示面板还包括位于有机膜层背离衬底基板一侧的阳极金属层;钝化层设置有第三过孔,有机膜层设置有第四过孔,第三过孔与第四过孔连通,且阳极金属层通过第三过孔和第四过孔与漏极金属连接。
优选地,显示面板还包括:位于阳极金属层背离衬底基板一侧的阴极金属层;位于阳极金属层与阴极金属层之间的发光层。
一种显示装置,包括上述任一种的显示面板。
一种应用于上述任一种的显示面板的制备方法,包括如下步骤:提供衬底基板,在衬底基板上依层制备栅极金属、栅极绝缘层、有源层以及金属氧化物层;对金属氧化物层刻蚀图案化以形成第一过孔和第二过孔;在金属氧化物层背离衬底基板的一侧制备源漏金属层,并通过构图工艺形成源极金属图形以及漏级金属图形,其中,源极金属图形通过第一过孔与有源层连接,漏极金属图形通过第二过孔与有源层连接,金属氧化物层位于第一过孔和第二过孔之间的部位露出;对金属氧化物层的露出部分刻蚀图案化,以将其分隔为第一金属氧化物和第二金属氧化物,其中,第一过孔位于第一金属氧化物,第二过孔位于第二金属氧化物;在第一金属氧化物和第二金属氧化物背离衬底基板的一侧依层制备钝化层、有机膜层和阳极金属层,其中,钝化层设置有第三过孔,有机膜层设置有第四过孔,第三过孔与第四过孔连通,阳极金属层通过第三过孔和第四过孔与漏极金属连接;在阳极金属层背离衬底基板一侧依层制备发光层和阴极金属层;对栅极金属施加电压,以获得能够发光的显示面板。
附图说明
图1为本发明实施例提供的薄膜晶体管的结构示意图;
图2为本发明实施例提供的显示面板的结构示意图;
图3为本发明实施例提供的显示面板的制备方法的流程图;
图4-图10为本发明实施例提供的显示面板的制备方法对应的各步骤的结构示意图。
图标:1-衬底基板;2-栅极金属;3-栅极绝缘层;4-有源层;5-第一金属氧化物;6-第二金属氧化物;7-第一过孔;8-第二过孔;9-源极金属;10-漏极金属;11-钝化层;12-有机膜层;13-阳极金属层;14-阴极金属层;15-发光层;16-金属氧化物层。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
图1为本发明实施例提供的薄膜晶体管的结构示意图,如图1所示,本发明实施例提供的薄膜晶体管,包括衬底基板1、位于衬底基板1一侧的栅极金属2、位于栅极金属2背离衬底基板1一侧的栅极绝缘层3,还包括:位于栅极绝缘层3背离衬底基板1一侧的有源层4;位于有源层4背离衬底基板1一侧、且同层设置的第一金属氧化物5和第二金属氧化物6,第一金属氧化物5设置有第一过孔7,第二金属氧化物6设置有第二过孔8;位于第一金属氧化物5和第二金属氧化物6背离衬底基板1一侧、且同层设置的源极金属9和漏极金属10;源极金属9与第一金属氧化物5连接、且通过第一过孔7与有源层4连接;漏极金属10与第二金属氧化物6连接、且通过第二过孔8与有源层4连接;第一金属氧化物5和第二金属氧化物6能够在温度上升至预定值时由绝缘状态相变为导电状态。
本发明实施例提供的薄膜晶体管,在薄膜晶体管的温度小于预定值时,第一金属氧化物5和第二金属氧化物6均处于绝缘状态,此时薄膜晶体管的沟道长度为:第一金属氧化物5与有源层4接触的部位靠近第二金属氧化物6的一侧,到第二金属氧化物6与有源层4接触的部位靠近第一金属氧化物5的一侧之间的距离(即图1所示的L1)。工作时,先给予栅极一个较高的电压,直到薄膜晶体管的温度上升至预定值时,第一金属氧化物5和第二金属氧化物6均发生晶格相变,由绝缘状态相变为导电状态,则此时源极金属9和第一金属氧化物5共同构成薄膜晶体管的源极结构,漏极金属10和第二金属氧化物6共同构成薄膜晶体管的漏极结构,因此,此时薄膜晶体管的沟道长度为:第一金属氧化物5靠近第二金属氧化物6的一端到第二金属氧化物6靠近第一金属氧化物5的一端之间的距离(即图1所示的L2,可知L2小于L1)。然后再给予栅极一个较小的电压,以令薄膜晶体管达到相变发生前的光源或显示的响应亮度。
这种设置方式,由于当温度上升至预定值时,第一金属氧化物5和第二金属氧化物6均由绝缘状态相变为导电状态,且源漏金属层下端对应薄膜晶体管走线区域的部分均设置有第一金属氧化物5和第二金属氧化物6,因此,薄膜晶体管的沟道长度减小,且减小了源漏极层整体的电阻,由漏极端流出的电流变大,提高了薄膜晶体管的性能。另外,相变过程中第一金属和第二金属会吸收因对栅极施加的高电压而产生的热量,对生成的无用的热量进行了再利用,且最终给予栅极一个较小的电压,薄膜晶体管还是会恢复到相变发生前的光源或显示的响应亮度,此时线路的电流负载降低,提高了薄膜晶体管使用寿命的同时,还起到了节能的作用。
优选地,第一金属氧化物5和第二金属氧化物6材质均为二氧化钒;预定值为68℃。
第一金属氧化物5和第二金属氧化物6均可掺杂稀有金属。
本实施例中,稀有金属可为锗,锗金属能够调节二氧化钒的相变温度,便于满足不同环境温度情况下对第一金属氧化物5和第二金属氧化物6相变所需温度的调节,提高了工作效率。
图2为本发明实施例提供的显示面板的结构示意图,如图2所示,本发明实施例还提供了一种显示面板,包括上述任一种的薄膜晶体管,显示面板还包括:位于源极金属9和漏极金属10背离衬底基板1一侧的钝化层11;位于钝化层11背离衬底基板1一侧的有机膜层12。
如图2所示,显示面板还包括位于有机膜层12背离衬底基板1一侧的阳极金属层13;钝化层11设置有第三过孔,有机膜层12设置有第四过孔,第三过孔与第四过孔连通,且阳极金属层13通过第三过孔和第四过孔与漏极金属10连接。
如图2所示,显示面板还包括:位于阳极金属层13背离衬底基板1一侧的阴极金属层14;位于阳极金属层13与阴极金属层14之间的发光层15。
本发明实施例还提供了一种显示装置,包括上述任一种的显示面板。
图3为本发明实施例提供的显示面板的制备方法的流程图,图4-图10为本发明实施例提供的显示面板的制备方法对应的各步骤的结构示意图;如图3-图10所示,本发明实施例还提供了一种应用于上述任一种的显示面板的制备方法,包括如下步骤:
如图3和图4所示,步骤S101,提供衬底基板1,在衬底基板1上依层制备栅极金属2、栅极绝缘层3、有源层4以及金属氧化物层16。其中,可在衬底基板1上用物理气相沉积法制备栅极金属2并图案化,用等离子体增强化学气相沉积法制备栅极绝缘层3,栅极绝缘层3的材质可选用氧化硅,用等离子体增强化学气相沉积法制备有源层4,用物理气相沉积法制备金属氧化物层16。
如图3和图5所示,步骤S102,对金属氧化物层16刻蚀图案化以形成第一过孔7和第二过孔8。
如图3和图6所示,步骤S103,在金属氧化物层16背离衬底基板1的一侧制备源漏金属层,并通过构图工艺形成源极金属9图形以及漏级金属图形,其中,源极金属9图形通过第一过孔7与有源层4连接,漏极金属10图形通过第二过孔8与有源层4连接,金属氧化物层16位于第一过孔7和第二过孔8之间的部位露出。其中,源漏金属层的材质可选用金属铜。
如图3和图7所示,步骤S104,对金属氧化物层16的露出部分刻蚀图案化,以将其分隔为第一金属氧化物5和第二金属氧化物6,其中,第一过孔7位于第一金属氧化物5,第二过孔8位于第二金属氧化物6。
如图3和图8所示,步骤S105,在第一金属氧化物5和第二金属氧化物6背离衬底基板1的一侧依层制备钝化层11、有机膜层12和阳极金属层13,其中,钝化层11设置有第三过孔,有机膜层12设置有第四过孔,第三过孔与第四过孔连通,阳极金属层13通过第三过孔和第四过孔与漏极金属10连接。钝化层11可用物理气相沉积法制备。
如图3和图9所示,步骤S106,在阳极金属层13背离衬底基板1一侧依层制备发光层15和阴极金属层14。其中,可用蒸镀设备蒸镀发光层15、用溅射法制备阴极金属层14。
如图3和图10所示,步骤S107,对栅极金属2施加电压,以获得能够发光的显示面板。
显然,本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样,倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内,则本申请也意图包含这些改动和变型在内。
Claims (8)
1.一种薄膜晶体管,包括衬底基板、位于衬底基板一侧的栅极金属、位于所述栅极金属背离所述衬底基板一侧的栅极绝缘层,其特征在于,还包括:
位于所述栅极绝缘层背离所述衬底基板一侧的有源层;
位于所述有源层背离所述衬底基板一侧、且同层设置的第一金属氧化物和第二金属氧化物,所述第一金属氧化物设置有第一过孔,所述第二金属氧化物设置有第二过孔;
位于所述第一金属氧化物和所述第二金属氧化物背离所述衬底基板一侧、且同层设置的源极金属和漏极金属;所述源极金属与所述第一金属氧化物连接、且通过所述第一过孔与所述有源层连接;所述漏极金属与所述第二金属氧化物连接、且通过所述第二过孔与所述有源层连接;所述第一金属氧化物和所述第二金属氧化物能够在温度上升至预定值时由绝缘状态相变为导电状态。
2.根据权利要求1所述的薄膜晶体管,其特征在于,所述第一金属氧化物和所述第二金属氧化物材质均为二氧化钒;
所述预定值为68℃。
3.根据权利要求2所述的薄膜晶体管,其特征在于,所述第一金属氧化物和所述第二金属氧化物均可掺杂稀有金属。
4.一种显示面板,其特征在于,包括如权利要求1-3任一项所述的薄膜晶体管,所述显示面板还包括:
位于所述源极金属和漏极金属背离所述衬底基板一侧的钝化层;
位于所述钝化层背离所述衬底基板一侧的有机膜层。
5.根据权利要求4所述的显示面板,其特征在于,所述显示面板还包括位于所述有机膜层背离所述衬底基板一侧的阳极金属层;
所述钝化层设置有第三过孔,所述有机膜层设置有第四过孔,所述第三过孔与所述第四过孔连通,且所述阳极金属层通过所述第三过孔和所述第四过孔与所述漏极金属连接。
6.根据权利要求5所述的显示面板,其特征在于,所述显示面板还包括:
位于所述阳极金属层背离所述衬底基板一侧的阴极金属层;
位于所述阳极金属层与所述阴极金属层之间的发光层。
7.一种显示装置,其特征在于,包括如权利要求4-6任一项所述的显示面板。
8.一种应用于如权利要求4-6任一项所述的显示面板的制备方法,其特征在于,包括如下步骤:
提供衬底基板,在衬底基板上依层制备栅极金属、栅极绝缘层、有源层以及金属氧化物层;
对金属氧化物层刻蚀图案化以形成第一过孔和第二过孔;
在金属氧化物层背离衬底基板的一侧制备源漏金属层,并通过构图工艺形成源极金属图形以及漏级金属图形;其中,源极金属图形通过第一过孔与有源层连接,漏极金属图形通过第二过孔与有源层连接,金属氧化物层位于第一过孔和第二过孔之间的部位露出;
对金属氧化物层的露出部分刻蚀图案化,以将其分隔为第一金属氧化物和第二金属氧化物;其中,第一过孔位于第一金属氧化物,第二过孔位于第二金属氧化物;
在第一金属氧化物和第二金属氧化物背离衬底基板的一侧依层制备钝化层、有机膜层和阳极金属层;其中,钝化层设置有第三过孔,有机膜层设置有第四过孔,第三过孔与第四过孔连通,阳极金属层通过第三过孔和第四过孔与漏极金属连接;
在阳极金属层背离衬底基板一侧依层制备发光层和阴极金属层;
对栅极金属施加电压,以获得能够发光的显示面板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010070957.9A CN111180524B (zh) | 2020-01-21 | 2020-01-21 | 薄膜晶体管、显示面板及其制备方法、显示装置 |
US16/936,447 US11335710B2 (en) | 2020-01-21 | 2020-07-23 | Thin film transistor, display panel and preparation method thereof, and display apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010070957.9A CN111180524B (zh) | 2020-01-21 | 2020-01-21 | 薄膜晶体管、显示面板及其制备方法、显示装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111180524A true CN111180524A (zh) | 2020-05-19 |
CN111180524B CN111180524B (zh) | 2023-04-18 |
Family
ID=70654842
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010070957.9A Active CN111180524B (zh) | 2020-01-21 | 2020-01-21 | 薄膜晶体管、显示面板及其制备方法、显示装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US11335710B2 (zh) |
CN (1) | CN111180524B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023087373A1 (zh) * | 2021-11-18 | 2023-05-25 | 武汉华星光电半导体显示技术有限公司 | 显示面板及其制作方法、移动终端 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114823913A (zh) * | 2022-04-14 | 2022-07-29 | 广州华星光电半导体显示技术有限公司 | 显示面板及其制作方法、移动终端 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1812124A (zh) * | 2005-12-05 | 2006-08-02 | 复旦大学 | 多值相变存储器的实现方法 |
KR20080046454A (ko) * | 2006-11-22 | 2008-05-27 | 엘지디스플레이 주식회사 | 박막 트랜지스터 어레이 기판 및 그 제조 방법 |
US20090146141A1 (en) * | 2007-12-06 | 2009-06-11 | Kibong Song | Method for manufacturing n-type and p-type chalcogenide material, doped homojunction chalcogenide thin film transistor and method of fabricating the same |
CN103354218A (zh) * | 2013-06-28 | 2013-10-16 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法和显示装置 |
CN104517858A (zh) * | 2013-09-27 | 2015-04-15 | 英特尔公司 | 混合相场效应晶体管 |
JP2015216241A (ja) * | 2014-05-12 | 2015-12-03 | 株式会社アルバック | 機能性素子、二酸化バナジウム薄膜製造方法 |
CN107851713A (zh) * | 2014-10-17 | 2018-03-27 | 株式会社丰田中央研究所 | 电子装置 |
-
2020
- 2020-01-21 CN CN202010070957.9A patent/CN111180524B/zh active Active
- 2020-07-23 US US16/936,447 patent/US11335710B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1812124A (zh) * | 2005-12-05 | 2006-08-02 | 复旦大学 | 多值相变存储器的实现方法 |
KR20080046454A (ko) * | 2006-11-22 | 2008-05-27 | 엘지디스플레이 주식회사 | 박막 트랜지스터 어레이 기판 및 그 제조 방법 |
US20090146141A1 (en) * | 2007-12-06 | 2009-06-11 | Kibong Song | Method for manufacturing n-type and p-type chalcogenide material, doped homojunction chalcogenide thin film transistor and method of fabricating the same |
CN103354218A (zh) * | 2013-06-28 | 2013-10-16 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法和显示装置 |
CN104517858A (zh) * | 2013-09-27 | 2015-04-15 | 英特尔公司 | 混合相场效应晶体管 |
JP2015216241A (ja) * | 2014-05-12 | 2015-12-03 | 株式会社アルバック | 機能性素子、二酸化バナジウム薄膜製造方法 |
CN107851713A (zh) * | 2014-10-17 | 2018-03-27 | 株式会社丰田中央研究所 | 电子装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023087373A1 (zh) * | 2021-11-18 | 2023-05-25 | 武汉华星光电半导体显示技术有限公司 | 显示面板及其制作方法、移动终端 |
Also Published As
Publication number | Publication date |
---|---|
US11335710B2 (en) | 2022-05-17 |
US20210225886A1 (en) | 2021-07-22 |
CN111180524B (zh) | 2023-04-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10916185B1 (en) | Array substrate, display panel, display device and array-substrate manufacturing method | |
CN103715228B (zh) | 阵列基板及其制造方法、显示装置 | |
KR100579182B1 (ko) | 유기 전계 발광 표시 장치의 제조 방법 | |
CN109560141B (zh) | 薄膜晶体管、发光装置及其制造方法 | |
CN111180524B (zh) | 薄膜晶体管、显示面板及其制备方法、显示装置 | |
CN107331669A (zh) | Tft驱动背板的制作方法 | |
CN109599419A (zh) | 一种阵列基板及其制造方法 | |
US10396209B2 (en) | Thin film transistor comprising light shielding layers, array substrate and manufacturing processes of them | |
CN103383989B (zh) | 像素结构的制造方法及其结构 | |
CN110660846B (zh) | 薄膜晶体管及制作方法、发光装置 | |
CN105118929A (zh) | 电极结构和有机发光单元及其制造方法 | |
CN208570607U (zh) | 一种布线结构、阵列基板及显示装置 | |
KR100946809B1 (ko) | 박막트랜지스터 및 그의 제조방법 | |
CN102800708B (zh) | 半导体元件及其制作方法 | |
KR20070024016A (ko) | 박막트랜지스터 및 그 제조 방법 | |
CN113066835A (zh) | 发光面板及其制备方法、发光装置 | |
KR20020050085A (ko) | 박막 트랜지스터 | |
CN111092077B (zh) | 双薄膜晶体管及其制备方法、显示面板 | |
CN108660458B (zh) | 金属膜蚀刻液组合物及利用其的导电图案形成方法 | |
JP2018509761A (ja) | 共平面型酸化物半導体tft基板構造及びその製作方法 | |
JP4244525B2 (ja) | 薄膜トランジスタ基板の製造方法 | |
CN108183074B (zh) | 薄膜晶体管及其制备方法、阵列基板和显示面板 | |
CN111048593A (zh) | 一种薄膜晶体管及其制造方法 | |
CN112002711A (zh) | 阵列基板及其制备方法 | |
CN113224172B (zh) | 薄膜晶体管及其制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |