CN111106065B - 具有界面层的栅极结构和集成电路的制造方法 - Google Patents

具有界面层的栅极结构和集成电路的制造方法 Download PDF

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CN111106065B
CN111106065B CN201910538003.3A CN201910538003A CN111106065B CN 111106065 B CN111106065 B CN 111106065B CN 201910538003 A CN201910538003 A CN 201910538003A CN 111106065 B CN111106065 B CN 111106065B
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layer
capping layer
forming
annealing process
capping
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CN111106065A (zh
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程仲良
吴俊毅
方子韦
赵皇麟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供一种形成集成电路器件的方法的示例，其中，所述集成电路器件具有设置在沟道区和栅极介电质之间界面层。在一些示例中，所述方法包括接收具有衬底和鳍的工件，所述鳍具有设置在所述衬底上的沟道区。界面层形成在所述鳍的沟道区上，且栅极介电层形成在所述界面层上。第一覆盖层形成在所述栅极介电层上，且第二覆盖层形成在所述第一覆盖层上。在所述工件上执行退火工艺，所述退火工艺被配置为使第一材料从所述第一覆盖层扩散到所述栅极介电层中。可在制造工具的同一腔室中执行所述第一覆盖层和第二覆盖层的形成和退火工艺。本发明的实施例还提供了具有界面层的栅极结构和集成电路的制造方法。

Description

具有界面层的栅极结构和集成电路的制造方法
技术领域
本发明的实施例一般地涉及半导体技术领域，更具体地，涉及集成电路的制造方法。
背景技术
半导体集成电路(IC)行业经历了快速增长。随着IC的发展，功能密度(即，单位芯片面积的互连器件的数量)通常会增加，而几何尺寸(即，可使用制造工艺产生的最小部件(或线))减小。这种按比例缩小过程通常通过提高生产效率和降低相关成本来提供益处。然而，每次减小尺寸都会给设计和制造带来更大的挑战。通过这些领域的进步，正在精确和可靠地制造越来越复杂的设计。
例如，用于形成晶体管的栅极结构的材料和技术不断发展。高水平的栅极结构可包括导体和栅极介电质，该栅极介电质将导体与晶体管的沟道区分开。一种常见的栅极介电质是氧化硅。虽然减薄氧化硅栅极介电质改善了沟道电流并提高了晶体管的开关速度，但是更薄的栅极介电质也更容易受隧穿影响并具有更大的栅极泄漏。由于这些原因和其他原因，通过高k介电材料部分地取代氧化硅栅极介电质，以获得更好的晶体管性能。然而，特别是在高k介电材料与其他材料交界的情况下，该高k介电材料可能难以制造并易于出现缺陷。
发明内容
根据本发明的一方面，提供了一种制造集成电路的方法，包括：接收具有衬底和设置在所述衬底上的鳍的工件，其中，所述鳍具有限定在其中的沟道区；在所述鳍的沟道区上形成界面层；在所述界面层上形成栅极介电层；在所述栅极介电层上形成第一覆盖层；在所述第一覆盖层上形成第二覆盖层；以及在所述工件上执行退火工艺，其中，所述工艺被配置为使第一材料从所述第一覆盖层扩散到所述栅极介电层中。
根据本发明的另一方面，提供了一种制造集成电路的方法，包括：接收工件，所述工件包括：衬底；半导体鳍，设置在所述衬底上；以及一对介电部件，设置在所述半导体鳍上，使得栅极沟槽在所述一对介电部件之间延伸；在所述栅极沟槽内的所述衬底上形成界面层；在所述栅极沟槽内的所述界面层上形成高k栅极介电质；在所述栅极沟槽内的所述高k栅极介电质上形成第一覆盖层；在所述栅极沟槽内的所述第一覆盖层上形成第二覆盖层；以及在所述工件上执行退火工艺，其中，所述退火工艺被配置为从所述界面层获取氧。
根据本发明的又一方面，提供了一种制造集成电路的方法，包括：接收具有其上限定有沟道区的衬底；在所述沟道区上形成界面层；在所述界面层上形成栅极介电质；在所述栅极介电质上形成第一覆盖层；在所述第一覆盖层上形成第二覆盖层，所述第二覆盖层具有与所述第一覆盖层不同的组成；在具有所述第二覆盖层的所述衬底上执行第一退火工艺，其中，所述第一退火工艺被配置为使氮从所述第一覆盖层扩散到所述栅极介电质中；在所述第二覆盖层上形成第三覆盖层；在具有所述第三覆盖层的所述衬底上执行第二退火工艺；以及移除所述第二覆盖层和所述第三覆盖层。
附图说明
当结合附图进行阅读时，从下面的详细描述可以最好地理解本发明公开内容。应注意到，根据工业中的标准实践，各种部件不是按比例绘制而是作为说明目的。实际上，为了清楚的讨论，各个部件的尺寸可以被任意增加或减少。
图1A和图1B是根据本发明的各个方面的制造具有栅极结构的半导体器件的方法的流程图，其中，该栅极结构具有界面层。
图2是根据本发明的各个方面的经历制造方法的工件的透视图。
图3至图15是根据本发明的各个方面的在制造方法的各个时间点处沿第一截面截取的工件的截面图。
图16是根据本发明的各个方面的工件的材料成分的曲线图。
具体实施方式
以下公开内容为实现本发明的不同部件提供了诸多不同的实施例或者实例。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，也可以包括在第一部件和第二部件之间形成附加部件使得第一部件和第二部件不直接接触的实施例。例如，在以下描述中，连接到和/或耦合到本发明的另一部件的部件的形成可包括其中多个部件形成为直接接触的实施例，也可包括其中附加部件可形成为插入多个部件之间的实施例，从而使得多个部件可不直接接触。
此外，使用空间相对术语(例如，“下部”、“上部”、“水平”、“垂直”、“在…之上”、“在…上方”、“在…之下”、“在…下方”、“向上”、“向下”、“顶部”、“底部”等)以及其衍生物(例如，“水平地”、“向下地”、“向上地”等)以便于说明本发明的一个部件与另一个部件的关系。空间相对术语旨在覆盖包括多个部件的装置的不同取向。此外，本发明可能会在各种实例中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，并且其本身不指示超过内容所述的各个实施例和/或配置之间的关系。
在最基本的情况下，晶体管可包括掺杂的半导体，以形成由沟道区分开的源极/漏极部件。栅极结构设置在沟道区上，并包括栅电极和将所述栅电极和所述沟道区分开的栅极介电质。虽然可使用任何合适的栅极介电质，但是本公开的许多示例使用高k栅极介电质来减少漏电流、降低阈值电压和/或优化晶体管的操作。
然而，如果一些高k材料直接应用于沟道区的半导体，则这些高k材料可能不会形成均匀的无缺陷界面。为了解决这个问题，可在沉积高k材料之前在半导体上形成界面层。特别是在界面处，该界面层可减少高k材料中的氧空位和其他缺陷。该界面层还可改善热稳定性、减少穿过高k材料的隧穿，并改善通过沟道区的载流子迁移率。然而，必须权衡这些益处与成本。该界面层有助于栅极电容并降低器件的响应性。在一些示例中，通过沟道区的器件电流和开关速度随着界面层变的更厚而降低。
由于这些原因和其他原因，本发明公开的技术在沟道区和高k栅极介电质之间形成界面层，并防止非预期的氧化，否则这种氧化会增加界面层的厚度。一些示例还使氧扩散出界面层以减小界面层的厚度。在这些示例和其他示例中，该技术提供了对界面层厚度的精确控制，以使制造商可平衡界面层的成本和益处，从而提供改进的器件性能、均匀性和可靠性。然而，除非另有说明，否则不需要实施例提供任何特定的优点。
本发明公开的技术可用于形成各种平面和非平面器件。参考图1A至图15描述鳍式场效应晶体管(FinFET)及其形成方法的示例。在这方面，图1A和1B是根据本公开各个方面制造具有栅极结构的半导体器件的方法100的流程图，其中，该栅极结构具有界面层。可在方法100之前、期间和之后提供附加步骤，并对于方法100的其他实施例，可替换或去除所描述的一些步骤。
图2是根据本发明的各个方面的经历方法100的工件200的透视图。图3至图15是根据本发明的各个方面所述，在制造方法100的各个时间点处沿第一截面(图2的平面202)截取的工件200的截面图。为清楚起见，已经简化了图2至图15，并且更好地说明本发明公开的概念。附加部件可结合到工件200中，且对于工件200的其他实施例，可替换或去除下面描述的一些部件。
参考图1A的方框102和图2，接收工件200。工件200包括衬底206，在该衬底上形成有器件。在各种示例中，衬底206包括基本(单一元素)半导体，比如，晶体结构的硅或锗；化合物半导体，比如，碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，比如，SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；非半导体材料，比如，钠钙玻璃、熔融硅石、熔融石英和/或氟化钙(CaF2)；和/或其组合。
衬底206的成分可以是均匀的，或可包括各种层，其中一些层可被选择性地蚀刻以形成鳍。这些层可具有相似或不同的组成，且在各种实施例中，一些衬底层具有不均匀的组成以诱导器件应变并由此调节器件性能。分层衬底的示例还包括绝缘体上硅(SOI)衬底206。在一些这样的示例中，SOI衬底206的绝缘层包括半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物和/或其他合适的绝缘体材料。
在一些示例中，待形成在衬底206上的器件延伸到衬底206之外。例如，FinFET和/或其他非平面器件可形成在设置于衬底206上的器件鳍208上。器件鳍208代表任何凸起部件，并包括FinFET器件鳍208以及用于在衬底206上形成其他凸起的有源和无源器件的鳍208。可通过蚀刻衬底206的部分、通过在衬底206上沉积各种层并蚀刻这些层，和/或通过其他合适的技术来形成鳍208。例如，可使用一种或多种光刻工艺图案化鳍208，包括双图案化或多图案化工艺。通常，双图案化或多图案化工艺结合了光刻和自对准工艺，从而允许要制造的图案的间距小于例如使用单个直接光刻工艺另外可获得的间距。例如，在一个实施例中，牺牲层形成在衬底上方并使用光刻工艺进行图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，然后剩余的间隔件可用于图案化鳍。
鳍208的成分可与衬底206类似，或者可与衬底不同。例如，在一些实施例中，衬底206主要包括硅，而鳍208包括主要是锗或SiGe半导体的一个或多个层。在一些实施例中，衬底206包括SiGe半导体，且鳍208包括一个或多个层，该一个或多个层包括硅与锗比率的不同的SiGe半导体。
鳍208可通过隔离部件210(例如浅沟槽隔离部件(STI))彼此物理地和电气地分离。在各种示例中，隔离部件210包括介电材料，比如，半导体氧化物、半导体氮化物、半导体碳化物、氟硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的介电材料。
每个器件鳍208可包括任何数量的电路器件，比如，FinFET，该电路器件又各自包括由沟道区214分开的一对相对的源极/漏极部件212。源极/漏极部件212可包括半导体(例如，Si、Ge、SiGe等)和一种或多种掺杂剂，比如，p型掺杂剂(例如硼，BF2或铟)或n型掺杂剂(例如磷或砷)。类似地，沟道区214可包括半导体和掺杂类型与源极/漏极部件212的掺杂剂相反的一种或多种掺杂剂。
由施加到邻近并包覆沟道区214的栅极结构的电压来控制通过沟道区214的载流子(用于n沟道FinFET的电子和用于p沟道FinFET的空穴)的流动。为了避免模糊其他元件，由图2中的透明标记216指示栅极结构的位置。
参考图3，更详细地示出了所接收的工件200的一部分。工件200包括设置在鳍208的沟道区214上的占位栅极结构302。当功能栅极结构的材料对制造工艺敏感或难以图案化时，在一些制造工艺期间，可使用多晶硅、介电质和/或其他弹性材料的占位栅极结构302。稍后移除占位栅极结构302，并在后栅极工艺中用功能栅极的元件(例如，界面层、栅极介电层、栅电极等)代替。在此之前，占位栅极结构302为功能栅极预留空间并为要应用的其他材料提供框架。
例如，侧壁间隔件304设置在占位栅极结构302的侧面上。在各种示例中，侧壁间隔件304包括一层或多层合适的材料，比如，介电材料(例如，半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、半导体碳氮氧化物等)、旋涂玻璃(SOG)、原硅酸四乙酯(TEOS)、等离子体增强化学气相沉积氧化物(PE-氧化物)、高纵横比工艺(HARP)形成的氧化物和/或其他合适的材料。在一个这样的实施例中，侧壁间隔件304中每个包括第一氧化硅层、设置在第一层上的第二氮化硅层，以及设置在第二层上的第三氧化硅层。在该实施例中，侧壁间隔件304的每层的厚度在约1nm和约10nm之间。
工件200还可包括设置在侧壁间隔件304旁边并位于源极/漏极部件212上的接触蚀刻停止层(CESL)306。CESL 306可包括介电质(例如，半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物等)和/或其他合适的材料，在多个实施例中，CESL 306包括SiN、SiO、SiON和/或SiC。在一些示例中，CESL 306的厚度在约1nm和约50nm之间。
层间介电(ILD)层308设置在CESL 306上和工件200的源极/漏极部件212上。ILD层308用作支撑和隔离导电迹线的绝缘体。在后面的工艺中，多个ILD层308沉积为彼此堆叠以形成多层互连结构，该多层互连结构电互连工件200的元件，比如，源极/漏极部件212和功能栅极结构。每个ILD层308可包括介电材料(例如，半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物等)、SOG、氟化物掺杂的硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、Black
Figure BDA0002101700250000061
干凝胶、气凝胶、非晶氟化碳、聚对二甲苯、BCB、
Figure BDA0002101700250000062
和/或它们的组合。
参考图1A的方框104和图4，执行蚀刻工艺，从而选择性地移除占位栅极结构302。在留下侧壁间隔件304、CESL 306和ILD层308的同时移除占位栅极结构302限定了栅极凹槽402，以在其中形成功能栅极结构。蚀刻工艺可包括任何合适的蚀刻技术，比如，湿法蚀刻、干法蚀刻、反应离子蚀刻(RIE)、灰化和/或其他蚀刻方法。在一些实施例中，蚀刻工艺包括使用基于氧的蚀刻剂、基于氟的蚀刻剂、基于氯的蚀刻剂、基于溴的蚀刻剂、基于碘的蚀刻剂、其他合适的蚀刻剂气体或等离子体、和/或它们的组合的干法蚀刻。在一些实施例中，蚀刻工艺包括使用选择的不同蚀刻剂蚀刻占位栅极结构的特定材料的多个阶段(例如，选择性地蚀刻介质栅极覆盖件的第一阶段、选择性地蚀刻多晶硅占位栅电极的第二阶段等)。
参考图1A的方框106和到图5，界面层502在栅极凹槽402内形成在沟道区214的顶面上。界面层502可包括任何合适的材料，比如，介电质(例如，半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、半导体碳氮化物等)或其他合适的材料。界面层502可通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)和/或其他合适的技术形成。因此，在一些实施例中，界面层502包括通过热氧化形成的氧化硅和/或氧化硅锗。界面层502可形成为任何合适的厚度，且在各种示例中，厚度在约5埃和约20埃之间。可调整随后的一些工艺以防止由于例如沟道区214的无意氧化而导致的界面层502的进一步生长。因此，成品工件200中的界面层502的厚度可与方框106结束时的厚度基本相同。在其他示例中，随后的工艺实际上使界面层502变薄，使得成品工件200中的界面层502的厚度小于方框106结束时的厚度。
参考图1A的方框108并且任参考图5，栅极介电层504在栅极凹槽402内形成在界面层502上。特别地，栅极介电层504可覆盖界面层502，并还可沿着侧壁隔离物304的垂直侧面垂直延伸。
用于栅极介电层504的合适材料的特征通常在于它们相对于氧化硅的介电常数(k)。栅极介电层504可包括高k介电材料，比如，HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆(ZrO2)、氧化镧(La2O3)，氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料，和/或其组合。与氧化硅栅极介电层相比，高k栅极介电层504可更厚，这可减少栅电极和沟道区214之间的隧穿、减少泄漏、避免介电击穿、并增加晶体管寿命。此外，由于高k栅极介电层504整体可更厚，所以通过调节栅极介电层504的厚度，可更容易调节各个晶体管的参数，比如，工作电压或阈值电压。
然而，栅极介电层504不限于高k介电材料。另外或替代地，栅极介电层504可包括其他介电质，比如，氮化硅、氮氧化硅、碳化硅、非晶碳、原硅酸四乙酯(TEOS)、其他合适的介电材料，和/或它们的组合。
栅极介电层504可通过任何合适的技术形成，比如，ALD、等离子体增强ALD(PEALD)、CVD或等离子体增强CVD(PECVD)。栅极介电层504可形成为任何合适的厚度，且在一些示例中，栅极介电层504的厚度在约10埃和约30埃之间。
参考图1A的方框110和图6，第一覆盖层602在栅极凹槽402内形成在栅极介电层504上。第一覆盖层602可覆盖栅极介电层504的水平表面以及沿着侧壁间隔件304延伸的栅极介电层504的垂直表面。
第一覆盖层602可包括任何合适的保护材料，包括金属(例如，W、Al、Ta、Ti、Ni、Cu、Co等)、金属氮化物和/或金属氮化硅。在多个此类实施例中，第一覆盖层602包括TiSiN和/或TiN。在第一覆盖层602包括氮的实例中，第一覆盖层602可用作钝化工艺的氮源，其中氮扩散到栅极介电层504的高k介电材料中以补偿高k材料中的氧空位。
可通过ALD、PEALD、CVD、PECVD、物理气相沉积(PVD)和/或其他合适的沉积工艺来沉积第一覆盖层602。特别地，可在没有氧的环境中执行沉积工艺，以避免穿透沟道区214的氧化，这种氧化可增加界面层502的厚度。在一些示例中，使用TiCl4和NH3前体，在约400℃至约550℃之间的温度下，在约3托至约30托的压力下使用ALD沉积第一覆盖层602。沉积工艺可被配置为产生具有任何合适厚度的第一覆盖层602，并在多个示例中，第一覆盖层602具有在大约10埃和大约20埃之间的厚度。
参考图1A的方框112并且仍参考图6，第二覆盖层604在栅极凹槽402内形成在第一覆盖层602上。在这方面，第二覆盖层604可共形地形成为覆盖第一覆盖层602的水平表面和垂直表面。
第二覆盖层604可包括任何合适的保护材料，包括金属、半导体及其其氮化物。第二覆盖层604的组成可与第一覆盖层602相同或不同。在一些实施例中，第二覆盖层604包括非晶硅。在一些实施例中，第二覆盖层604包括铝和/或铝化合物。
可通过ALD、PEALD、CVD、PECVD、PVD和/或其他合适的沉积工艺来沉积第二覆盖层604。在一个此类示例中，第二覆盖层604包括硅并通过硅烷(SiH4)浸泡工艺来沉积该第二覆盖层，其中在约400℃至约550℃之间的温度下在约3托至约30托的压力下引入硅烷。类似于第一覆盖层602的沉积，可在没有氧的环境中执行该沉积工艺，以避免穿透沟道区214的氧化，这种氧化可增加界面层502的厚度。为了进一步减少无意氧化的机会，可在相同工具和/或工具的相同腔室中执行(即，原位沉积)第一覆盖层602和第二覆盖层604的沉积。在同一工具和/或腔室中进行沉积避免了在运输工件200时发生意外氧化或与环境的其他反应的风险。沉积工艺可被配置为产生具有任何合适厚度的第二覆盖层604，并在多个示例中，第二覆盖层604具有在大约5埃和大约10埃之间的厚度。
参考图1A的方框114和图7，在工件200上执行金属后退火(PMA)工艺。PMA工艺被配置为使氮从第一覆盖层602扩散到栅极介电层504的高k介电材料中。更详细地，如所形成的，栅极介电层504可具有由介电材料中的氧空位产生的缺陷。这些缺陷可能导致阈值电压变化，并可能损害器件的可靠性。通过将来自第一覆盖层602和/或退火环境的原子(例如氮)驱动到栅极介电质中以填充这些空位，可解决这些缺陷(即，栅极介电质可被钝化)。
PMA工艺可在任何合适的温度下进行任何合适的时间段。在一些示例中，PMA工艺包括将工件200加热至约600℃至约800℃之间的温度，以在NH3周围环境中浸泡约10秒到约60秒之间，同时在约850℃至约950℃的温度下进行尖峰退火。
类似于方框110和112，可在没有氧的环境中执行PMA工艺，以避免穿透沟道区214的氧化，这种氧化可增加界面层502的厚度。进一步减少无意氧化的机会，可在与沉积第一覆盖层602和/或第二覆盖层604的相同工具和/或腔室中进行PMA工艺(即，原位退火)。
除了将氮扩散到栅极介电层504中之外，PMA工艺还可使界面层502中的氧向外扩散到第二覆盖层604中。结果，界面层502在方框114结束时可以比在方框106中沉积时更薄。按此方式，本技术不仅可避免增加界面层502的厚度，方法100实际上还可减小厚度。举例来说，界面层502在沉积时可在约5埃和约20埃之间，且在方框114结束时可保持在约5埃和约20埃之间。
参考图1A的方框116并且任参考图8，第三覆盖层702在栅极凹槽402内形成在第二覆盖层604上。第三覆盖层702可共形地形成为覆盖第二覆盖层604的水平和垂直表面。
第三覆盖层702可包括任何合适的保护材料，包括金属、半导体和其氮化物。第三覆盖层702的组成可与第一覆盖层602和第二覆盖层604相同或不同。在一些实施例中，第三覆盖层702基本上类似于第二覆盖层604并包括非晶硅。在一些实施例中，第三覆盖层702基本上类似于第二覆盖层604并包括铝和/或铝化合物。
可通过ALD、PEALD、CVD、PECVD、PVD和/或其他合适的沉积工艺沉积第三覆盖层702，且在一个示例中，包括使用Si2H6作为前体、在约350℃至约500℃之间的温度下以及在约0.3托至约30托的压力下通过CVD沉积的非晶硅。由于存在第二覆盖层604，所以栅极结构的其他材料可能不再需要保护而防止氧气损害。因此，可在不同的腔室或工具中执行第三覆盖层702的沉积工艺。腔室或工具之间的转移可表示自第一覆盖层602沉积以来，工件200第一次暴露于不受控制的环境。
沉积工艺可被配置成产生具有任何合适厚度的第三覆盖层702。在一些示例中，第三覆盖层702的厚度在约20埃到约50埃之间，并基本上比第二覆盖层604厚，在这些示例中，第二覆盖层的厚度在约10埃和约20埃之间。在一些示例中，第三覆盖层702的厚度在约10埃至约20埃之间，并与第二覆盖层604的厚度基本相同。
参考图1A的方框118和图9，在工件200上执行覆盖后退火(PCA)工艺。类似于PMA工艺，PCA工艺可被配置为使氮从第一覆盖层602和/或退火环境扩散到栅极介电层504的高k介电材料中，并可使界面层502中的氧向外扩散到第二覆盖层604和/或第三覆盖层702中。结果，界面层502在方框118结束时可以比在方框106中沉积时更薄。举例来说，界面层502在沉积时可在约5埃和约20埃之间，且在方框118结束时可保持在约5埃和约20埃之间。
可在任何合适的温度下在任何合适的持续时间段内执行PCA工艺，并可实施为基本类似于方框114的PMA工艺。在一些示例中，PCA工艺包括将工件200加热至约600℃至约800℃之间的温度，以在N2周围环境中浸泡约10秒到约60秒之间，同时在约850℃至约950℃之间的温度下进行尖峰退火。
参考图1B的方框120和到图10，在工件200上执行蚀刻工艺以去除第二覆盖层604和第三覆盖层702。蚀刻工艺可包括任何合适的蚀刻技术，比如，湿法蚀刻、干法蚀刻、RIE、灰化和/或其他蚀刻方法。蚀刻工艺可使用任何合适的蚀刻剂，并可选择技术和蚀刻剂化学物质以选择性地蚀刻第二覆盖层604和第三覆盖层702，而不会显著地蚀刻任何周围材料，比如，第一覆盖层602的周围材料。
应注意，一些蚀刻技术和材料可在第一覆盖层602的最顶面上留下第二覆盖层604的残余物。在一些示例中，特别是在结合含氮高k栅极介电质层504(例如，ALD TiN，该TiN具有小于约2.3原子百分比的氮)使用时，来自含硅第二覆盖层的残留硅保留在第一覆盖层602的最顶面上。
然后可沉积构成栅电极的金属层。虽然界面层502、栅极介电层504和上述的多个覆盖层对于工件200的pMOS和nMOS晶体管可基本相同，但是栅电极的一些金属层可不同。因此，图11至图15示出了用于形成pMOS晶体管的工件200的第一区域902和用于形成nMOS晶体管的相同工件200的第二区域904。
参考图1B的方框122和图11，在pMOS区域902和nMOS区域904中的栅极凹槽402内的第一覆盖层602上形成阻挡层906。阻挡层906可包含任何合适的材料，包括金属和金属氮化物，比如，Ta、TaN、Ti、TiN、W、Ru或其组合。可基于它们扩散到第一覆盖层602、栅极介电层504和侧壁间隔件304中的恢复力(resilience)来选择用于阻挡层906的材料。可通过任何合适的技术沉积阻挡层906，包括ALD、PEALD、CVD、PECVD、PVD(例如溅射)和/或它们的组合。
参考图1B的方框124并参考图12至图14，在阻挡层906上的栅极凹槽402内形成一个或多个功函数层。合适的功函数层材料包括基于栅极堆叠件所对应的器件类型的n型和/或p型功函数材料。示例性的p型功函数材料包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其他合适的p型功函数材料，和/或其组合。示例性n型功函数材料包括Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合适的n型功函数材料，和/或其组合。可通过任何合适的技术沉积功函数层(多个功函数层)，包括ALD、PEALD、CVD、PECVD、PVD和/或它们的组合。
在一个示例中，如图10所示，p型功函数层1002(例如，TiN)沉积在pMOS区域902和nMOS区域904的栅极凹槽402内。在沉积之后，可通过光致抗蚀剂和/或其他抗蚀剂材料保护pMOS区域902内的p型功函数层1002的部分，同时暴露nMOS区域904内的部分。然后可在蚀刻工艺中蚀刻p型功函数层1002在nMOS区域904中的露出部分，该蚀刻工艺被配置为避免对诸如阻挡层906的周围材料进行显著蚀刻。如图13所示，这可使p型功函数层1002在pMOS区域902中的部分未被蚀刻。在蚀刻之后可去除任何剩余的抗蚀剂材料。
继续该示例，如图14所示，n型功函数层1202(例如，TiAlC)沉积在pMOS区域902和nMOS区域904的栅极凹槽402内。可允许n型功函数层1202保留在pMOS区域902中，因为更靠近沟道区域214的p型功函数层1002可支配栅极结构的功函数。
参考图1B的方框126和仍参考图14，第四覆盖层1204形成在栅极凹槽402内的功函数层1002和1202上。第四覆盖层1204可包含任何合适的保护材料，包括金属、金属氮化物和/或金属硅氮化物，并在一个示例中，第四覆盖层1204包括TiN。可通过任何合适的技术沉积第四覆盖层1204，包括ALD、PEALD、CVD、PECVD、PVD和/或它们的组合。
参考图1B的方框128和仍参考图14，胶层1206形成在栅极凹槽402内的第四覆盖层1204上。胶层1206可包含选择用于促进层之间的粘附的任何合适的材料，且可包括金属、金属氮化物和/或金属硅氮化物，在一个示例中，胶层1206包括钨。可通过任何合适的技术沉积胶层1206，包括ALD、PEALD、CVD、PECVD、PVD和/或它们的组合。在一个实施例中，在无氟沉积工艺中使用ALD形成含钨胶层1206。
参考图1B的方框130和仍参考图14，电极填充物1208形成在栅极凹槽402内的胶层1206上。电极填充物1208可包括任何合适的材料，包括金属、金属氧化物、金属氮化物和/或它们的组合，并在一个示例中，电极填充物1208包括钨。可通过任何合适的技术沉积电极填充物1208，包括ALD、PEALD、CVD、PECVD、PVD和/或它们的组合。
参考图1B的方框132和图15，可执行化学机械平坦化/抛光(CMP)工艺以去除栅极结构1302外部的材料(例如，栅极介电层504、第一覆盖层602、阻挡层906、功函数层1002和1202、第四覆盖层1204、胶层1206、电极填充物1208等的材料)。
参考图1B的方框134，提供工件200用于进一步制造。在各种示例中，进一步的制造包括形成电连接至栅极结构1302和源极/漏极部件212的接触件、形成电互连结构的剩余部分、切割、封装和其他制造工艺。
图16是根据本发明的各个方面的示例性工件的材料成分的曲线图1600。工件可基本上类似于图2至图15的工件200，并可通过图1A至图1B的方法100形成。曲线图1600可通过能量色散光谱(EDS)或其他合适的技术产生，并包括表示位置的第一轴1602和表示对应于特定材料的信号强度的第二轴1604。信号1606对应于硅，信号1608对应于铪，信号1610对应于钛，信号1612对应于钽，信号1614对应于钨。任何给定的技术对某些材料可能比其他材料更敏感，因此信号1606至1614的幅值可能无法直接比较。然而，通过比较给定信号的变化，可确定给定位置处的相应材料的相对量。
在该示例中，曲线图1600具有对应于衬底206和界面层502的第一区域1616。第一区域1616主要是硅。第二区域1618对应于栅极介电层504，并主要是铪和硅与一些钽。第三区域1620对应于第一覆盖层602，并主要是TiN形式的钛。如上在框120的上下文中所述，工件可包括在第一覆盖层602和阻挡层906之间的第四区域1622中发现的硅残余物。第五区域1624对应于阻挡层906，并包括TaN形式的钽和一些钛。
曲线图1600具有第六区域1626，其对应于栅极堆叠件(例如，p型功函数层1002、n型功函数层1202、第四覆盖层1204、胶层1206、电极填充物1208等)的导体。第六区域1626包括钛和钨。
因此，本发明提供了用于形成集成电路器件的改进方法的示例，该集成电路器件具有在沟道区和栅极介电质之间的改进界面层。在一些实施例中，所述制造集成电路的方法包括接收具有衬底和鳍的工件，所述鳍具有设置在所述衬底上的沟道区。界面层形成在所述鳍的沟道区上，且栅极介电层形成在所述界面层上。第一覆盖层形成在所述栅极介电层上，且第二覆盖层形成在所述第一覆盖层上。在所述工件上执行退火工艺，所述工艺被配置为使第一材料从所述第一覆盖层扩散到所述栅极介电层中。在一些该实施例中，所述第一覆盖层的形成和所述第二覆盖层的形成在制造工具的第一腔室中执行。在一些该实施例中，所述退火工艺在所述制造工具的第一腔室中执行。在一些该实施例中，所述退火工艺被配置为使氧扩散出所述界面层。在一些该实施例中，所述退火工艺是第一退火工艺，所述方法还包括：在所述第二覆盖层上形成第三覆盖层，并在所述工件上执行第二退火工艺。在一些该实施例中，所述第二退火工艺被配置为使氧扩散出所述界面层。在一些该实施例中，所述第二覆盖层的厚度与所述第三覆盖层的厚度基本相同。在一些该实施例中，所述第三覆盖层具有与所述第二覆盖层基本相同的组成。在一些实施例中，所述第二覆盖层包括非晶硅和/或铝。在一些实施例中，所述第一覆盖层包括金属氮化物，且所述第一材料包括氮。
在实施例中，在制造工具的第一腔室中实施所述第一覆盖层的形成和所述第二覆盖层的形成。
在实施例中，在所述制造工具的第一腔室中执行所述退火工艺。
在实施例中，所述退火工艺被配置为使氧扩散到所述界面层之外。
在实施例中，所述退火工艺是第一退火工艺，所述方法还包括：在所述第二覆盖层上形成第三覆盖层；以及在所述工件上执行第二退火工艺。
在实施例中，所述第二退火工艺被配置为使氧扩散到所述界面层之外。
在实施例中，所述第二覆盖层的厚度与所述第三覆盖层的厚度相同。
在实施例中，所述第三覆盖层具有与所述第二覆盖层相同的组成。
在实施例中，所述第二覆盖层包括由以下材料所组成的组中的材料：非晶硅和铝。
在实施例中，所述第一覆盖层包括金属氮化物，并且所述第一材料包括氮。
在其他实施例中，所述方法包括接收工件，所述工件进而包括衬底、设置在所述衬底上的半导体鳍以及设置在所述半导体鳍上的一对介电部件，从而使得栅极沟槽可在所述一对介电部件之间延伸。在所述栅极沟槽内的所述衬底上形成界面层，并在所述栅极沟槽内的所述界面层上形成高k栅极介电质。此外，第一覆盖层形成在所述栅极沟槽内的所述高k栅极介电质上，且第二覆盖层形成在所述栅极沟槽内的所述第一覆盖层上。在所述工件上执行退火工艺，所述退火工艺被配置为从所述界面层获取氧。在一些该实施例中，所述第一覆盖层的形成、所述第二覆盖层的形成和所述退火工艺的执行在制造工具的单个腔室中实施。在一些该实施例中，所述第一覆盖层包括金属氮化物，且所述退火工艺还被配置为使氮从所述第一覆盖层扩散到所述高k栅极介电质中。在一些该实施例中，所述第二覆盖层包括来自以下材料所组成的组中的材料：硅和铝。在一些该实施例中，所述退火工艺是第一退火工艺，所述方法还包括：在所述栅极沟槽内的所述第二覆盖层上形成第三覆盖层，并在所述工件上执行第二退火工艺，所述第二退火工艺被配置为从所述界面层获取氧。在一些该实施例中，移除所述第二覆盖层和所述第三覆盖层，并形成栅极结构，所述栅极结构包括所述界面层、所述高k栅极介电质和所述第一覆盖层。
在实施例中，在制造工具的单个腔室中实施形成所述第一覆盖层、形成所述第二覆盖层和执行所述退火工艺。
在实施例中，所述第一覆盖层包括金属氮化物，且所述退火工艺还被配置为使氮从所述第一覆盖层扩散到所述高k栅极介电质中。
在实施例中，所述第二覆盖层包括来自以下材料所组成的组中的材料：硅和铝。
在实施例中，所述退火工艺是第一退火工艺，所述方法还包括：在所述栅极沟槽内的所述第二覆盖层上形成第三覆盖层；以及在所述工件上执行第二退火工艺，其中，所述第二退火工艺被配置为从所述界面层获取氧。
在实施例中，方法还包括：移除所述第二覆盖层和所述第三覆盖层；以及形成包括所述界面层、高k栅极介电质和所述第一覆盖层的栅极结构。
在又一些实施例中，所述方法包括接收具有沟道区的衬底。界面层形成在所述沟道区上，且栅极介电质形成在所述界面层上。第一覆盖层形成在所述栅极介电质上，且第二覆盖层形成在所述第一覆盖层上。所述第二覆盖层具有与所述第一覆盖层不同的组成。在具有所述第二覆盖层的所述衬底上执行第一退火工艺。所述第一退火工艺被配置为使氮从所述第一覆盖层扩散到所述栅极介电质中。第三覆盖层形成在所述第二覆盖层上，且在具有所述第三覆盖层的所述衬底上执行第二退火工艺。然后移除所述第二覆盖层和所述第三覆盖层。在一些该实施例中，所述第一覆盖层的形成、所述第二覆盖层的形成和所述第一退火工艺的执行在制造工具的同一腔室中实施。在一些该实施例中，所述第一退火工艺的执行还被配置为从所述界面层获取氧。在一些该实施例中，所述第二退火工艺的执行还被配置为从所述界面层获取氧。
在实施例中，制造工具的同一腔室中实施形成所述第一覆盖层、形成所述第二覆盖层和执行所述第一退火工艺。
在实施例中，所述第一退火工艺的执行还被配置为从所述界面层获取氧。
在实施例中，所述第二退火工艺的执行还被配置为从所述界面层获取氧。
前述概述了若干实施例的部件，使得本领域技术人员可更好地理解本发明的各方面。本领域技术人员应当理解，他们可以容易地使用本公开作为基础来设计或修改其他用于达到与实施与本文所介绍的实施例相同目的和/或实现相同优点的工艺和结构。本领域技术人员还应该认识到，这样的等效结构不脱离本公开的精神和范围，并且在不脱离本公开的精神和范围的情况下，它们可以在本发明中进行各种改变、替换和变更。

Claims (20)

1.一种制造集成电路的方法，包括：
接收具有衬底和设置在所述衬底上的鳍的工件，其中，所述鳍具有限定在其中的沟道区；
在所述鳍的沟道区上形成界面层；
在所述界面层上形成栅极介电层；
在所述栅极介电层上形成第一覆盖层；
在所述第一覆盖层上形成第二覆盖层；以及
在所述工件上执行第一退火工艺，其中，所述工艺被配置为使第一材料从所述第一覆盖层扩散到所述栅极介电层中，
在所述第二覆盖层上形成第三覆盖层；以及
在所述工件上执行第二退火工艺，其中，所述第二退火工艺被配置为使氧扩散到所述界面层之外。
2.根据权利要求1所述的方法，其中，在制造工具的第一腔室中实施所述第一覆盖层的形成和所述第二覆盖层的形成。
3.根据权利要求2所述的方法，其中，在所述制造工具的第一腔室中执行所述第一退火工艺。
4.根据权利要求1所述的方法，其中，所述第一退火工艺被配置为使氧扩散到所述界面层之外。
5.根据权利要求1所述的方法，其中，所述第一退火工艺包括将所述工件加热至600℃至800℃之间的温度，以在NH3周围环境中浸泡10秒到60秒之间，同时在850℃至950℃的温度下进行尖峰退火。
6.根据权利要求5所述的方法，其中，所述第三覆盖层的厚度在20埃到50埃之间，并比所述第二覆盖层厚。
7.根据权利要求5所述的方法，其中，所述第二覆盖层的厚度与所述第三覆盖层的厚度相同。
8.根据权利要求5所述的方法，其中，所述第三覆盖层具有与所述第二覆盖层相同的组成。
9.根据权利要求1所述的方法，其中，所述第二覆盖层包括由以下材料所组成的组中的材料：非晶硅和铝。
10.根据权利要求1所述的方法，其中，所述第一覆盖层包括金属氮化物，并且所述第一材料包括氮。
11.一种制造集成电路的方法，包括：
接收工件，所述工件包括：
衬底；
半导体鳍，设置在所述衬底上；以及
一对介电部件，设置在所述半导体鳍上，使得栅极沟槽在所述一对介电部件之间延伸；
在所述栅极沟槽内的所述衬底上形成界面层；
在所述栅极沟槽内的所述界面层上形成高k栅极介电质；
在所述栅极沟槽内的所述高k栅极介电质上形成第一覆盖层；
在所述栅极沟槽内的所述第一覆盖层上形成第二覆盖层；
在所述工件上执行第一退火工艺，其中，所述第一退火工艺被配置为从所述界面层获取氧；
在所述栅极沟槽内的所述第二覆盖层上形成第三覆盖层；以及
在所述工件上执行第二退火工艺，其中，所述第二退火工艺被配置为从所述界面层获取氧。
12.根据权利要求11所述的方法，其中，在制造工具的单个腔室中实施形成所述第一覆盖层、形成所述第二覆盖层和执行所述第一退火工艺。
13.根据权利要求11所述的方法，其中，所述第一覆盖层包括金属氮化物，且所述第一退火工艺还被配置为使氮从所述第一覆盖层扩散到所述高k栅极介电质中。
14.根据权利要求11所述的方法，其中，所述第二覆盖层包括来自以下材料所组成的组中的材料：硅和铝。
15.根据权利要求11所述的方法，其中，所述第三覆盖层包括铝和/或铝化合物。
16.根据权利要求11所述的方法，还包括：
移除所述第二覆盖层和所述第三覆盖层；以及
形成包括所述界面层、高k栅极介电质和所述第一覆盖层的栅极结构。
17.一种制造集成电路的方法，包括：
接收具有其上限定有沟道区的衬底；
在所述沟道区上形成界面层；
在所述界面层上形成栅极介电质；
在所述栅极介电质上形成第一覆盖层；
在所述第一覆盖层上形成第二覆盖层，所述第二覆盖层具有与所述第一覆盖层不同的组成；
在具有所述第二覆盖层的所述衬底上执行第一退火工艺，其中，所述第一退火工艺被配置为使氮从所述第一覆盖层扩散到所述栅极介电质中；
在所述第二覆盖层上形成第三覆盖层；
在具有所述第三覆盖层的所述衬底上执行第二退火工艺；以及
移除所述第二覆盖层和所述第三覆盖层。
18.根据权利要求17所述的方法，其中，在制造工具的同一腔室中实施形成所述第一覆盖层、形成所述第二覆盖层和执行所述第一退火工艺。
19.根据权利要求17所述的方法，其中，所述第一退火工艺的执行还被配置为从所述界面层获取氧。
20.根据权利要求17所述的方法，其中，所述第二退火工艺的执行还被配置为从所述界面层获取氧。
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