CN1109637A - Cmos技术中集成电路极性颠倒的保护 - Google Patents

Cmos技术中集成电路极性颠倒的保护 Download PDF

Info

Publication number
CN1109637A
CN1109637A CN94117031A CN94117031A CN1109637A CN 1109637 A CN1109637 A CN 1109637A CN 94117031 A CN94117031 A CN 94117031A CN 94117031 A CN94117031 A CN 94117031A CN 1109637 A CN1109637 A CN 1109637A
Authority
CN
China
Prior art keywords
well region
resistance
substrate
region
link
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN94117031A
Other languages
English (en)
Other versions
CN1043388C (zh
Inventor
卢瑟·布劳斯非尔德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
German Itt Industry Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=6499816&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN1109637(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by German Itt Industry Co ltd filed Critical German Itt Industry Co ltd
Publication of CN1109637A publication Critical patent/CN1109637A/zh
Application granted granted Critical
Publication of CN1043388C publication Critical patent/CN1043388C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及在CMOS技术中，用于单片集成电 路极性颠倒保护的措施。

Description

本发明涉及在CMOS技术中，用于单片集成电路极性颠倒的保护措施，特别涉及用于CMOS器件本身。
防止电子线路元件保护（比如说电源接错）非常重要，特别是在自动化电子设备中，由于极性的颠倒，整个电路可能损坏，从而引起极大的破坏。
为了避免极性颠倒的后果，通常使用一个二极管。在CMOS电路中，这有一个很大的缺点，因为一个二极管只能通过“埋层技术”构成。这样，使得技术更加复杂，从而引起费用上升，这是应想尽一切办法要避免的。
因此，本发明的目的是提供极性颠倒保护，在常规MOS技术下，不需附加技术，就能完成这种保护。
本极性颠倒保护装置包括一种导电类型的基片，在基片的一个主要表面形成的另一导电类型的阱区，和在阱区中形成的基片导电类型的一个源极区及漏极区。通过一个低阻抗，源极区与正电源电压相连，要被保护的电路的输入端位于漏极区，在极性颠倒时，通过一个相同数值的电阻，阱区与电源相连，使得阱区电流被限制在一个最小值。
根据一个实施例的下述描述和附图，本发明将变得更清楚。图中：
图1是依照本发明，用于一个p沟道CMOS晶体管的极性颠倒保护装置的平面图。
图2是图1中沿线A-A的剖面图。
图3给出了图1装置的等效电路图。
图1展示了p型掺杂的基片1，这种情况是MOS技术中被广泛应用的一种模式。n型阱区2形成在基片1的表面。基片1和阱区2被覆盖一绝缘层（没在图1中画出），这个绝缘层有用于底层活跃区的连接孔。在阱区2，漏极区3和源极区5以常规方式形成。位于两区之间是例如多晶硅的栅极4。在远离栅极4的一方，源极区5之后是小分区51，它延伸到n+型阱区部分6。参照数字7、8、9和10，定义了在各个区的金属连结。通过一个低阻抗，源极区5与正电源VDD相连，要被保护的电路的输入es位于漏极区3。
图2给出了图1沿线A-A剖面结构图。
n型阱区2以常规方式在p型基片1中形成。基片，漏极区3，源极区5和在杂质很重的阱区6的表面被一层绝缘层11（如二氧化硅）所覆盖，但为漏极连接9，为源极连接8和作为电阻与分区51相连的连接7以及与电源VDD相连的阱区6留下开孔。栅极4位于栅极区二氧化层12上，它也被一层绝缘层11所覆盖。
在图3中的等效电路中，p沟道晶体管f1有它自己的连接在电源VDD和要保护的电路之间的源漏通路。位于电源VDD和地之间的是一个无源pnp晶体管pt，它是通过源极区5（集电极），n型阱区2（基极）和基片1（发射极）构成的。基极（n型阱区2）和电源VDD之间的是电阻R。
在图3中，通过虚线形式给出了更多的无源晶体管。
图1到图3所给出的p沟道CMOS晶体管位于一个n型阱区，这个阱区通常与正电源电压相连。在极性颠倒过程中，朝着基片1的方向，n-型阱2形成一个正向偏压的二极管，用以吸收一个大电流，以避免热损坏的发生。由于在常规的操作中，只有一个很小的电流（＜1nA）反方向流过CMOS电路的n型阱区，这个阱区可以通过一个电阻与电源VDD相连。电阻应该足够大，以限制在极性颠倒过程中流经阱区的电流。一个先决条件是，电源极区作为集电极，n-型阱区作为基极，底层作为发射极组成的无源pnp晶体管必须有一个足够的小电流增益，并且电流的大小应有电阻决定，而不是由晶体管的增益决定。如果电流的增益小于1（B＜1），那么上述条件可以实现。这就要求包括附加电阻R区在内的源极区的面积和n型阱区的面积之比应小于0.5。
电阻R也可是在阱区中形成的被集成的一个合适尺寸的多晶体窄条。在这种特殊情况下，仅需考虑p型源极区的面积在所占比率。
平导体器件的另一个问题是静电保护，这种静电放电也可以损坏器件。ESD保护的器件也必须满足上述要求。于是上述无源pnp晶体管则可作为一个ESD保护结构。决定四层器件接通电流的分流电阻必须具有一定数值，使得接通远在工作电流之上发生。
为了提供电压保护，象齐纳二极管，可控硅和门限可以由场氧化物（field-oxide）的厚度决定的场氧化物晶体管，这些过压保护器件可以通过阱区6的连接7被连接起来。
本发明的最大优点在于，它可以提供极性颠倒保护。并且因为两种结构基本上是固有的，所以在不需附加面积的情况，它具有抗静电放电的保护结构。
面积的节约非常重要。由于有可能通过一个电阻把两个或更多的n型阱区与电源连接起来，所以面积有可能增长。
为了保证一个稳定的电源供应，可以把p沟道晶体管的栅极与一个低于供电电源的稳定电压相连。也可以把p沟道晶体管的栅极与一个负电源相连。

Claims (6)

1、用于CMOS器件的一个极性颠倒保护装置，包括：
-一种导电类型的基片(1)；
-在基片的一个主要表面中形成的的另一导电类型的阱区(2)；
-在阱区(2)形成的，基片导电类型的一个源极区(5)和一个漏极区(3)。其特征在于：
通过一个低阻抗，源极区(5)与正电源电压(VDD)相连，要被保护的电路的输入端位于漏极区(3)，在极性颠倒时，通过一个相同数值的电阻(R)，阱区(2)与电源(VDD)相连，则阱区电流被限制在一个最小值。
2、如权利要求1所述的装置，其特征在于：基片（1）是p型掺杂的。
3、如权利要求2的所述的装置，其特征在于：电阻（R）为漏极区（3）的分区（51），其中包括源区（5）和分区（51）的总电阻面积与阱区面积之比小于0.5。
4、如权利要求2中所述的装置，其特征在于：电阻（R）由多晶硅构成的。
5、如权利要求4中所述的装置，其特征在于：两个或更多的阱区（2）通过电阻（R）与电源（VDD）相连。
6、如上述任何一个权利要求中所述的装置，其特征在于：过压保护器件是通过阱区（6）的连接区（7）被附加连接的。
CN94117031A 1993-10-09 1994-10-08 Cmos技术中集成电路极性颠倒的保护装置 Expired - Fee Related CN1043388C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4334515A DE4334515C1 (de) 1993-10-09 1993-10-09 Verpolungsschutz für integrierte elektronische Schaltkreise in CMOS-Technik
DEP4334515.8 1993-10-09

Publications (2)

Publication Number Publication Date
CN1109637A true CN1109637A (zh) 1995-10-04
CN1043388C CN1043388C (zh) 1999-05-12

Family

ID=6499816

Family Applications (1)

Application Number Title Priority Date Filing Date
CN94117031A Expired - Fee Related CN1043388C (zh) 1993-10-09 1994-10-08 Cmos技术中集成电路极性颠倒的保护装置

Country Status (6)

Country Link
US (1) US5504361A (zh)
EP (1) EP0647970B1 (zh)
JP (1) JP3559075B2 (zh)
KR (1) KR100276495B1 (zh)
CN (1) CN1043388C (zh)
DE (2) DE4334515C1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2576433B2 (ja) * 1994-12-14 1997-01-29 日本電気株式会社 半導体装置用保護回路
JPH1079472A (ja) * 1996-09-05 1998-03-24 Mitsubishi Electric Corp 半導体集積回路
DE19640272C2 (de) * 1996-09-30 1998-07-23 Siemens Ag Verpolschutzschaltung für integrierte Schaltkreise
US5847431A (en) * 1997-12-18 1998-12-08 Intel Corporation Reduced capacitance transistor with electro-static discharge protection structure
US6049112A (en) * 1998-09-14 2000-04-11 Intel Corporation Reduced capacitance transistor with electro-static discharge protection structure and method for forming the same
TW490907B (en) * 2000-11-14 2002-06-11 Silicon Touch Tech Inc Circuit with protection for inverted connection of power source polarity
JP5032378B2 (ja) * 2008-03-31 2012-09-26 セイコーインスツル株式会社 充放電制御回路及びバッテリ装置
US8964437B2 (en) 2013-01-15 2015-02-24 Keysight Technologies, Inc. Energy dissipating device for DC power supplies
DE102015004235B4 (de) 2014-04-14 2019-01-03 Elmos Semiconductor Ag Verfahren zum Schutz eines CMOS Schaltkreises auf einem N-Substrat vor Verpolung
DE102014017146A1 (de) 2014-04-14 2015-10-15 Elmos Semiconductor Aktiengesellschaft Rail-to-Rail-Verpolschutz für den kombinierten Ein-/Ausgang eine integrierten CMOS Schaltkreises auf einem P-Substrat

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3411200A (en) * 1965-04-14 1968-11-19 Westinghouse Electric Corp Fabrication of semiconductor integrated circuits
JPS53136980A (en) * 1977-05-04 1978-11-29 Nippon Telegr & Teleph Corp <Ntt> Resistance value correction method for poly crystal silicon resistor
JPS59189675A (ja) * 1983-04-12 1984-10-27 Seiko Instr & Electronics Ltd 半導体装置
JPS60767A (ja) * 1983-06-17 1985-01-05 Hitachi Ltd 半導体装置
FR2598852B1 (fr) * 1986-05-16 1988-10-21 Eurotechnique Sa Dispositif de protection d'entree pour circuits integres en technologie cmos.
JPH03295268A (ja) * 1990-04-13 1991-12-26 Sony Corp 半導体装置
US5229635A (en) * 1991-08-21 1993-07-20 Vlsi Technology, Inc. ESD protection circuit and method for power-down application
EP0538507B1 (de) * 1991-10-22 1996-12-27 Deutsche ITT Industries GmbH Schutzschaltung für Anschlusskontakte von monolithisch integrierten Schaltungen
US5345356A (en) * 1992-06-05 1994-09-06 At&T Bell Laboratories ESD protection of output buffers

Also Published As

Publication number Publication date
DE59403534D1 (de) 1997-09-04
KR950012714A (ko) 1995-05-16
EP0647970B1 (de) 1997-07-30
KR100276495B1 (ko) 2000-12-15
CN1043388C (zh) 1999-05-12
DE4334515C1 (de) 1994-10-20
EP0647970A1 (de) 1995-04-12
JP3559075B2 (ja) 2004-08-25
JPH07245348A (ja) 1995-09-19
US5504361A (en) 1996-04-02

Similar Documents

Publication Publication Date Title
US5652689A (en) ESD protection circuit located under protected bonding pad
US7485930B2 (en) Method for four direction low capacitance ESD protection
US5072273A (en) Low trigger voltage SCR protection device and structure
US5717559A (en) Input/output protection device for use in semiconductor device
KR0139648B1 (ko) 트리거 전압이 낮은 scr 보호장치 및 보호회로
EP0412561B1 (en) Semiconductor integrated circuit device
JPH11259148A (ja) 静電放電（ｅｓｄ）保護回路
US4609931A (en) Input protection MOS semiconductor device with zener breakdown mechanism
US5675469A (en) Integrated circuit with electrostatic discharge (ESD) protection and ESD protection circuit
US5181092A (en) Input protection resistor used in input protection circuit
EP0703621B1 (en) Electrostatic discharge protection device for MOS integrated circuits
EP0068844B1 (en) A protective device for a semiconductor integrated circuit
US5347185A (en) Protection structure against latch-up in a CMOS circuit
CN1043388C (zh) Cmos技术中集成电路极性颠倒的保护装置
EP0253105A1 (en) Integrated circuit with improved protective device
KR100194496B1 (ko) 반도체 장치
KR100553015B1 (ko) 반도체장치
KR19980018323A (ko) Ｅｓｄ 보호 반도체 회로 및 ｅｓｄ 보호 회로
US6320229B1 (en) Semiconductor device
EP0202646B1 (en) Input protection device
JP4457620B2 (ja) 静電破壊保護回路
JPH06236965A (ja) 半導体装置
EP0130737B1 (en) Semiconductor device having input protection circuit
KR100347397B1 (ko) 반도체 집적회로용 입출력 보호 장치
US5521413A (en) Semiconductor device having a solid metal wiring with a contact portion for improved protection

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C53 Correction of patent for invention or patent application
COR Change of bibliographic data

Free format text: CORRECT: PATENTEE; FROM: DEUTSCHE ITT INDUSTRIES GMBH TO: MIKERONAS MEDIUM METAL CO., LTD.

CP01 Change in the name or title of a patent holder

Patentee after: Micronas Intermetall GmbH

Patentee before: Deutsche ITT Industries

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 19990512

Termination date: 20131008