CN110911479A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN110911479A
CN110911479A CN201811450374.8A CN201811450374A CN110911479A CN 110911479 A CN110911479 A CN 110911479A CN 201811450374 A CN201811450374 A CN 201811450374A CN 110911479 A CN110911479 A CN 110911479A
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semiconductor
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electrode
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CN110911479B (zh
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松下宪一
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Abstract

实施方式提供一种耐压较高的半导体装置。实施方式的半导体装置具备：第1导电型的半导体基板，具有第1面和第2面；第2导电型的第1半导体区域，设置在第1面中；第2导电型的第2半导体区域，在第1面中，在第1半导体区域的周围以将第1半导体区域包围的方式设置；第2导电型的第3半导体区域，在第1面中，在第2半导体区域内以将第1半导体区域包围的方式设置，第2导电型杂质浓度比第2半导体区域高；第1绝缘膜，在第2半导体区域之上以将第1半导体区域包围的方式设置，在第3半导体区域之上具有孔；以及第1电极，设置在第1绝缘膜之上，经由孔与第3半导体区域电气地连接。

Description

半导体装置
本申请主张以日本专利申请第2018－173140号(申请日：2018年9月15日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置。
背景技术
面向发电及送电、泵及鼓风机等的旋转设备、通信系统或工厂等的电源装置、基于交流马达的铁路、电动汽车、家庭用电器等的范围较宽的领域的，以IGBT(绝缘栅双极晶体管、Insulated Gate Bipolar Transistor)及PIN二极管等的半导体元件为代表的功率半导体装置的开发正在被推进。
作为末端构造，被称作VLD(横向变掺杂、Variation of Lateral Doping)构造的构造开始被用在近年来开发的功率半导体装置中。VLD构造与到目前为止使用的保护环构造等相比，有能够将末端构造小型化的优点。但是，由于VLD构造中的杂质浓度较低，所以有在截止时耗尽层到达电极而泄漏电流增加的问题。此外，如果为了防止该问题而另外形成浓度更高的半导体层，则有制造工序数增加的问题。
发明内容
本发明的实施方式提供一种耐压较高的半导体装置。
技术方案的半导体装置具备：第1导电型的半导体基板，具有第1面和第2面；第2导电型的第1半导体区域，设置在第1面中；第2导电型的第2半导体区域，在第1面中，在第1半导体区域的周围以将第1半导体区域包围的方式设置；第2导电型的第3半导体区域，在第1面中，在第2半导体区域内以将第1半导体区域包围的方式设置，第2导电型杂质浓度比第2半导体区域高；第1绝缘膜，在第2半导体区域之上以将第1半导体区域包围的方式设置，在第3半导体区域之上具有孔；以及第1电极，设置在第1绝缘膜之上，经由孔与第3半导体区域电气地连接。
附图说明
图1是第1实施方式的半导体装置的示意俯视图。
图2是第1实施方式的半导体装置的示意俯视图。
图3的(a)是第1实施方式的半导体装置的主要部的示意剖视图。
图3的(b)是第1实施方式的半导体装置的主要部的示意俯视图。
图4是表示第1实施方式的半导体装置的制造工艺的一部分的示意剖视图。
图5的(a)是作为第1实施方式的比较形态的半导体装置的主要部的示意剖视图。
图5的(b)是作为第1实施方式的比较形态的半导体装置的主要部的示意俯视图。
图6的(a)是作为第1实施方式的比较形态的半导体装置的主要部的示意剖视图。
图6的(b)是作为第1实施方式的比较形态的半导体装置的主要部的示意俯视图。
图7的(a)、图7的(b)是说明第1实施方式的半导体装置的作用效果的图。
图8是第2实施方式的半导体装置的示意俯视图。
图9是第3实施方式的半导体装置的示意俯视图。
图10是第4实施方式的半导体装置的主要部的示意剖视图。
具体实施方式
以下，使用附图说明实施方式。另外，在图中，对于相同或类似的部位赋予相同或类似的标号。
在本说明书中，有对于相同或类似的部位赋予相同的标号而省略重复的说明的情况。
本说明书中，为了表示零件等的位置关系，将图面的上方记述为“上”，将图面的下方记述为“下”。在本说明书中，“上”“下”的概念并不一定是表示与重力的方向的关系的用语。
在本说明书中，n+、n、n－及p+、p、p－的表述表示各导电型中的杂质浓度的相对的高低。即n+表示与n相比n型的杂质浓度相对较高，n－表示与n相比n型的杂质浓度相对较低。此外，p+表示与p相比p型的杂质浓度相对较高，p－表示与p相比p型的杂质浓度相对较低。另外，也有将n+和n－仅记作n型、或将p+和p－仅记作p型的情况。
以下，以第1导电型是n型、第2导电型是p型的情况为例进行说明。
(第1实施方式)
本实施方式的半导体装置具备：第1导电型的半导体基板，具有第1面和第2面；第2导电型的第1半导体区域，设置在第1面中；第2导电型的第2半导体区域，在第1面中，在第1半导体区域的周围以将第1半导体区域包围的方式设置；第2导电型的第3半导体区域，在第1面中，在第2半导体区域内以将第1半导体区域包围的方式设置，第2导电型杂质浓度比第2半导体区域高；第1绝缘膜，在第2半导体区域之上以将第1半导体区域包围的方式设置，在第3半导体区域之上具有孔；以及第1电极，设置在第1绝缘膜之上，经由孔与第3半导体区域电气地连接。
此外，本实施方式的半导体装置具备：第1导电型的半导体基板，具有第1面和第2面；第2导电型的第1半导体区域，设置在第1面中；第2导电型的第2半导体区域，在第1面中，在第1半导体区域的周围以将第1半导体区域包围的方式设置；第1绝缘膜，在第2半导体区域之上以将第1半导体区域包围的方式设置，且具有孔；第1电极，设置在第1绝缘膜之上，经由孔与第2半导体区域电气地连接；以及第2电极，与第1半导体区域电气地连接，与第1电极相间隔而设置。
图1是本实施方式的半导体装置100的示意俯视图。本实施方式的半导体装置100是PIN二极管。
半导体装置100具备半导体基板2、阳极电极10(第2电极的一例)、第1绝缘膜12、第1孔13a(孔的一例)、场板(Field plate)电极14(第1电极的一例)、阻挡电极18、阻挡层20、阴极层24(第7半导体区域的一例)、阴极电极26(第3电极的一例)、p+型半导体区域28(第3半导体区域的一例)、n型表面半导体区域30(第4半导体区域的一例)、阳极层32(第1半导体区域的一例)和p型半导体区域40(第2半导体区域的一例)。
半导体基板2具有第1面4和第2面6。设置在第1面4与第2面6之间的部分作为PIN二极管的漂移层22发挥功能。
p型半导体区域40具有镇流电阻区域42(第5半导体区域的一例)和VLD区域44(第6半导体区域的一例)。镇流电阻区域42具有第1镇流电阻区域部分42a和第2镇流电阻区域部分42b。
图2是本实施方式的半导体装置100的示意俯视图。图2与图1相比省略了阳极电极10、第1绝缘膜12、场板电极14、阻挡电极18和n型表面半导体区域30的记载，表示有p+型半导体区域28、阳极层32、p型半导体区域40、镇流电阻区域42和VLD区域44。
图3是本实施方式的半导体装置100的主要部分的示意图。图3的(a)是图1所示的A－A’截面的半导体装置100的示意剖视图。图3的(b)是在包括图1所示的A－A’截面的部分中、将阳极电极10、第1绝缘膜12、场板电极14和阻挡电极18去掉而表示的半导体装置100的示意俯视图。另外，镇流电阻区域42及VLD区域44如图3所示，有具有多个分别包含p型杂质的区域的情况。
以下，参照图1、图2及图3，说明半导体装置100。
n－型的半导体基板2例如是Si(硅)基板。n型杂质例如是P(磷)。这里，定义x轴、垂直于x轴的y轴、和垂直于x轴及y轴的z轴。假设第1面4及第2面6平行于xy面而配置。此外，以下假设第1面4显示在上，第2面6显示在下。
p型的阳极层32设置在第1面4的中央部。p型杂质例如是B(硼)。
p型半导体区域40在第1面4中，在阳极层32的周围以将阳极层32包围的方式设置。镇流电阻区域42在阳极层32的周围以将阳极层32包围的方式设置。VLD区域44在镇流电阻区域42的周围以将镇流电阻区域42包围的方式设置。可以说，镇流电阻区域42及VLD区域44分别在第1面4中以环状设置。并且，在VLD区域44中，与第1面4平行的面内的p型杂质的梯度朝向半导体基板的端部2b以比镇流电阻区域42大的梯度变低。关于这一点，使用图4进一步在后面叙述。
p+型半导体区域28在第1面4中，在p型半导体区域40内以将阳极层32包围的方式设置。并且，p+型半导体区域28的p型杂质浓度比p型半导体区域40的杂质浓度高。
在图3的(a)的示意图中，p+型半导体区域28设置在镇流电阻区域42的任意的位置。比p+型半导体区域28靠内侧的镇流电阻区域42是第1镇流电阻区域部分42a。此外，比p+型半导体区域28靠外侧的镇流电阻区域42是第2镇流电阻区域部分42b。并且，p+型半导体区域28的厚度比p型半导体区域40的厚度薄。
并且，p型半导体区域40的p型杂质浓度在距第1面4的规定的距离d1处具有最大值。
第1绝缘膜12在p型半导体区域40之上以将阳极层32包围的方式设置。并且，在第1绝缘膜12中，沿着p+型半导体区域28之上以环状设置有第1孔13a(孔的一例)。第1绝缘膜12例如是硅氧化膜。
场板电极14设置在第1绝缘膜12之上。并且，场板电极14经由第1孔13a与p+型半导体区域28电气地连接。场板电极14例如由铝(Al)形成。场板电极14的端部2b侧的前端设置在镇流电阻区域42与VLD区域44之间。但是，设置场板电极14的前端的位置并不限定于此。
阳极电极10在阳极层32之上与阳极层32电气地连接，一部分设置在第1绝缘膜12之上。阳极电极10由铝(Al)形成。阳极电极10与场板电极14相间隔而设置。
n+型的阻挡层20在第1面4上，且设置在半导体装置100的外周。阻挡电极18设置在阻挡层20之上。阻挡电极18与阻挡层20电气地连接。阻挡层20抑制耗尽层来到在端部2b上通过切割加工而形成的未图示的凹凸处。阻挡电极18使阻挡层20的电位在半导体装置100内变得更均匀。
n型表面半导体区域30在第1面4中以将阳极层32包围的方式设置。n型表面半导体区域30的杂质浓度比半导体基板2的n型杂质浓度高。并且，如上述那样，p型半导体区域40的p型杂质浓度在距第1面4的基板在深度方向的规定的距离d1处具有最大值，而规定的距离d1比n型表面半导体区域30的厚度d2长。
n型的阴极层24设置在第2面6中。阴极层24的n型杂质浓度比半导体基板2的n型杂质浓度高。
阴极电极26与阴极层24电气地连接。阴极电极26例如由铝(Al)形成。
图4是表示本实施方式的半导体装置100的制造工艺的一部分的示意剖视图。图4是表示本实施方式的半导体装置100的制造工艺中的p型半导体区域40的制造工艺的图。
在图4中，在第1面4之上形成有多个遮蔽件90。这里，遮蔽件90的x方向的宽度分别相等。另一方面，各个遮蔽件90的间隔在更靠近半导体基板2的内侧的区域以d11相等。另一方面，在更外侧分别为d12、d13、d14、d15及d16。另外，是d11>d12>d13>d14>d15>d16。这里，将p型杂质打入，然后将遮蔽件90通过灰化等除去并进行热处理。将各个遮蔽件90的间隔都设为较小，以使得打入到各个遮蔽件90之间的p型杂质的分布相互重叠。在各个遮蔽件90的间隔是d11的部分，形成镇流电阻区域42。另一方面，在各个遮蔽件90的间隔是d12、d13、d14、d15及d16的部分，形成VLD区域44。
由于遮蔽件90的间隔以d11相等，所以镇流电阻区域42的与第1面4平行的面内的p型杂质浓度无梯度而是一定的。另一方面，由于遮蔽件90的间隔以d12>d13>d14>d15>d16随着向端部2b前进而变窄，所以VLD区域44的与第1面4平行的面内的p型杂质浓度的梯度以比镇流电阻区域42大的梯度朝向半导体基板2的端部2b变低。另外，根据热处理的程度及遮蔽件90的形成方式，镇流电阻区域42及VLD区域44中的p型杂质浓度的分布也有如图3所示那样在各处形成有p型杂质的浓度变低的地方的情况。此外，也有在各处不形成p型杂质的浓度变低的地方、通过热处理成为更均匀的分布的情况。不论怎样，更宏观地看，在VLD区域44中都形成为，与第1面4平行的面内的p型杂质的梯度以比镇流电阻区域42大的梯度朝向半导体基板的端部2b变低。
例如，通过使用市面销售的高加速度离子注入装置将p型杂质注入而形成p型半导体区域40，通过使用通常的离子注入装置将n型杂质注入而形成n型表面半导体区域30。由此，能够使规定的距离d1比n型表面半导体区域30的厚度d2长。
另外，p型半导体区域40及n型表面半导体区域30的制造方法并不限定于上述的方法。
接着，说明本实施方式的作用效果。
图5的(a)及图5的(b)是作为本实施方式的比较形态的半导体装置800的主要部分的示意图。在半导体装置800中，设置有VLD区域44。此外，代替镇流电阻区域42而设置有p型杂质浓度更高的p+型的区域38。另一方面，没有设置p+型半导体区域28。此外，场板电极14与未图示的阳极电极10一体成型，不是浮动式的。
场板电极14的下方的p+型的区域38变得不易耗尽层化。因此，在对半导体装置800施加了逆向电压的情况下，在场板电极14的端部的下方，局部地发生雪崩击穿。通过雪崩击穿产生的空穴穿过p+型的区域38而局部地向未图示的阳极电极10的方向流动。此时，由于p+型的区域38的电阻非常低，所以成为局部的电流密度较高的状态，所以有半导体装置800局部地受到损伤的问题。此外，由于可能发生被称作骤回(折返、snapback)的局部地流动的空穴进一步集中而流动的现象，所以空穴更局部地集中而流动。因此，半导体装置800的局部性的损伤进一步变大。
图6的(a)及图6的(b)是作为本实施方式的比较形态的半导体装置900的主要部的示意图。在半导体装置900中，设置有镇流电阻区域42。另一方面，没有设置p+型半导体区域28。此外，场板电极14与未图示的阳极电极10一体成型，不是浮动式的。
由于镇流电阻区域42的p型杂质浓度比p+型的区域38的p型杂质浓度低而电阻较高，所以不发生半导体装置800那样的由骤回带来的电流集中。但是，由于发生局部性的雪崩击穿，所以可能发生局部的电流密度较高的状态。因此，还是有半导体装置900局部地受到损伤的问题。
图7的(a)及图7的(b)是说明本实施方式的半导体装置100的作用效果的图。
通过局部性的雪崩击穿产生的空穴向纸面左侧流动。第2镇流电阻区域部分42b的p型杂质浓度比p+型的区域38的p型杂质浓度低。由此，电阻成分较高，所以不易发生由骤回带来的电流集中。另一方面，进入到p+型半导体区域28中的空穴经由场板电极14而向y方向扩展。
结果，在第1镇流电阻区域部分42a中，雪崩电流更均匀地流动。由此，不发生局部性的电流集中，所以能够提高半导体装置100的耐压。
另外，根据设计，有镇流电阻区域作为VLD区域发挥功能、或VLD区域作为镇流电阻区域发挥功能的情况。因此，半导体装置100的动作并不限定于上述。
在半导体装置100的内置的封装的树脂等中含有离子。如果在半导体装置100的动作中该离子混入到半导体装置100内，则有耐压变动的问题。例如，如果具有负电荷的离子混入，则在第1绝缘膜12与半导体基板2的界面处出现正电荷。这样，第1绝缘膜12与半导体基板2的界面处的n型杂质浓度看起来变低。所以，设置n型表面半导体区域30而进行补偿。
通过使距第1面4在基板深度方向的规定的距离d1比n型表面半导体区域30的厚度d2长，能够将由n型表面半导体区域30的n型杂质带来的效果不由p型杂质抵消，该距第1面4在基板深度方向的规定的距离d1处是p型半导体区域40的p型杂质浓度具有最大值的位置。
根据本实施方式的半导体装置，能够提供耐压较高的半导体装置。
(第2实施方式)
在本实施方式的半导体装置中，设置在第3半导体区域的内侧的第5半导体区域具有：第8半导体区域，设置在距半导体基板的角部较近的部分处；第9半导体区域，邻接于第8半导体区域而设置，且第2导电型杂质浓度比第8半导体区域高，在这一点上与第1实施方式不同。这里，关于与第1实施方式重复的点省略记载。
图8是本实施方式的半导体装置110的俯视图。在图8中，省略阳极电极10、第1绝缘膜12、场板电极14、阻挡电极18、阻挡层20、n型表面半导体区域30和VLD区域44的记载，而表示有p+型半导体区域28、阳极层32和镇流电阻区域42。
第1镇流电阻区域部分42a在距角部2a较近的部分处具有第1镇流电阻区域部分42a2(第8半导体区域的一例)。此外，具有邻接于第1镇流电阻区域部分42a2而设置，且p型杂质浓度比第1镇流电阻区域部分42a2高的第1镇流电阻区域部分42a1(第9半导体区域的一例)。
通常，距角部2a较近的部分其电流密度容易变高。特别是，距角部2a较近的部分如图8所示，第2镇流电阻区域部分42b2具有曲率。电流更容易集中到具有这样的曲率的部分。所以，使第1镇流电阻区域部分42a1的p型杂质浓度比第1镇流电阻区域部分42a2高，使电流关于距角部2a较近的部分相对不易流动。
另外，关于第2镇流电阻区域部分42b1和第2镇流电阻区域部分42b2，也可以使p型杂质浓度相同而使雪崩电流均匀地留到p+型半导体区域28中。此外，也可以使第2镇流电阻区域部分42b2的p型杂质浓度更低，使电流关于距角部2a较近的部分相对更不易流动。
根据本实施方式的半导体装置，能够提供耐压较高的半导体装置。
(第3实施方式)
在本实施方式的半导体装置中，第1电极具有：第1电极部分；和第2电极部分，邻接于第1电极部分而设置，且与上述半导体基板的端部的距离比上述第1电极部分长，在这一点上，与第1及第2实施方式不同。这里，关于与第1及第2实施方式重复的点省略记载。
图9是本实施方式的半导体装置120的示意俯视图。
场板电极14具有第1电极部分14a、和邻接于第1电极部分14a而设置的第2电极部分14b。相比第1电极部分14a与半导体基板2的端部2b的距离d21，第2电极部分14b与半导体基板2的端部2b的距离d22较长。
更具体地讲，本实施方式的场板电极14的外周部整体上具有波状的形状，使得半导体基板2的端部2b与场板电极14的外周部的距离不同的部分尽可能变多。这是为了，通过使发生雪崩击穿的部位尽可能分散，使得雪崩电流不集中。
根据本实施方式的半导体装置，能够提供耐压较高的半导体装置。
(第4实施方式)
本实施方式的半导体装置在还具备以下部分的点上与第1至第3实施方式不同：第4电极(栅极电极62的一例)，设置在上述第1面中；第2绝缘膜(栅极绝缘膜64的一例)，设置在第4电极与第1半导体区域(基极层68的一例)之间；第10半导体区域(发射极层66的一例)，在第1半导体区域内且设置在第1半导体区域的上部，第1导电型杂质浓度比半导体基板高；第5电极(发射极电极70的一例)，与第10半导体区域电气地连接；第2导电型的第11半导体区域(集电极层74的一例)，设置在半导体基板的第2面中；以及第6电极(集电极电极76的一例)，与第11半导体区域电气地连接。这里，关于与第1至第3实施方式重复的点省略记载。
图10是本实施方式的半导体装置200的主要部的示意剖视图。半导体装置200是IGBT。
根据本实施方式的半导体装置，能够提供耐压较高的半导体装置。
说明了本发明的一些实施方式及实施例，但这些实施方式及实施例是作为例子提示的，不是要限定发明的范围。这些新的实施方式能够以其他各种各样的形态实施，在不脱离发明的主旨的范围内能够进行各种各样的省略、替换、变更。这些实施方式及其变形包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明和其等价的范围中。

Claims (9)

1.一种半导体装置，其特征在于，
具备：
第1导电型的半导体基板，具有第1面和第2面；
第2导电型的第1半导体区域，设置在上述第1面中；
第2导电型的第2半导体区域，在上述第1面中，在上述第1半导体区域的周围以将上述第1半导体区域包围的方式设置；
第2导电型的第3半导体区域，在上述第1面中，在上述第2半导体区域内以将上述第1半导体区域包围的方式设置，第2导电型杂质浓度比上述第2半导体区域高；
第1绝缘膜，在上述第2半导体区域之上以将上述第1半导体区域包围的方式设置，在上述第3半导体区域之上具有孔；以及
第1电极，设置在上述第1绝缘膜之上，经由上述孔与上述第3半导体区域电气地连接。
2.如权利要求1所述的半导体装置，其特征在于，
在上述第1面中，还具备以将上述第1半导体区域包围的方式设置、第1导电型杂质浓度比上述半导体基板高的第1导电型的第4半导体区域。
3.如权利要求2所述的半导体装置，其特征在于，
上述第2半导体区域的第2导电型杂质浓度在距上述第1面的在基板深度方向的规定的距离处具有最大值，上述规定的距离比上述第4半导体区域的厚度长。
4.如权利要求1～3中任一项所述的半导体装置，其特征在于，
上述第2半导体区域具有：
第5半导体区域，在上述第1半导体区域的周围以将上述第1半导体区域包围的方式设置；以及
第6半导体区域，在上述第5半导体区域的周围以将上述第5半导体区域包围的方式设置，在与上述第1面平行的面内的第2导电型杂质浓度朝向上述半导体基板的端部以比上述第5半导体区域大的梯度变低。
5.如权利要求4所述的半导体装置，其特征在于，
设置在上述第3半导体区域的内侧的上述第5半导体区域具有：
第8半导体区域，设置在距上述半导体基板的角部近的部分处；以及
第9半导体区域，与上述第8半导体区域邻接而设置，且第2导电型杂质浓度比上述第8半导体区域高。
6.如权利要求1～3中任一项所述的半导体装置，其特征在于，
上述第1电极具有：
第1电极部分；以及
第2电极部分，与上述第1电极部分邻接而设置，且与上述半导体基板的端部的距离比上述第1电极部分长。
7.如权利要求1～3中任一项所述的半导体装置，其特征在于，
还具备：
第2电极，与上述第1半导体区域电气地连接，与上述第1电极相间隔而设置；以及
第7半导体区域，设置在上述半导体基板的第2面中，第1导电型杂质浓度比上述半导体基板高；以及
第3电极，与上述第7半导体区域电气地连接。
8.如权利要求1～3中任一项所述的半导体装置，其特征在于，
还具备：
第4电极，设置在上述第1面中；
第2绝缘膜，设置在上述第4电极与上述第1半导体区域之间；
第10半导体区域，在上述第1半导体区域内且设置在上述第1半导体区域的上部，第1导电型杂质浓度比上述半导体基板高；
第5电极，与上述第10半导体区域电气地连接；
第2导电型的第11半导体区域，设置在上述半导体基板的第2面中；以及
第6电极，与上述第11半导体区域电气地连接。
9.一种半导体装置，其特征在于，
具备：
第1导电型的半导体基板，具有第1面和第2面；
第2导电型的第1半导体区域，设置在上述第1面中；
第2导电型的第2半导体区域，在上述第1面中，在上述第1半导体区域的周围以将上述第1半导体区域包围的方式设置；
第1绝缘膜，在上述第2半导体区域之上以将上述第1半导体区域包围的方式设置，且具有孔；
第1电极，设置在上述第1绝缘膜之上，经由上述孔与上述第2半导体区域电气地连接；以及
第2电极，与上述第1半导体区域电气地连接，与上述第1电极相间隔而设置。
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